DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed 11 November 2025, with respect to the rejection(s) of claim(s) 18-19 under 35 USC 112(b), and the claims 1-5, 8-9, and 36 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Park and newly discovered reference Kyoung June Jung et al. (US 2021/0202666 A1; hereinafter Jung). The rejections are detailed below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9, and 36-40 are rejected under 35 U.S.C. 103 as being unpatentable over Hyunae Park et al. (US 2020/0176542 A1; hereinafter Park) in view of Kyoung June Jung et al. (US 2021/0202666 A1; hereinafter Jung).
PNG
media_image1.png
705
994
media_image1.png
Greyscale
Regarding Claim 1, Park teaches a display panel (Fig. 1, 10; ¶0096), comprising:
a light transmission region (OA; ¶0105);
a display region (DA; ¶0091), arranged around the light transmission region (OA) or at a side of the light transmission region (as shown in Fig. 1);
a bezel region (NDA1), located between the light transmission region (OA) and the display region (DA) (as shown in Fig. 1);
a plurality of data lines (Fig. 8; DL1-DL8; hereinafter DL; ¶0138), located on a base substrate (in view of Fig. 5 and Fig. 5B; 100; ¶0130), comprising a plurality of bezel region data lines (annotated Fig. 8; BR-DL) located in the bezel region (NDA1) and a plurality of display region data lines (annotated Fig. 8; DR-DL) located in the display region (DA), and the plurality of bezel region data lines (BR-DL) being connected with the plurality of display region data lines (DR-DL), respectively (as shown in Fig. 8); and
a plurality of gate lines (Fig. 8; SWL1-SWL7; hereinafter SWL; connected to a gate; ¶0138) located on the base substrate (100), comprising a plurality of bezel region gate lines (annotated Fig. 8; BR-SWL) located in the bezel region (NDA1) and a plurality of display region gate lines (annotated Fig. 8; DR-SWL) located in the display region (DA), and the plurality of bezel region gate lines (BR-SWL) being connected with the plurality of display region gate lines (DR-SWL), respectively (as shown in Fig. 8),
wherein each of the plurality of bezel region gate lines (BR-SWL) comprises a first portion (1P-SWL), each of the plurality of bezel region data lines (BR-DL) comprises a first portion (1P-DL), an extending direction (around OA) of the first portion (1P-SWL) of the bezel region gate line (BR-SWL) is same as an extending direction (around OA) of the first portion (1P-DL) of the bezel region data line (BR-DL) (as shown in annotated Fig. 8), the first portion (1P-SWL) of the bezel region gate line (BR-SWL) overlaps with the first portion (1P-DL) of one of the plurality of bezel region data lines (BR-DL) in a direction perpendicular (z direction) to the base substrate (100) (as shown in annotated Fig. 8 indicated by the circled area), and the first portion of the bezel region data line (1P-DL) comprises a first curved portion (curved portion of 1P-DL as shown in annotated Fig. 8; hereinafter 1P-DLC) and extends around the light transmission region (OA),
the display panel (10) further comprises a plurality of light emitting control signal lines (Fig. 8; EL1-EL8; hereinafter EL; which is an emission control line connected to pixel P; ¶0128), the plurality of light emitting control signal lines (EL) comprise a plurality of bezel region light emitting control signal lines (annotated Fig. 8; BR-EL) located in the bezel region (NDA1) and a plurality of display region light emitting control signal lines (annotated Fig. 8; DR-EL) located in the display region (DA), both of a portion of each of the plurality of display region gate lines (DR-SWL) and a portion of each of the plurality of display region light emitting control signal lines (DR-LE) extend in a first direction (x direction) (as shown in Fig. 8), and each of the plurality of display region data lines (DR-DL) extends in a second direction (y direction) (as shown in Fig. 8), the first direction and the second direction are parallel to the base substrate, and the first direction (x direction) intersects with the second direction (y direction) (as shown in Fig. 8);
the plurality of bezel region light emitting control signal lines (BR-EL) are connected with the plurality of display region light emitting control signal lines (DR-EL), respectively (as shown in Park Fig. 8), each of the plurality of bezel region light emitting control signal lines (BR-EL) comprises a first portion (Park; annotated Fig. 8; 1P-EL), an extending direction (around OA) of the first portion of the bezel region light emitting control signal line (1P-EL) is same as the extending direction (around OA) of the first portion of the bezel region data line (1P-DL), and the first portion of the bezel region light emitting control signal line (1P-EL) overlaps with the first portion of one of the plurality of bezel region data lines (1P-DL) in the direction perpendicular to the base substrate (z direction) (as shown by the square in Park annotated Fig. 8), and the first portion of the bezel region light emitting control signal line (1P-EL) comprises a second curved portion (curved portion of 1P-EL; hereinafter 1P-ELC) and extends around the light transmission region (OA) (as shown in Fig. 8),
the display panel (10) further comprises a plurality of display pixel units (P; ¶0125), each of the plurality of display pixel units (P) comprises a light emitting unit (Fig. 6; organic light emitting diode OLED; ¶0133) and a pixel circuit structure (Fig. 6; pixel circuit PC) that provides a driving current for the light emitting unit (as described in ¶0134; furthermore this limitation of “providing a driving current” is drawn toward the intended use and imparts no limitation to the structure of the device), each of the plurality of light emitting control signal lines (EL) is configured to provide a light emitting control signal (EM; ¶0136; furthermore this limitation of “configured to provide a light emitting control signal” is the intended use of the connection and imparts no limitation on the structure of the device) to the display pixel unit (P) (as described in ¶0128), each of the plurality of data lines (DL) is configured to provide a data signal (Dm; ¶0136; furthermore this limitation “configured to provide a data signal” imparts no further limitation on the structure of the device as the type of signal is it’s intended use) to the pixel circuit structure (PC) (as shown in Fig. 6 and described in ¶0137), each of the plurality of gate lines (SWL) is configured to provide at least one of a scan signal (GW; ¶0136) or a reset signal to the pixel circuit structure (PC) (as shown in Fig. 6 and described in ¶0136) (furthermore this limitation “configured to provide a scan or reset signal” imparts no further limitation on the structure of the device as the type of signal is it’s intended use),
wherein the bezel region data lines that are adjacent to each other comprise a first bezel region data line (BR-DL5) and a second bezel region data line (BR-DL6), and
wherein the bezel region gate line (BR-SWL) overlaps with the first bezel region data line (BR-DL5), the bezel region light emitting control signal line (BR-EL) overlaps with the second bezel region data line (BR-DL6) (as shown in annotated Park Fig. 8).
Park does not expressly disclose wherein the first portion of the bezel region data line comprises a first curved portion (1P-DLC) that overlaps with the first portion of the bezel region gate line (1P-SWL), and the first portion of the bezel region light emitting control signal line comprises a second curved portion (1P-ELC) that overlaps with the first portion of the bezel region data line (1P-DL);
the first bezel region data line is closer to the base substrate than the second bezel region data line, and a first insulation layer is arranged between the first bezel region data line and the second bezel region data line, and
the first bezel region data line, the second bezel region data line, the bezel region gate line, and the bezel region light emitting control signal line are located in four different layers.
In the same field of endeavor, Jung teaches a substantially similar device comprising (Figs. 1-9; ¶0028-¶0036):
a light transmission region (H1; ¶0052); a display region (DA; ¶0051), arranged around the light transmission region (H1) or at a side of the light transmission region (H1) (as shown in Fig. 1 and Fig. 4);
a bezel region (NDA2; ¶0051), located between the light transmission region (H1) and the display region (DA);
a plurality of data lines (plurality of data lines 124a/125a of Fig. 6 are the data lines SD1 from Fig. 3 in the region NDA2 as shown in the figures; ¶0061; ¶0064; ¶0086), located on a base substrate (111; ¶0068);
a plurality of gate lines (gate lines 123a as shown in view of Fig. 6, but not illustrated in Fig. 3 as described in ¶0061, ¶0064; ¶0086) located on the base substrate (111);
a plurality of light emitting control signal lines (emission lines EM from Fig. 3; ¶0061; which are the emission lines 121a of Fig. 6; ¶0086);
the data lines (124a/125a {SD1}), the gate lines (123a), and the light emitting control signal lines (121a {EM}) comprise curved portions that overlap each other in the bezel region (NDA2) (Jung; ¶0061-¶0065 in view of Figs. 3, 4, and 6);
wherein bezel region data lines (124a/125a {SD1}) that are adjacent to each other comprise a first bezel region data line (Fig. 6; 124a left) and a second bezel region data line (Fig. 6; 125a middle)
the first bezel region data line (124a left) is closer to the base substrate (111) than the second bezel region data line (125a middle) (as shown in Fig. 6), and a first insulation layer (116; ¶0082) is arranged between the first bezel region data line and the second bezel region data line (as shown in Fig. 6), and
the first bezel region data line (124a left), the second bezel region data line (125a middle), the bezel region gate line (123a), and the bezel region light emitting control signal line (121a) are located in four different layers (as shown in Fig. 6, each line is located in a different one of 4 layers).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Jung with those of Park in order to decrease the size of the non-display area around the light transmission region (as described in Jung ¶0064; ¶0108) while enabling freedom of design when routing lines (Jung; ¶0110) and ensuring parasitic capacitance between lines is reduced (Jung; ¶0109) (which is for the same reasoning as in the instant application).
Regarding Claim 2, modified Park teaches the display panel according to claim 1, wherein a width of a part of the bezel region gate line (BR-SWL) overlapping with the bezel region data line (BR-DL) is less than or equal to a width of the bezel region data line (BR-DL) (as shown in Fig. 8; where the lines overlap, BR-SWL is less wide than BR-DL).
Regarding Claim 3, modified Park teaches the display panel according to claim 1, wherein a length of a part of the bezel region gate line (BR-SWL) overlapping with the bezel region data line (BR-DL) along an extending direction of the part of the bezel region gate line (BR-SWL) is less than a length of the first portion of the bezel region gate line (1P-SWL) (as shown in annotated Fig. 8).
Regarding Claim 4, modified Park teaches the display panel according to claim 1, wherein a length of a part of the bezel region gate line (BR-SWL) overlapping with the bezel region data line (BR-DL) along an extending direction of the part of the bezel region gate line (BR-SWL) (around OA) is greater than a width of the bezel region data line (BR-DL) (as modified by Jung, wherein a length of the curved portions of the bezel region data lines and bezel region gate lines that overlap each other is longer than a width of BR-DL).
Regarding Claim 5, modified Park teaches the display panel according to claim 1, wherein the plurality of light emitting control signal lines and the plurality of gate lines are alternately arranged (as shown in annotated Fig. 8 wherein EL and SWL are alternately arranged).
Regarding Claim 9, modified Park teaches the display panel according to claim 1, but Park does not expressly disclose wherein the second bezel region data line and the display region data line connected to the second bezel region data line are connected through a via hole penetrating the first insulation layer.
However, Jung teaches in ¶0099-¶0107 (in view of Figs. 9 and 13) that various lines may be located in different vertical layers, connected to each other by a via hole penetrating the insulation layer(s) between the two when transitioning from the display area (DA) to the bezel region (NDA2).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the second bezel region data line (BR-DL6) and the display region data line (DR-DL6) connected to the second bezel region data line be connected through a via hole penetrating the first insulation layer in the manner of Jung in order to reduce the size of the bezel region (Jung; ¶0108) while enabling freedom of design when routing lines (Jung; ¶0110) and ensuring parasitic capacitance between lines is reduced (Jung; ¶0109) (which is the same reasoning for doing so as in the instant application).
Furthermore, Applicant has not presented persuasive evidence that the claimed orientation/arrangement is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed orientation shape). Also, the applicant has not shown that the claimed orientation/arrangement produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. It would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the display device of Park by re-arranging the lines in the manner of Jung with a reasonable expectation of success (benefits of Jung; ¶0108-¶0110) since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950), see MPEP 2144.04 VI.
Regarding Claim 36, modified Park teaches a display device (Park; Fig. 1; 1; ¶0096), comprising the display panel (10) according to claim 1 (as described in Park ¶0096).
PNG
media_image2.png
386
767
media_image2.png
Greyscale
Regarding Claim 37, modified Park teaches the display panel according to claim 1 (as modified by Jung, see annotated Jung Fig. 6), wherein the bezel region gate line (123a) is located in a first conductive pattern layer (1CP), the bezel region light emitting control signal line (121a) is located in a second conductive pattern layer (2CP), the first bezel region data line (124a) is located in a third conductive pattern layer (3CP), the second bezel region data line (125a) is located in a fourth conductive pattern layer (4CP),
a gate insulation layer (113+114; which insulates the top/bottom of the gate electrode and are of the same material; ¶0073 and ¶0076) is located between the first conductive pattern layer (1CP) and the second conductive pattern layer (2CP),
an interlayer insulation layer (115; ¶0078) is located between the second conductive pattern layer (2CP) and the third conductive pattern layer (3CP),
the gate insulation layer (part of 113+114) and the interlayer insulation layer (115) are located between the bezel region gate line (123a) and the first bezel region data line (124a), and
the interlayer insulation layer (115) and the first insulation layer (116) are located between the bezel region light emitting control signal line (121a) and the second bezel region data line (125a).
Furthermore, Applicant has not presented persuasive evidence that the claimed orientation/arrangement is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed orientation/configuration). Also, the applicant has not shown that the claimed orientation/arrangement produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. It would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the display device of Park by re-arranging the lines/insulation layers in the manner of Jung with a reasonable expectation of success (benefits of Jung; ¶0108-¶0110, which is the same reasons as in the instant application) since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950), see MPEP 2144.04 VI.
Regarding Claim 38, modified Park teaches the display panel according to claim 37, wherein a sum of thicknesses (t1) of the gate insulation layer (113+114) and the interlayer insulation layer (115) that are located between the bezel region gate line (123a) and the first bezel region data line (124a) is less than a sum of thicknesses (t2) of the interlayer insulation layer (115) and the first insulation layer (116) that are located between the bezel region light emitting control signal line (121a) and the second bezel region data line (125a) (as shown in Jung annotated Fig. 6; t1 < t2).
Furthermore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adjust the thicknesses of the insulation layers between the conductive lines to optimize the reduction in parasitic capacitance and RC delay (as disclosed in Jung ¶0089-¶0092).
Regarding Claim 39, modified Park teaches the display panel according to claim 37, wherein the second conductive pattern (2CP) layer is closer to the base substrate than the third conductive pattern layer (3CP).
Modified Park does not expressly disclose wherein the first conductive pattern layer is closer to the base substrate than the second conductive pattern layer.
However, Applicant has not presented persuasive evidence that the claimed orientation/arrangement is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed orientation shape). Also, the applicant has not shown that the claimed orientation/arrangement produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the display device of modified Park by re-arranging the lines/insulation layers to arrive at the claimed limitation with a reasonable expectation of success, while obtaining the benefits of reducing the size of the bezel region (Jung; ¶0108), enabling freedom of design when routing lines (Jung; ¶0110), and ensuring parasitic capacitance between lines is reduced (Jung; ¶0109) (which is the same reasoning for doing so as in the instant application), since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950), see MPEP 2144.04 VI.
Regarding Claim 40, modified Jung teaches the display panel according to claim 37, but does not expressly disclose wherein a thickness of the gate insulation layer (113+114) is less than a thickness of the interlayer insulation layer (115), and the thickness of the interlayer insulation layer (115) is less than a thickness of the first insulation layer (116).
However, Jung establishes that the parasitic capacitance between the wiring layers is related to the thickness of the insulation layers therebetween (Jung; ¶0089-¶0092). Absent any evidence of new or unexpected results, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adjust the thicknesses of the various insulation layers between the conductive lines to optimize the known result of a reduction in parasitic capacitance and RC delay (as disclosed in Jung ¶0089-¶0092). "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898