DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/02/2026 has been entered.
Response to Amendment/Argument
Applicant’s arguments, see remarks, filed 03/02/2026, with respect to the rejection of claim 9 under 35 U.S.C. 112(b) have been fully considered and are persuasive. The rejection of claim 9 has been withdrawn.
Applicant’s arguments, see remarks, filed 03/02/2026, with respect to the rejection(s) of claim(s) 1-11 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of an updated prior art search.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 9 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (CN-109698188-A – hereinafter Zhou) in view of Kuan et al. (US-10879192-B1 – hereinafter Kuan), and further in view of Kim et al. (US-20210398869-A1 – hereinafter Kim), and further in view of Min et al. (US-20200312783-A1 – hereinafter Min).
Regarding claim 9, Zhou teaches a packaging structure (Fig.13n 200; ¶0082), comprising:
a pre-encapsulation panel (Fig.13n middle section of 200 containing a chip), wherein the pre-encapsulation panel (mid-section of 200) includes an encapsulation layer (Fig.13n 2021; ¶0089), the encapsulation layer (2021) contains a plurality of semiconductor chips (Fig.13n 10; ¶0086), each semiconductor chip (10) of the plurality of semiconductor chips includes a functional surface (bottom surface) and a non-functional surface (top surface) opposite to the functional surface, a plurality of pads (Fig.13n 1011; ¶0089) are formed on the functional surface (bottom surface), and the encapsulation layer (2021) exposes the plurality of pads (1011) on the functional surface (bottom surface);
a first shielding layer (Fig.13n 11’; ¶0132) disposed between a corresponding semiconductor chip (10) of the plurality of semiconductor chips (10) and the encapsulation layer (2021), wherein the first shielding layer (11’) covers the non-functional surface (bottom surface) and a sidewall surface of the corresponding semiconductor chip (10), and the first shielding layer (11’) is connected to the peripheral edge of the bottom shielding layer (11”); and
an external contact structure (Fig.13n external wiring to connect chip 10 to other components is clearly depicted) disposed on a back side of the pre-encapsulation panel (mid-section of 200) and connected to the corresponding pad of the plurality of pads (1011).
Zhou does not teach a dielectric layer deposited on the functional surface;
a first isolation layer deposited on the dielectric layer;
a second isolation layer deposited on the first isolation layer;
a bottom shielding layer and a plurality of second isolation layers, both deposited on the first isolation layer and interposing with each other, wherein:
each pad penetrates through the first isolation layer and a second isolation layer of the plurality of second isolation layers,
each second isolation layer encloses a corresponding pad of the plurality of pads to separate the corresponding pad from the bottom shielding layer; and
wherein a peripheral edge of the bottom shielding layer is flush with a surrounding sidewall of the corresponding semiconductor chip.
Kuan teaches a semiconductor chip (Fig.6B 212; Col.7 lines 1-22 of Kuan) with a dielectric layer (Fig.6B 216; Col.7 lines 1-22 of Kuan) disposed on a surface of the semiconductor chip (212 of Kuan) and surrounding conductive contacts (Fig.6B 214; Col.7 lines 1-22 of Kuan).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include this dielectric layer with the die taught by Zhou (10 of Zhou). A practitioner would have been motivated to make this modification for the benefit of providing protection (Col.7 lines 1-22 of Kuan) to the conductive contacts (214 of Kuan).
Zhou in view of Kuan does not teach a first isolation layer deposited on the dielectric layer;
a second isolation layer deposited on the first isolation layer;
a bottom shielding layer and a plurality of second isolation layers, both deposited on the first isolation layer and interposing with each other, wherein:
each pad penetrates through the first isolation layer and a second isolation layer of the plurality of second isolation layers,
each second isolation layer encloses a corresponding pad of the plurality of pads to separate the corresponding pad from the bottom shielding layer; and
wherein a peripheral edge of the bottom shielding layer is flush with a surrounding sidewall of the corresponding semiconductor chip.
Kim teaches a die package with a semiconductor chip (Fig.13 210; ¶0113 of Kim) with a first isolation layer (Fig.13 2311; ¶0167 of Kim);
a second isolation layer (Fig.13 2313; ¶0167 of Kim) deposited on the first isolation layer (2311 of Kim);
a bottom shielding layer (Fig.13 280; ¶0167 of Kim) and a plurality of second isolation layers (2313 of Kim), both deposited on the first isolation layer (2311 of Kim) and interposing with each other, wherein:
each pad (Fig.13 241; ¶0167) penetrates through the first isolation layer (2311 of Kim) and a second isolation layer (2313 of Kim) of the plurality of second isolation layers (2313 of Kim), and
each second isolation layer (2313 of Kim) encloses a corresponding pad (241 of Kim) of the plurality of pads (241 of Kim) to separate the corresponding pad (241 of Kim) from the bottom shielding layer (280 of Kim).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to implement the shield layer (280 of Kim) of Kim and accompanying isolation layers (2311 and 2313 of Kim) and pads (241 of Kim) to the structure taught by Zhou in view of Kuan to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of reducing electromagnetic interference (¶0166 of Kim), with the reference recommending insulating (¶0167-0168 of Kim) the shield layer (280 of Kim) from the pads (241 of Kim) with the isolation layers (2311 and 2313 of Kim).
Zhou in view of Kuan, and further in view of Kim does not teach wherein a peripheral edge of the bottom shielding layer is flush with a surrounding sidewall of the corresponding semiconductor chip.
Min teaches a semiconductor chip (Fig.2A 10; ¶0024 of Min) with a bottom shielding layer (Fig.2A 14; ¶0024 of Min) that is flush with a sidewall of the semiconductor chip (10 of Min) and connected to a top shielding layer (Fig.2A 20 and 30; ¶0024 of Min).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to implement the top and bottom shielding layer arrangement Min (Fig.2A of Min) to the embodiment taught by Zhou in view of Kuan, and further in view of Kim (Fig.13n of Zhou) to arrive at the claimed invention. This modification is obvious because it is a matter of design choice where all required components are already taught by Zhou in view of Kuan, and further in view of Kim.
Regarding claim 11, the aforementioned combination of Zhou in view of Kuan, and further in view of Kim, and further in view of Min from claim 9 teaches the packaging structure according to claim 9, further including:
a metal bump (Fig.13n of Zhou bump portions are depicted between pads 1011 and chip 10) formed on the pad (1011 of Zhou).
Claim(s) 1 and 3-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Miwa (CN-107114005-A), and further in view of Kuan, and further in view of Kim, and further in view of Min.
Regarding claim 1, Zhou teaches a packaging structure (Fig.13n 200; ¶0082), comprising:
a pre-encapsulation panel (Fig.13n middle section of 200 containing a chip), wherein the pre-encapsulation panel (mid-section of 200) includes an encapsulation layer (Fig.13n 2021; ¶0089), the encapsulation layer (2021) contains a plurality of semiconductor chips (Fig.13n 10; ¶0086), each semiconductor chip (10) of the plurality of semiconductor chips includes a functional surface (bottom surface) and a non-functional surface (top surface) opposite to the functional surface (bottom surface), a plurality of pads (Fig.13n 1011; ¶0089) are formed on the functional surface (bottom surface), and the encapsulation layer (2021) exposes the plurality of pads (1011) on the functional surface (bottom surface);
a first shielding layer (Fig.13n 11’; ¶0132) disposed between a corresponding semiconductor chip (10) of the plurality of semiconductor chips and the encapsulation layer (2021), wherein the first shielding layer (11’) covers the non-functional surface (top surface) and a sidewall surface of the corresponding semiconductor chip (10); and
an external contact structure (Fig.13n external wiring to connect chip 10 to other components is clearly depicted) disposed on a back side of the pre-encapsulation panel (mid-section of 200) and connected to the corresponding pad (1011) of the plurality of pads.
Zhou does not teach a second shielding layer disposed between a corresponding semiconductor chip of the plurality of semiconductor chips and the encapsulation layer, wherein the second shielding layer is disposed between the first shielding layer and the encapsulation layer and fully covers a surface of the first shielding layer on the non-functional surface and the sidewall surface of the corresponding semiconductor chip;
a dielectric layer deposited on the functional surface;
a first isolation layer deposited on the dielectric layer;
a bottom shielding layer and a plurality of second isolation layers, both deposited on the first isolation layer and interposing with each other, wherein:
each pad penetrates through the first isolation layer and a second isolation layer of the plurality of second isolation layers,
each second isolation layer encloses a corresponding pad of the plurality of pads to separate the corresponding pad from the bottom shielding layer; and
a peripheral edge of the bottom shielding layer is flush with a surrounding sidewall of the corresponding semiconductor chip, and the peripheral edge of the bottom shielding layer is connected to the first shielding layer.
Miwa teaches a shielding layer (Fig.4 600; ¶0130 of Miwa) for covering a circuit module (abstract of Miwa) having a first layer (Fig.4 610; ¶0130) for shielding an electric field and a second layer (Fig.4 620; ¶0130) for shielding a magnetic field.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to implement the two-layered shield of Miwa (600 of Miwa) with the device taught by Zhou (200 of Zhou). A practitioner would have been motivated to make this modification for the benefit of improved shielding property (abstract of Miwa).
Zhou in view of Miwa does not teach a dielectric layer deposited on the functional surface;
a first isolation layer deposited on the dielectric layer;
a bottom shielding layer and a plurality of second isolation layers, both deposited on the first isolation layer and interposing with each other, wherein:
each pad penetrates through the first isolation layer and a second isolation layer of the plurality of second isolation layers,
each second isolation layer encloses a corresponding pad of the plurality of pads to separate the corresponding pad from the bottom shielding layer; and
a peripheral edge of the bottom shielding layer is flush with a surrounding sidewall of the corresponding semiconductor chip, and the peripheral edge of the bottom shielding layer is connected to the first shielding layer.
Kuan teaches a semiconductor chip (Fig.6B 212; Col.7 lines 1-22 of Kuan) with a dielectric layer (Fig.6B 216; Col.7 lines 1-22 of Kuan) disposed on a surface of the semiconductor chip (212 of Kuan) and surrounding conductive contacts (Fig.6B 214; Col.7 lines 1-22 of Kuan).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include this dielectric layer with the die taught by Zhou (10 of Zhou). A practitioner would have been motivated to make this modification for the benefit of providing protection (Col.7 lines 1-22 of Kuan) to the conductive contacts (214 of Kuan).
Zhou in view of Miwa, and further in view of Kuan does not teach a first isolation layer deposited on the dielectric layer;
a bottom shielding layer and a plurality of second isolation layers, both deposited on the first isolation layer and interposing with each other, wherein:
each pad penetrates through the first isolation layer and a second isolation layer of the plurality of second isolation layers,
each second isolation layer encloses a corresponding pad of the plurality of pads to separate the corresponding pad from the bottom shielding layer; and
a peripheral edge of the bottom shielding layer is flush with a surrounding sidewall of the corresponding semiconductor chip, and the peripheral edge of the bottom shielding layer is connected to the first shielding layer.
Kim teaches a die package with a semiconductor chip (Fig.13 210; ¶0113 of Kim) with a first isolation layer (Fig.13 2311; ¶0167 of Kim);
a second isolation layer (Fig.13 2313; ¶0167 of Kim) deposited on the first isolation layer (2311 of Kim);
a bottom shielding layer (Fig.13 280; ¶0167 of Kim) and a plurality of second isolation layers (2313 of Kim), both deposited on the first isolation layer (2311 of Kim) and interposing with each other, wherein:
each pad (Fig.13 241; ¶0167) penetrates through the first isolation layer (2311 of Kim) and a second isolation layer (2313 of Kim) of the plurality of second isolation layers (2313 of Kim), and
each second isolation layer (2313 of Kim) encloses a corresponding pad (241 of Kim) of the plurality of pads (241 of Kim) to separate the corresponding pad (241 of Kim) from the bottom shielding layer (280 of Kim).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to implement the shield layer (280 of Kim) of Kim and accompanying isolation layers (2311 and 2313 of Kim) and pads (241 of Kim) to the structure taught by Zhou in view of Kuan to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of reducing electromagnetic interference (¶0166 of Kim), with the reference recommending insulating (¶0167-0168 of Kim) the shield layer (280 of Kim) from the pads (241 of Kim) with the isolation layers (2311 and 2313 of Kim).
Zhou in view of Miwa, and further in view of Kuan, and further in view of Kim does not teach a peripheral edge of the bottom shielding layer is flush with a surrounding sidewall of the corresponding semiconductor chip, and the peripheral edge of the bottom shielding layer is connected to the first shielding layer.
Min teaches a semiconductor chip (Fig.2A 10; ¶0024 of Min) with a bottom shielding layer (Fig.2A 14; ¶0024 of Min) that is flush with a sidewall of the semiconductor chip (10 of Min) and connected to a top shielding layer (Fig.2A 20 and 30; ¶0024 of Min).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to implement the top and bottom shielding layer arrangement Min (Fig.2A of Min) to the embodiment taught by Zhou in view of Kuan, and further in view of Kim (Fig.13n of Zhou) to arrive at the claimed invention. This modification is obvious because it is a matter of design choice where all required components are already taught by Zhou in view of Kuan, and further in view of Kim.
Regarding claim 3, the aforementioned combination of Zhou in view of Miwa, and further in view of Kuan, and further in view of Kim, and further in view of Min from claim 1 teaches the packaging structure according to claim 1, wherein:
one of the first shielding layer and the second shielding layer is an electric field shielding layer (¶0130 of Miwa); and
another of the first shielding layer and the second shielding layer is a magnetic field shielding layer (¶0130 of Miwa).
Regarding claim 4, the aforementioned combination of Zhou in view of Miwa, and further in view of Kuan, and further in view of Kim, and further in view of Min from claim 3 teaches the packaging structure according to claim 3, wherein:
a material of the electric field shielding layer includes copper, tungsten, or aluminum (abstract of Miwa); and
a material of the magnetic field shielding layer includes CoFeB alloy, CoFeTa alloy, NiFe alloy, Co, CoFe alloy, CoPt alloy, or an alloy of Ni, Co, and Fe (abstract of Miwa).
Regarding claim 5, the aforementioned combination of Zhou in view of Miwa, and further in view of Kuan, and further in view of Kim, and further in view of Min from claim 1 teaches the packaging structure according to claim 1, wherein:
the bottom shielding layer (11” of Zhou) covers the functional surface (bottom surface) of the corresponding semiconductor chip (10 of Zhou).
Regarding claim 6, the aforementioned combination of Zhou in view of Miwa, and further in view of Kuan, and further in view of Kim, and further in view of Min from claim 1 teaches the packaging structure according to claim 1, wherein:
the external contact structure (Fig.13n of Zhou external wiring to connect chip 10 to other components is clearly depicted) includes a rewiring layer (Fig.13n 2013; ¶0089 of Zhou) disposed on the back side of the pre-encapsulation panel (mid-section of 200 of Zhou) and connected to the corresponding pad (1011 of Zhou), and an external contact element (Fig.13n 2031; ¶0097 of Zhou) disposed on the rewiring layer (2013 of Zhou) and connected to the rewiring layer (2013 of Zhou).
Regarding claim 7, the aforementioned combination of Zhou in view of Miwa, and further in view of Kuan, and further in view of Kim, and further in view of Min from claim 6 teaches the packaging structure according to claim 6, further including:
an insulating layer (Fig.13n of Zhou isolation layer 2022 is also an insulating layer) formed on the back side (bottom side) of the pre-encapsulation panel (mid-section of 200 of Zhou), wherein the insulating layer (2022 of Zhou) has an opening that exposes a surface of the corresponding pad (1011 of Zhou), the rewiring layer (2013 of Zhou) is formed in the opening and on a partial surface of the insulating layer (2022 of Zhou), and the external contact element (2031 of Zhou) is disposed on a surface of the rewiring layer (2013 of Zhou) outside the opening.
Regarding claim 8, the aforementioned combination of Zhou in view of Miwa, and further in view of Kuan, and further in view of Kim, and further in view of Min from claim 7 teaches the packaging structure according to claim 7, further including:
a conductive contact structure (not shown in applicant’s disclosure, so Zhou is presumed to also teach this limitation) in the insulating layer (2022 of Zhou) for electrically connecting the first shielding layer (11’ of Zhou) and a portion of the rewiring layer (2013 of Zhou).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Kuan, and further in view of Kim, and further in view of Min, and further in view of Miwa.
Regarding claim 10, the aforementioned combination of Zhou in view of Kuan, and further in view of Kim, and further in view of Min from claim 9 teaches the packaging structure according to claim 9.
The aforementioned combination does not teach the package structure further including:
a second shielding layer disposed between the first shielding layer and the encapsulation layer, wherein the second shielding layer covers a surface of the first shielding layer.
Miwa teaches a shielding layer (Fig.4 600; ¶0130 of Miwa) for covering a circuit module (abstract of Miwa) having a first layer (Fig.4 610; ¶0130) for shielding an electric field and a second layer (Fig.4 620; ¶0130) for shielding a magnetic field.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to implement the two-layered shield of Miwa (600 of Miwa) with the device taught by Zhou (200 of Zhou) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of improved shielding property (abstract of Miwa).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Miwa, and further in view of Kuan, and further in view of Kim, and further in view of Min, and further in view of Duanmu et al. (CN-104779213-A – hereinafter Duanmu).
Regarding claim 2, the aforementioned combination of Zhou in view of Miwa, and further in view of Kuan, and further in view of Kim, and further in view of Min from claim 1 teaches the packaging structure according to claim 1.
The aforementioned combination does not teach wherein:
the surface of the first shielding layer has an ellipsoidal shape.
Duanmu teaches a packaging structure (Fig.3; ¶0028 of Duanmu) having a chip (Fig.3 5; ¶0028 of Duanmu) with a shielding layer (Fig.3 10; ¶0028 of Duanmu) that has an ellipsoidal shape.
Shape differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. Additionally, the Applicant has presented no discussion in the specification which convinces the Examiner that the particular shape of the shielding layer is anything more than one of numerous shapes a person of ordinary skill in the art would find obvious for the purpose of protecting from electrical and magnetic fields (In re Dailey, 149 USPQ 47 (CCPA 1976)). It appears that these changes produce no functional differences and therefore would have been obvious.
Conclusion
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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