DETAILED ACTION
This correspondence is in response to the communications received 03/03/2026. Claims 11-22 have been added. Claims 1, 10, 13, 14, 19, and 22 have been amended. Claims 1, 2, and 5-22 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment to claims 13, 14, 18, 19, and 22 overcomes the objections outlined in the previous Office Action. The objections are withdrawn.
Response to Arguments
Applicant’s arguments, see page-7, filed 02/04/2026, with respect to the 112(a) rejection of claims 1, 2, 10, and 11 have been fully considered and are persuasive. The 112(a) rejection of 12/15/2025 has been withdrawn.
Applicant's arguments filed 10/10/2025 with respect to the 103 rejection of claims 1, 6, and 10 have been fully considered but they are not persuasive.
Applicant asserts in the last paragraph of page 9 of the Remarks filed 02/04/2026 that Kawahito (US 2009/0114919 A1) and Fujii (US 2020/0169704 A1) whether considered individually or in combination do not disclose the features of newly amended claims 1 and 10. Specifically, that the references fail to disclose, teach, or suggest at least “an additional transistor provided between the additional capacitance section and the plurality of charge storage sections”.
However, Kawahito does disclose an additional transistor (“first read-out gate electrode 14b and the second read-out gate electrode 14a”, 14a and 14b are gates of unnamed transistors hereinafter “AT”) provided between the additional capacitance section and the plurality of charge storage sections (as seen in Fig. 13, 14a is between 26a and 27a, and 14b is between 26b and 27b, where “first buried charge read-out region 26b and the second buried charge read-out region 26a” ([0124]) are interpretated as the additional capacitance section, and “first buried charge-transfer region 27b and the second buried charge-transfer region 27a” ([0124]) are interpretated as the plurality of charge storage sections.
Therefore, Kawahito in combination with Fujii discloses the limitations of newly amended claims 1 and 10.
Applicant asserts on page 10 of the Remarks filed 02/04/2026 that Kawahito (US 2009/0114919 A1), Fujii (US 2020/0169704 A1), and Nakata (US 2021/0159260 A1) whether considered individually or in combination do not disclose the features of claim 6. Specifically, that the references do not explicitly recite “wherein a distance between the trench to a first transistor of the plurality of transfer sections is equal to a distance between the trench and a second transistor of the plurality of transfer sections”.
However as discussed in the previous Office Action, Fig. 2 of Nakata shows the trench filled by “light-shielding members 106 and 107” as having a line of symmetry across a horizontal line bisecting the device. Fig. 13(a) of Kawahito also shows “TOF pixel circuit 81” as having a horizontal line of symmetry shown as “LS”. Substitution of the trench of Nakata into Kawahito would then include aligning the lines of symmetry as Nakata shows “photoelectric conversion unit 104”, “charge holding portion 105”, and “transfer gate 103” as being centered between the upper and lower portions of 106. Thus, the distance between the trench of Nakata to the first transistor of the plurality of transfer sections represented by 16b of Kawahito is equal to the distance between the trench of Nakata to the second transistor of the plurality of transfer sections represented by 16a of Kawahito.
Therefore, Kawahito in combination with Fujii and Nakata discloses the limitations of claim 6.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, an imaging element ("pixel 50c"), comprising:
a photoelectric converting section ("photodiode 61" or "PD 61") configured to perform photoelectric conversion;
a plurality of charge storage sections ("FD 63" where FD is "floating diffusion region") configured to store charge obtained by the photoelectric converting section;
a plurality of transfer sections ("transfer transistor 62") configured to transfer the charge from the photoelectric converting section to each of the plurality of charge storage sections,
wherein each of the charge storage sections is provided between a first gate of a transistor ("TG 62" where "The TG 62-1 is a gate portion of the transfer transistor 62-1, and the TG 62-2 is a gate portion of the transfer transistor 62-2" [0081]) included in a corresponding one of the transfer sections and a second gate ("a gate of the transistor for conversion efficiency switching 251 is represented as FDG 251", [0117]) provided at a position parallel to the first gate (as seen in Fig. 13, FDG 251 is provided at a position parallel to TG 62),
an additional capacitance section ("additional capacitance section 252") configured to add a capacitance to each charge storage section of the plurality of charge storage sections; and
an additional transistor ("transistor for conversion efficiency switching 251") provided between the additional capacitance section and the plurality of charge storage sections, (see Fig. 13) configured to add the additional capacitance section to each charge storage section of the plurality of charge storage sections,
wherein each charge storage section of the plurality of charge storage sections is provided between the first gate and the second gate included in the additional transistor (as seen in Fig. 13, each of FD 63 is between TG62 and FDG 251).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 8-14, 17, 18, 21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Kawahito (US 2009/0114919 A1) in view of Fujii (US 2020/0169704 A1).
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Regarding claim 1, Figs. 13(a) and 13(b) of Kawahito disclose an imaging element (“the semiconductor range-finding element serving as the TOF pixel circuit 81”, [0119]), comprising:
a photoelectric converting section (“light receiving gate electrode 11”, [0119]);
a plurality of charge storage sections (“the first buried charge-transfer region 27b and the second buried charge-transfer region 27a”, [0124]) configured to store charge obtained by the photoelectric converting section (“As a result, the signal charges are transferred to and accumulated in the first buried charge-transfer region 27b of the second conductivity type (n-type) and the second buried charge-transfer region 27a”, [0125], therefore 27b and 27a obtain the charge from 22 where the charge is generated);
a plurality of transfer sections (“The portion located just under the first transfer gate electrode 16b between the buried charge-generation region 22 and the first buried charge-transfer region 27b serves as the first transfer channel, and the portion located just under the second transfer gate electrode 16a between the buried charge-generation region 22 and the second buried charge-transfer region 27a serves as the second transfer channel”, [0148], this portion is denoted by “TSb” and “TSa” in Fig. 13(a)) configured to transfer the charge from the photoelectric converting section to each of the plurality of charge storage sections (“the first transfer gate electrode 16b and the second transfer gate electrode 16a electrostatically control the potentials in the first and second transfer channels through the insulating films 31 formed on the upper portions of the first and second transfer channels, respectively. Since the potentials in the first and second transfer channels are electrostatically controlled, the signal charges are transferred through the first and second transfer channels alternately in the parallel directions in the two stages (two rows), respectively. As a result, the signal charges are transferred to and accumulated in the first buried charge-transfer region 27b of the second conductivity type (n-type) and the second buried charge-transfer region 27a in the two stages (two rows) in the parallel directions, respectively”, [0148]), wherein each of the charge storage sections is provided between a first gate of a transistor (“the first transfer gate electrode 16b and the second transfer gate electrode 16a”, [0119]) included in a corresponding one of the transfer sections (as seen in Fig. 13(b), 16b is in the corresponding TS) and a second gate (“the first read-out gate electrode 14b and the second read-out gate electrode 14a”, [0124], as seen in Fig. 13(a), 27b and 27a are between 16b and 14b, and 16a and 14a, respectively) provided at a position parallel to the first gate (as seen in Fig. 13(a), 14b and 14a are parallel to 16b and 16a, respectively);
an additional capacitance section (together “first buried charge read-out region 26b and the second buried charge read-out region 26a”, [0124], form an additional capacitance section) configured to add a capacitance to each charge storage section of the plurality of charge storage sections (“Then, when the first read-out gate electrode 14b and the second read-out gate electrode 14a are opened, the charges which are accumulated in the first buried charge-transfer region 27b and the second buried charge-transfer region 27a are all transferred to the first buried charge read-out region 26b and the second buried charge read-out region 26a”, [0050]); and
an additional transistor (“first read-out gate electrode 14b and the second read-out gate electrode 14a”, [0124], 14a and 14b are gates of unnamed transistors hereinafter “AT”) provided between the additional capacitance section and the plurality of charge storage sections (as seen in Fig. 13(b), 14a is between 26a and 27a, and 14b is between 26b and 27b), configured to add the additional capacitance section to each charge storage section of the plurality of charge storage sections (as discussed above, 14a and 14b control the charge transfer between 26a/26b and 27a/27b, thus 14a and 14b add the charge storage capacity of 26a/26b to 27a/27b),
wherein each charge storage section of the plurality of charge storage sections is provided between the first gate and the second gate included in the additional transistor (as seen in Figs. 13(a) and 13(b), 27a/27b is provided between 16a/16b and 14a/14b).
Kawahito fails to specify “a photoelectric converting section configured to perform photoelectric conversion.”
However, in a similar field of endeavor, Fujii teaches a photoelectric converting section configured to perform photoelectric conversion (“a photoelectric conversion section that photoelectrically converts received light”, [0184], the photoelectric conversion section of Fujii is equivalent to “the buried charge-generation region 22” of Kawahito).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a photoelectric converting section configured to perform photoelectric conversion” as taught by Fujii in the system of Kawahito for the purpose of transforming an optical signal into a digital signal.
Regarding claim 2, Figs. 13(a) and 13(b) of Kawahito in combination with Fujii disclose the imaging element according to claim 1, Figs. 13(a) and 13(b) of Kawahito further disclose wherein the second gate includes a gate of a reset transistor configured to reset each charge storage section (as mentioned previously, “when the first read-out gate electrode 14b and the second read-out gate electrode 14a are opened, the charges which are accumulated in the first buried charge-transfer region 27b and the second buried charge-transfer region 27a are all transferred to the first buried charge read-out region 26b and the second buried charge read-out region 26a”, [0050]”, as all the accumulated charges in 27a/27b are transferred when 14a/14b are opened, 14a/14b function as the gate of a reset transistor).
Regarding claim 5, Figs. 13(a) and 13(b) of Kawahito in combination with Fujii disclose the imaging element according to claim 1, Figs. 13(a) and 13(b) of Kawahito further disclose wherein the additional capacitance section is provided between the second gate and a third gate provided in an adjacent pixel (“FIG. 13 (a) is a schematic plan view describing a configuration of a semiconductor range-finding element serving as a part of pixels in a solid-state imaging device”, [0032], thus Fig. 13 (a) represents a single pixel in a larger array and “first reset gate electrode 13b and second reset gate electrode 13a”, [0122], are a third gate in each pixel, therefore a first pixel’s 26a/26b are provided between the first pixel’s 14a/14b and a second pixel’s 13a/13b where the second pixel is located to the right of the first pixel as seen in Fig. 13a).
Regarding claim 8, Figs. 13(a) and 13(b) of Kawahito in combination with Fujii disclose the imaging element according to claim 1, Figs. 13(a) and 13(b) of Kawahito further disclose wherein two of the charge storage sections are provided in a pixel (“wherein each of the pixels encompasses … (c) island-shaped first and second buried charge-transfer regions of the second conductivity type buried in a part of the surface of the semiconductor layer, separated by a part of the semiconductor layer from the buried charge-generation region, configured to accumulate signal charges transferred from the buried charge-generation region”, [0010], the “first and second buried charge-transfer regions” are 27b and 27a respectively).
Regarding claim 9, Figs. 13(a) and 13(b) of Kawahito in combination with Fujii disclose the imaging element according to claim 1, Figs. 13(a) and 13(b) of Kawahito further disclose wherein the plurality of charge storage sections is disposed in a line symmetric with the plurality of transfer sections (as seen in Fig. 13(a), 27b and 27a, and TSb and TSa are disposed around a line of symmetry “LS”).
Regarding claim 10, Fig. 1 of Kawahito discloses a distance measuring apparatus (“the semiconductor range-finding element serving as the TOF pixel circuit 81”, [0119]), comprising:
a light emitting section(“a light source 91”, [0042]) configured to emit irradiation light (“The light emitted as a repetitive pulse signal by a light source 91”, [0042]);
a light receiving section (“a pixel array area”, [0038], including X1,1 to Xn,m) configured to receive reflected light resulting from reflection of the irradiation light at a target object (“a target sample 92”, [0042], The light emitted as a repetitive pulse signal by a light source 91 in FIG. 1 is reflected by a target sample 92 and enters into the semiconductor photoelectric conversion element, [0042], the pixel array area contains the semiconductor photoelectric conversion elements); and
a computation section (“a TOF pixel circuit 81”, [0038], “peripheral circuit areas (94, 95, 96, and NC1 to NCm”, [0038], and “a first noise canceling circuit 84 and a second noise canceling circuit 83”, [0075]) configured to compute a distance to the target object based on a period of time from emission of the irradiation light until reception of the reflected light (“a light pulse reflected by a target sample enters as an optical signal in the surface buried region between the first and second charge transfer-barrier regions, and in the semiconductor layer just under the surface buried region, the optical signal is converted into the signal charges, and pulse signals are sequentially applied to the first and second transfer gate electrodes in synchronization with the light pulse so that a distance from the target sample is measured in accordance with a distribution ratio of the signal charges accumulated in the first and second potential wells”, [0009]), wherein an imaging element (“the semiconductor range-finding element serving as the TOF pixel circuit 81”, [0119]) disposed in the light receiving section (81 is in the pixel array area).
Fig. 1 of Kawahito fails to specify “wherein an imaging element disposed in the light receiving section includes:
a photoelectric converting section configured to perform photoelectric conversion;
a plurality of charge storage sections configured to store charge obtained by the photoelectric converting section;
a plurality of transfer sections configured to transfer the charge from the photoelectric converting section to each of the plurality of charge storage sections, and
wherein each of the charge storage sections is provided between a first gate of a transistor included in a corresponding one of the transfer sections and a second gate provided at a position parallel to the first gate,
an additional capacitance section configured to add a capacitance to each charge storage section of the plurality of charge storage sections; and
an additional transistor provided between the additional capacitance section and the plurality of charge storage sections, configured to add the additional capacitance section to each charge storage section of the plurality of charge storage sections,
wherein each charge storage section of the plurality of charge storage sections is provided between the first gate and the second gate included in the additional transistor.”
However, in a similar field of endeavor, Fujii teaches a photoelectric converting section configured to perform photoelectric conversion (“a photoelectric conversion section that photoelectrically converts received light”, [0184], the photoelectric conversion section of Fujii is equivalent to “the buried charge-generation region 22” of Kawahito).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a photoelectric converting section configured to perform photoelectric conversion” as taught by Fujii in the system of Kawahito for the purpose of transforming an optical signal into a digital signal
Fig. 1 of Kawahito in combination with Fuji fails to specify “wherein an imaging element disposed in the light receiving section includes:
a plurality of charge storage sections configured to store charge obtained by the photoelectric converting section;
a plurality of transfer sections configured to transfer the charge from the photoelectric converting section to each of the plurality of charge storage sections, and
wherein each of the charge storage sections is provided between a first gate of a transistor included in a corresponding one of the transfer sections and a second gate provided at a position parallel to the first gate,
an additional capacitance section configured to add a capacitance to each charge storage section of the plurality of charge storage sections; and
an additional transistor provided between the additional capacitance section and the plurality of charge storage sections, configured to add the additional capacitance section to each charge storage section of the plurality of charge storage sections,
wherein each charge storage section of the plurality of charge storage sections is provided between the first gate and the second gate included in the additional transistor.”
However, in a similar field of endeavor, Figs. 13(a) and 13(b) of Kawahito teach wherein an imaging element disposed in the light receiving section includes:
a photoelectric converting section (“light receiving gate electrode 11”, [0119], is equivalent to the “photoelectric conversion section” taught by Fujii) configured to perform photoelectric conversion;
a plurality of charge storage sections (“the first buried charge-transfer region 27b and the second buried charge-transfer region 27a”, [0124]) configured to store charge obtained by the photoelectric converting section (“As a result, the signal charges are transferred to and accumulated in the first buried charge-transfer region 27b of the second conductivity type (n-type) and the second buried charge-transfer region 27a”, [0125]);
a plurality of transfer sections (“The portion located just under the first transfer gate electrode 16b between the buried charge-generation region 22 and the first buried charge-transfer region 27b serves as the first transfer channel, and the portion located just under the second transfer gate electrode 16a between the buried charge-generation region 22 and the second buried charge-transfer region 27a serves as the second transfer channel”, [0148], this portion is denoted by “TSb” and “TSa” in Fig. 13(a)) configured to transfer the charge from the photoelectric converting section to each of the plurality of charge storage sections (“the first transfer gate electrode 16b and the second transfer gate electrode 16a electrostatically control the potentials in the first and second transfer channels through the insulating films 31 formed on the upper portions of the first and second transfer channels, respectively. Since the potentials in the first and second transfer channels are electrostatically controlled, the signal charges are transferred through the first and second transfer channels alternately in the parallel directions in the two stages (two rows), respectively. As a result, the signal charges are transferred to and accumulated in the first buried charge-transfer region 27b of the second conductivity type (n-type) and the second buried charge-transfer region 27a in the two stages (two rows) in the parallel directions, respectively”, [0148]), and
wherein each of the charge storage sections is provided between a first gate of a transistor included in a corresponding one of the transfer sections(“the first transfer gate electrode 16b and the second transfer gate electrode 16a”, [0119], and as seen in Fig. 13(b), 16b is in the corresponding TS) and a second gate provided at a position parallel to the first gate (“the first read-out gate electrode 14b and the second read-out gate electrode 14a”, [0124], as seen in Fig. 13(a), 27b and 27a are between 16b and 14b, and 16a and 14a, respectively) provided at a position parallel to the first gate (as seen in Fig. 13(a), 14b and 14a are parallel to 16b and 16a, respectively),
an additional capacitance section (together “first buried charge read-out region 26b and the second buried charge read-out region 26a”, [0124], form an additional capacitance section) configured to add a capacitance to each charge storage section of the plurality of charge storage sections (“Then, when the first read-out gate electrode 14b and the second read-out gate electrode 14a are opened, the charges which are accumulated in the first buried charge-transfer region 27b and the second buried charge-transfer region 27a are all transferred to the first buried charge read-out region 26b and the second buried charge read-out region 26a”, [0050]); and
an additional transistor (“first read-out gate electrode 14b and the second read-out gate electrode 14a”, [0124], 14a and 14b are gates of unnamed transistors hereinafter “AT”) provided between the additional capacitance section and the plurality of charge storage sections (as seen in Fig. 13(b), 14a is between 26a and 27a, and 14b is between 26b and 27b), configured to add the additional capacitance section to each charge storage section of the plurality of charge storage sections (as discussed above, 14a and 14b control the charge transfer between 26a/26b and 27a/27b, thus 14a and 14b add the charge storage capacity of 26a/26b to 27a/27b),
wherein each charge storage section of the plurality of charge storage sections is provided between the first gate and the second gate included in the additional transistor (as seen in Figs. 13(a) and 13(b), 27a/27b is provided between 16a/16b and 14a/14b).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein an imaging element disposed in the light receiving section includes:
a plurality of charge storage sections configured to store charge obtained by the photoelectric converting section;
a plurality of transfer sections configured to transfer the charge from the photoelectric converting section to each of the plurality of charge storage sections, and
wherein each of the charge storage sections is provided between a first gate of a transistor included in a corresponding one of the transfer sections and a second gate provided at a position parallel to the first gate,
an additional capacitance section configured to add a capacitance to each charge storage section of the plurality of charge storage sections; and
an additional transistor provided between the additional capacitance section and the plurality of charge storage sections, configured to add the additional capacitance section to each charge storage section of the plurality of charge storage sections,
wherein each charge storage section of the plurality of charge storage sections is provided between the first gate and the second gate included in the additional transistor” as taught by Figs 13(a) and 13(b) of Kawahito in the system of Fig. 1 of Kawahito in combination with Fujii for the purpose of storing and manipulating a signal charge.
Regarding claim 11, Figs. 13(a) and 13(b) of Kawahito in combination with Fujii disclose the distance measuring apparatus according to claim 10, Figs. 13(a) and 13(b) of Kawahito further disclose wherein the second gate includes a gate of a reset transistor configured to reset each charge storage section (as mentioned previously, “when the first read-out gate electrode 14b and the second read-out gate electrode 14a are opened, the charges which are accumulated in the first buried charge-transfer region 27b and the second buried charge-transfer region 27a are all transferred to the first buried charge read-out region 26b and the second buried charge read-out region 26a”, [0050]”, as all the accumulated charges in 27a/27b are transferred when 14a/14b are opened, 14a/14b function as the gate of a reset transistor).
Regarding claim 12, Figs. 1, 13(a), and 13(b) of Kawahito in combination with Fujii disclose the distance measuring apparatus according to claim 10, Figs. 13(a) and 13(b) of Kawahito further disclose wherein the additional capacitance section is provided between the second gate and a third gate provided in an adjacent pixel (“FIG. 13(a) is a schematic plan view describing a configuration of a semiconductor range-finding element serving as a part of pixels in a solid-state imaging device”, [0032], thus Fig. 13(a) represents a single pixel in a larger array and “first reset gate electrode 13b and second reset gate electrode 13a”, [0121], are a third gate in each pixel, therefore a first pixel’s 26a/26b are provided between the first pixel’s 14a/14b and a second pixel’s 13a/13b where the second pixel is located to the right of the first pixel as seen in Fig. 13a).
Regarding claim 13, Figs. 1, 13(a), and 13(b) of Kawahito in combination with Fujii disclose the distance measuring apparatus according to claim 10, Figs. 13(a) and 13(b) of Kawahito further disclose wherein two of the charge storage sections are provided in a pixel (“wherein each of the pixels encompasses … (c) island-shaped first and second buried charge-transfer regions of the second conductivity type buried in a part of the surface of the semiconductor layer, separated by a part of the semiconductor layer from the buried charge-generation region, configured to accumulate signal charges transferred from the buried charge-generation region”, [0010], the “first and second buried charge-transfer regions” are 27b and 27a respectively).
Regarding claim 14, Figs. 1, 13(a), and 13(b) of Kawahito in combination with Fujii disclose the distance measuring apparatus according to claim 10, Figs. 13(a) and 13(b) of Kawahito further disclose wherein the plurality of charge storage sections is disposed in a line symmetric with the plurality of transfer sections (as seen in Fig. 13(a), 27b and 27a, and TSb and TSa are disposed around a line of symmetry “LS”).
Regarding claim 17, Figs. 1, 13(a) and 13(b) of Kawahito in combination with Fujii disclose the distance measuring apparatus according to claim 10.
Figs. 1, 13(a), and 13(b) of Kawahito in combination with Fujii fail to disclose “further comprising a plurality of amplification sections provided around side portions the plurality of transfer sections, wherein the plurality of amplification sections includes a gate electrode connected to a corresponding charge storage section of the plurality of charge storage sections”.
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However, in a similar field of endeavor, Figs. 2 and 3 of Kawahito teach further comprising a plurality of amplification sections (“signal read-out transistor (amplification transistor) MA1”, [0052], and “signal read-out transistor (amplification transistor) MA2”, [0052]) provided around side portions the plurality of transfer sections (as seen in Fig. 2, MA1 and MA2 are provided around side portions of TSb and TSa, which are equivalent in Figs. 2 and 13(a)), wherein the plurality of amplification sections includes a gate electrode connected to a corresponding charge storage section of the plurality of charge storage sections (as seen in Fig. 2, MA1 and MA2 are electrically connected to 27b and 27a, which are also equivalent in Figs. 2 and 13(a)).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “further comprising a plurality of amplification sections provided around side portions the plurality of transfer sections, wherein the plurality of amplification sections includes a gate electrode connected to a corresponding charge storage section of the plurality of charge storage sections” as taught by Figs. 2 and 3 of Kawahito in the system of Fig. 1 of Kawahito in combination with Fujii and Figs. 13(a) and 13(b) of Kawahito for the purpose of increasing the signal strength of the range finding element.
Regarding claim 18, Figs. 1-3, 13(a) and 13(b) of Kawahito in combination with Fujii disclose the distance measuring apparatus according to claim 17, Figs. 2 and 3 of Kawahito further disclose further comprising a plurality of selections sections (“switching transistor MS1 … switching transistor MS2 for the pixel selection”, [0052]) provided around side portions of the photoelectric converting section in a plan view (as seen in Fig. 2, MS1 and MS2 are provided around side portions of 11 which is equivalent in Figs. 2 and 13(a), wherein the plurality of selections sections are connected to the plurality of amplification sections (as seen in Fig. 2, MS1 and MS2 are connected to MA1 and MA2 respectively).
Regarding claim 21, Figs. 13(a) and 13(b) of Kawahito in combination with Fujii disclose the imaging element according to claim 1.
Figs. 1, 13(a) and 13(b) of Kawahito in combination with Fujii fail to disclose “further comprising a plurality of amplification sections provided around side portions the plurality of transfer sections, wherein the plurality of amplification sections includes a gate electrode connected to a corresponding charge storage section of the plurality of charge storage sections”.
However, in a similar field of endeavor, Figs. 2 and 3 of Kawahito teach further comprising a plurality of amplification sections (“signal read-out transistor (amplification transistor) MA1”, [0052], and “signal read-out transistor (amplification transistor) MA2”, [0052]) provided around side portions the plurality of transfer sections (as seen in Fig. 2, MA1 and MA2 are provided around side portions of TSb and TSa, which are equivalent in Figs. 2 and 13(a)), wherein the plurality of amplification sections includes a gate electrode connected to a corresponding charge storage section of the plurality of charge storage sections (as seen in Fig. 2, MA1 and MA2 are electrically connected to 27b and 27a, which are also equivalent in Figs. 2 and 13(a)).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “further comprising a plurality of amplification sections provided around side portions the plurality of transfer sections, wherein the plurality of amplification sections includes a gate electrode connected to a corresponding charge storage section of the plurality of charge storage sections” as taught by Figs. 2 and 3 of Kawahito in the system of Fig. 1 of Kawahito in combination with Fujii and Figs. 13(a) and 13(b) of Kawahito for the purpose of increasing the signal strength of the range finding element.
Regarding claim 22, Figs. 2, 3, 13(a) and 13(b) of Kawahito in combination with Fujii disclose the image element according to claim 1, Figs. 2 and 3 of Kawahito further disclose further comprising a plurality of selections sections (“switching transistor MS1 … switching transistor MS2 for the pixel selection”, [0052]) provided around side portions of the photoelectric converting section in a plan view (as seen in Fig. 2, MS1 and MS2 are provided around side portions of 11 which is equivalent in Figs. 2 and 13(a), wherein the plurality of selections sections are connected to the plurality of amplification sections (as seen in Fig. 2, MS1 and MS2 are connected to MA1 and MA2 respectively).
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kawahito (US 2009/0114919 A1) in view of Fujii (US 2020/0169704 A1) in view of Nakata (US 2021/0159260 A1).
Regarding claim 6, Figs. 13(a) and 13(b) of Kawahito disclose an imaging element (“the semiconductor range-finding element serving as the TOF pixel circuit 81”, [0119]), comprising:
a plurality of charge storage sections (“the first buried charge-transfer region 27b and the second buried charge-transfer region 27a”, [0124]) configured to store charge obtained by the photoelectric converting section (“As a result, the signal charges are transferred to and accumulated in the first buried charge-transfer region 27b of the second conductivity type (n-type) and the second buried charge-transfer region 27a”, [0125]);
a plurality of transfer sections (“The portion located just under the first transfer gate electrode 16b between the buried charge-generation region 22 and the first buried charge-transfer region 27b serves as the first transfer channel, and the portion located just under the second transfer gate electrode 16a between the buried charge-generation region 22 and the second buried charge-transfer region 27a serves as the second transfer channel”, [0148], this portion is denoted by “TS” in Fig. 13(b)) configured to transfer the charge from the photoelectric converting section to each of the plurality of charge storage sections (“the first transfer gate electrode 16b and the second transfer gate electrode 16a electrostatically control the potentials in the first and second transfer channels through the insulating films 31 formed on the upper portions of the first and second transfer channels, respectively. Since the potentials in the first and second transfer channels are electrostatically controlled, the signal charges are transferred through the first and second transfer channels alternately in the parallel directions in the two stages (two rows), respectively. As a result, the signal charges are transferred to and accumulated in the first buried charge-transfer region 27b of the second conductivity type (n-type) and the second buried charge-transfer region 27a in the two stages (two rows) in the parallel directions, respectively”, [0148]); and
a gate of a transistor included in a corresponding one of the transfer sections (“the first transfer gate electrode 16b and the second transfer gate electrode 16a”, [0119]).
Kawahito fails to disclose “a photoelectric converting section configured to perform photoelectric conversion;
a trench provided parallel to a gate of a transistor included in a corresponding one of the plurality of transfer sections,
wherein each charge storage section of the plurality of charge storage sections is provided between the gate and the trench, and
wherein a distance between the trench to a first transistor of the plurality of transfer sections is equal to a distance between the trench and a second transistor of the plurality of transfer sections.”
However, in a similar field of endeavor, Fujii teaches a photoelectric converting section configured to perform photoelectric conversion (“a photoelectric conversion section that photoelectrically converts received light”, [0184], the photoelectric conversion section of Fujii is equivalent to “the buried charge-generation region 22” of Kawahito).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a photoelectric converting section configured to perform photoelectric conversion” as taught by Fujii in the system of Kawahito for the purpose of transforming an optical signal into a digital signal.
Kawahito in combination with Fujii fails to disclose “a trench provided parallel to a gate of a transistor included in a corresponding one of the plurality of transfer sections,
wherein each charge storage section of the plurality of charge storage sections is provided between the gate and the trench, and
wherein a distance between the trench to a first transistor of the plurality of transfer sections is equal to a distance between the trench and a second transistor of the plurality of transfer sections.”
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However, in a similar field of endeavor, Fig. 2 of Nakata teaches a trench (“light-shielding members 106 and 107 are disposed in the trenches formed in the pixel region within the semiconductor substrate (semiconductor layer) 53”, [0029]) provided parallel to a gate of a transistor included in a corresponding one of the plurality of transfer sections (as seen in Fig. 2, 106, and therefore the trench, extends in both the x and y direction, after substitution in Kawahito, 106 would be parallel to 16b and 16a which also extend in the x and y directions),
wherein each charge storage section of the plurality of charge storage sections is provided between the gate and the trench (“106 and 107 surround the photoelectric conversion unit 104 and the charge holding portion 105”, [0029], 104 is equivalent to 11 of Kawahito, and 105 is equivalent to 27b and 27a of Kawahito, as 106 surrounds 11, 27b and 27a of Kawahito after substitution, 27b and 27a would necessarily be between 16b and 16a respectively), and
wherein a distance between the trench to a first transistor of the plurality of transfer sections is equal to a distance between the trench and a second transistor of the plurality of transfer sections (As seen in Fig. 2 of Nakata, the trench containing 106 is symmetric across a horizontal line. Similarly, as seen in Fig. 13 of Kawahito, 16b and 16a are gates of unnamed transistors in TSb and TSa respectively, are also symmetric with one another across the horizontal line “LS”. Therefore, after substitution with the horizontal lines of symmetry overlapping, the distance between the trench of Nakata to the first transistor of the plurality of transfer sections represented by 16b of Kawahito is equal to the distance between the trench of Nakata to the second transistor of the plurality of transfer sections represented by 16a of Kawahito.)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a trench provided parallel to a gate of a transistor included in a corresponding one of the plurality of transfer sections,
wherein each charge storage section of the plurality of charge storage sections is provided between the gate and the trench, and
wherein a distance between the trench to a first transistor of the plurality of transfer sections is equal to a distance between the trench and a second transistor of the plurality of transfer sections” as taught by Nakata in the system of Figs. 13(a) and 13(b) of Kawahito in combination with Fujii for the purpose of incorporating isolation elements between pixels (“the semiconductor substrate 53 has the trenches for accommodating the light-shielding members 106 and 107”, [0029]).
Regarding claim 7, Figs. 13(a) and 13(b) of Kawahito in combination with Fujii and Fig. 2 of Nakata disclose the imaging element according to claim 6, Fig. 2 of Nakata further discloses wherein the trench is provided to surround a pixel (“106 and 107 surround the photoelectric conversion unit 104 and the charge holding portion 105”, [0029], therefore, after substitution into Kawahito, 106 would surround a pixel).
Claims 15, 16, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kawahito (US 2009/0114919 A1) in view of Fujii (US 2020/0169704 A1) in view of Raynor (US 10,116,891 B2).
Regarding claim 15, Figs. 1, 13(a), and 13(b) of Kawahito in combination with Fujii disclose the distance measuring apparatus according to claim 10.
Kawahito in combination with Fujii fails to disclose “wherein four of the plurality of charge storage sections are provided in a pixel”.
However, in a similar field of endeavor, Fig. 3 of Raynor teaches wherein four of the plurality of charge storage sections are provided in a pixel (“It is thus possible, and in some cases desirable, to modify the invention to have four sample/hold capacitors”, col. 6, lines 41-42, where the sample/hold capacitors of Raynor are equivalent to 27a/27b of Kawahito. Modifying Kawahito to include two pairs of 27a/27b could be realized by combining Fig. 2 and Fig. 13(a) of Kawahito such that a first pair of 27a/27b is to the right of 11 and a second pair of 27a/27b is to the left of 11).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein four of the plurality of charge storage sections are provided in a pixel” as taught by Raynor in the system of Kawahito so that “four capacitors can then be used to store two image values and two reset values so that CDS [correlated device sampling] can be performed on each of the acquired images” (col. 6, lines 42-45).
Regarding claim 16, Figs. 1, 13(a), and 13(b) of Kawahito in combination with Fujii disclose the distance measuring apparatus according to claim 10.
Kawahito in combination with Fujii fails to disclose “wherein the plurality of charge storage sections is disposed in a point symmetric relationship with the plurality of transfer sections”.
However, in a similar field of endeavor, Fig. 3 of Raynor teaches wherein the plurality of charge storage sections is disposed in a point symmetric relationship with the plurality of transfer sections (“It is thus possible, and in some cases desirable, to modify the invention to have four sample/hold capacitors”, col. 6, lines 41-42, where the sample/hold capacitors of Raynor are equivalent to 27a/27b of Kawahito. Modifying Kawahito to include two pairs of 27a/27b could be realized by combining Fig. 2 and Fig. 13(a) of Kawahito such that a first pair of 27a/27b and 16a/16b is to the right of 11 and a second pair of 27a/27b and 16a/16b is to the left of 11, thus the first and second pair of 27a/27b are disposed in a point symmetric relationship with the first and second pair of 16a/16b where the point of symmetry is the geometrically center of 11 as seen in a plan view).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the plurality of charge storage sections is disposed in a point symmetric relationship with the plurality of transfer sections” as taught by Raynor in the system of Kawahito so that “four capacitors can then be used to store two image values and two reset values so that CDS [correlated device sampling] can be performed on each of the acquired images” (col. 6, lines 42-45).
Regarding claim 19, Figs. 13(a) and 13(b) of Kawahito in combination with Fujii disclose imaging element according to claim 1.
Kawahito in combination with Fujii fails to disclose “wherein four of the plurality of charge storage sections are provided in a pixel”.
However, in a similar field of endeavor, Fig. 3 of Raynor teaches wherein four of the plurality of charge storage sections are provided in a pixel (“It is thus possible, and in some cases desirable, to modify the invention to have four sample/hold capacitors”, col. 6, lines 41-42, where the sample/hold capacitors of Raynor are equivalent to 27a/27b of Kawahito. Modifying Kawahito to include two pairs of 27a/27b could be realized by combining Fig. 2 and Fig. 13(a) of Kawahito such that a first pair of 27a/27b is to the right of 11 and a second pair of 27a/27b is to the left of 11).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein four of the plurality of charge storage sections are provided in a pixel” as taught by Raynor in the system of Kawahito so that “four capacitors can then be used to store two image values and two reset values so that CDS [correlated device sampling] can be performed on each of the acquired images” (col. 6, lines 42-45).
Regarding claim 20, Figs. 13(a) and 13(b) of Kawahito in combination with Fujii disclose imaging element apparatus according to claim 1.
Kawahito in combination with Fujii fails to disclose “wherein the plurality of charge storage sections is disposed in a point symmetric relationship with the plurality of transfer sections”.
However, in a similar field of endeavor, Fig. 3 of Raynor teaches wherein the plurality of charge storage sections is disposed in a point symmetric relationship with the plurality of transfer sections (“It is thus possible, and in some cases desirable, to modify the invention to have four sample/hold capacitors”, col. 6, lines 41-42, where the sample/hold capacitors of Raynor are equivalent to 27a/27b of Kawahito. Modifying Kawahito to include two pairs of 27a/27b could be realized by combining Fig. 2 and Fig. 13(a) of Kawahito such that a first pair of 27a/27b and 16a/16b is to the right of 11 and a second pair of 27a/27b and 16a/16b is to the left of 11, thus the first and second pair of 27a/27b are disposed in a point symmetric relationship with the first and second pair of 16a/16b where the point of symmetry is the geometrically center of 11 as seen in a plan view).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the plurality of charge storage sections is disposed in a point symmetric relationship with the plurality of transfer sections” as taught by Raynor in the system of Kawahito so that “four capacitors can then be used to store two image values and two reset values so that CDS [correlated device sampling] can be performed on each of the acquired images” (col. 6, lines 42-45).
Conclusion
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893