DETAILED ACTION
This correspondence is in response to the communications received 06/03/2026. Claims 1 and 10 have been amended. Claims 1, 2, and 5-22 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/04/2025 has been considered by the examiner and made of record in the application file.
Response to Arguments
Applicant’s arguments, see pages 8-10, filed 06/03/2026, with respect to the 103 rejections of claims 1 and 10 have been fully considered and are persuasive. The rejection of 12/15/2025 has been withdrawn.
Applicant's arguments filed 06/03/2026 with respect to the 103 rejection of claim 6 has been fully considered but they are not persuasive.
Applicant asserts on pages 8-10 of the Remarks filed 06/03/2026 that Kawahito (US 2009/0114919 A1), Fujii (US 2020/0169704 A1), and Nakata (US 2021/0159260 A1) whether considered individually or in combination do not disclose the features of claim 6. Specifically, that the references do not explicitly recite “wherein a distance between the trench to a first transistor of the plurality of transfer sections is equal to a distance between the trench and a second transistor of the plurality of transfer sections”.
However as discussed in the previous Office Action, Fig. 2 of Nakata shows the trench filled by “light-shielding members 106 and 107” as having a line of symmetry across a horizontal line bisecting the device. Fig. 13(a) of Kawahito also shows “TOF pixel circuit 81” as having a horizontal line of symmetry shown as “LS”. Substitution of the trench of Nakata into Kawahito would then include aligning the lines of symmetry as Nakata shows “photoelectric conversion unit 104”, “charge holding portion 105”, and “transfer gate 103” as being centered between the upper and lower portions of 106. Further, neither Nakata nor Kawahito suggest any asymmetry in the device structure that would cause the distance from the trench to any pair of symmetrically arranged elements to be unequal. Thus, the distance between the trench of Nakata to the first transistor of the plurality of transfer sections represented by 16b of Kawahito is equal to the distance between the trench of Nakata to the second transistor of the plurality of transfer sections represented by 16a of Kawahito.
Therefore, Kawahito in combination with Fujii and Nakata discloses the limitations of claim 6.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, an imaging element ("pixel 50c"), comprising:
a photoelectric converting section ("photodiode 61" or "PD 61") configured to perform photoelectric conversion;
a plurality of charge storage sections ("FD 63" where FD is "floating diffusion region") configured to store charge obtained by the photoelectric converting section;
a plurality of transfer sections ("transfer transistor 62") configured to transfer the charge from the photoelectric converting section to each of the plurality of charge storage sections,
wherein each of the charge storage sections is provided between a first gate of a transistor ("TG 62" where "The TG 62-1 is a gate portion of the transfer transistor 62-1, and the TG 62-2 is a gate portion of the transfer transistor 62-2" [0081]) included in a corresponding one of the transfer sections and a second gate ("a gate of the transistor for conversion efficiency switching 251 is represented as FDG 251", [0117]) provided at a position parallel to the first gate (as seen in Fig. 13, FDG 251 is provided at a position parallel to TG 62),
an additional capacitance section ("additional capacitance section 252") configured to add a capacitance to each charge storage section of the plurality of charge storage sections; and
a single additional transistor ("transistor for conversion efficiency switching 251") provided between the additional capacitance section and the plurality of charge storage sections, (see Fig. 13) configured to add the additional capacitance section to each charge storage section of the plurality of charge storage sections,
wherein each charge storage section of the plurality of charge storage sections is provided between the first gate and the second gate of the single additional transistor (as seen in Fig. 13, each of FD 63 is between TG62 and FDG 251), and
wherein the plurality of charge storage sections are commonly connected to the single additional transistor such that the single additional transistor is shared by the plurality of charge storage sections (see Fig. 13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kawahito (US 2009/0114919 A1) in view of Fujii (US 2020/0169704 A1) in view of Nakata (US 2021/0159260 A1).
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Regarding claim 6, Figs. 13(a) and 13(b) of Kawahito disclose an imaging element (“the semiconductor range-finding element serving as the TOF pixel circuit 81”, [0119]), comprising:
a plurality of charge storage sections (“the first buried charge-transfer region 27b and the second buried charge-transfer region 27a”, [0124]) configured to store charge obtained by the photoelectric converting section (“As a result, the signal charges are transferred to and accumulated in the first buried charge-transfer region 27b of the second conductivity type (n-type) and the second buried charge-transfer region 27a”, [0125]);
a plurality of transfer sections (“The portion located just under the first transfer gate electrode 16b between the buried charge-generation region 22 and the first buried charge-transfer region 27b serves as the first transfer channel, and the portion located just under the second transfer gate electrode 16a between the buried charge-generation region 22 and the second buried charge-transfer region 27a serves as the second transfer channel”, [0148], this portion is denoted by “TS” in Fig. 13(b)) configured to transfer the charge from the photoelectric converting section to each of the plurality of charge storage sections (“the first transfer gate electrode 16b and the second transfer gate electrode 16a electrostatically control the potentials in the first and second transfer channels through the insulating films 31 formed on the upper portions of the first and second transfer channels, respectively. Since the potentials in the first and second transfer channels are electrostatically controlled, the signal charges are transferred through the first and second transfer channels alternately in the parallel directions in the two stages (two rows), respectively. As a result, the signal charges are transferred to and accumulated in the first buried charge-transfer region 27b of the second conductivity type (n-type) and the second buried charge-transfer region 27a in the two stages (two rows) in the parallel directions, respectively”, [0148]); and
a gate of a transistor included in a corresponding one of the transfer sections (“the first transfer gate electrode 16b and the second transfer gate electrode 16a”, [0119]).
Kawahito fails to disclose “a photoelectric converting section configured to perform photoelectric conversion;
a trench provided parallel to a gate of a transistor included in a corresponding one of the plurality of transfer sections,
wherein each charge storage section of the plurality of charge storage sections is provided between the gate and the trench, and
wherein a distance between the trench to a first transistor of the plurality of transfer sections is equal to a distance between the trench and a second transistor of the plurality of transfer sections.”
However, in a similar field of endeavor, Fujii teaches a photoelectric converting section configured to perform photoelectric conversion (“a photoelectric conversion section that photoelectrically converts received light”, [0184], the photoelectric conversion section of Fujii is equivalent to “the buried charge-generation region 22” of Kawahito).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a photoelectric converting section configured to perform photoelectric conversion” as taught by Fujii in the system of Kawahito for the purpose of transforming an optical signal into a digital signal.
Kawahito in combination with Fujii fails to disclose “a trench provided parallel to a gate of a transistor included in a corresponding one of the plurality of transfer sections,
wherein each charge storage section of the plurality of charge storage sections is provided between the gate and the trench, and
wherein a distance between the trench to a first transistor of the plurality of transfer sections is equal to a distance between the trench and a second transistor of the plurality of transfer sections.”
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However, in a similar field of endeavor, Fig. 2 of Nakata teaches a trench (“light-shielding members 106 and 107 are disposed in the trenches formed in the pixel region within the semiconductor substrate (semiconductor layer) 53”, [0029]) provided parallel to a gate of a transistor included in a corresponding one of the plurality of transfer sections (as seen in Fig. 2, 106, and therefore the trench, extends in both the x and y direction, after substitution in Kawahito, 106 would be parallel to 16b and 16a which also extend in the x and y directions),
wherein each charge storage section of the plurality of charge storage sections is provided between the gate and the trench (“106 and 107 surround the photoelectric conversion unit 104 and the charge holding portion 105”, [0029], 104 is equivalent to 11 of Kawahito, and 105 is equivalent to 27b and 27a of Kawahito, as 106 surrounds 11, 27b and 27a of Kawahito after substitution, 27b and 27a would necessarily be between 16b and 16a respectively), and
wherein a distance between the trench to a first transistor of the plurality of transfer sections is equal to a distance between the trench and a second transistor of the plurality of transfer sections (As seen in Fig. 2 of Nakata, the trench containing 106 is symmetric across a horizontal line. Similarly, as seen in Fig. 13 of Kawahito, 16b and 16a are gates of unnamed transistors in TSb and TSa respectively, are also symmetric with one another across the horizontal line “LS”. Therefore, after substitution with the horizontal lines of symmetry overlapping, the distance between the trench of Nakata to the first transistor of the plurality of transfer sections represented by 16b of Kawahito is equal to the distance between the trench of Nakata to the second transistor of the plurality of transfer sections represented by 16a of Kawahito.)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a trench provided parallel to a gate of a transistor included in a corresponding one of the plurality of transfer sections,
wherein each charge storage section of the plurality of charge storage sections is provided between the gate and the trench, and
wherein a distance between the trench to a first transistor of the plurality of transfer sections is equal to a distance between the trench and a second transistor of the plurality of transfer sections” as taught by Nakata in the system of Figs. 13(a) and 13(b) of Kawahito in combination with Fujii for the purpose of incorporating isolation elements between pixels (“the semiconductor substrate 53 has the trenches for accommodating the light-shielding members 106 and 107”, [0029]).
Regarding claim 7, Figs. 13(a) and 13(b) of Kawahito in combination with Fujii and Fig. 2 of Nakata disclose the imaging element according to claim 6, Fig. 2 of Nakata further discloses wherein the trench is provided to surround a pixel (“106 and 107 surround the photoelectric conversion unit 104 and the charge holding portion 105”, [0029], therefore, after substitution into Kawahito, 106 would surround a pixel).
Allowable Subject Matter
Claims 1, 2, 5, and 8-22 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art of record does not teach or fairly suggest the imaging element as recited in the claims of the instant application.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Regarding claim 1, the prior art of Kawahito (US 2009/0114919 A1) in combination with Fujii (US 2020/0169704 A1) discloses a similar imaging element but fails to disclose the specific claims of the instant application regarding the structure of regarding the structure of the additional transistor and the plurality of charge storage sections e.g. “a single additional transistor … wherein the plurality of charge storage sections are commonly connected to the single additional transistor such that the single additional transistor is shared by the plurality of charge storage sections”.
Claims 2, 5, 8, 9, and 19-21 are allowable by virtue of their dependence on claim 1.
Regarding claim 10, the prior art of Kawahito (US 2009/0114919 A1) in combination with Fujii (US 2020/0169704 A1) discloses a similar imaging element but fails to disclose the specific claims of the instant application regarding the structure of regarding the structure of the additional transistor and the plurality of charge storage sections e.g. “a single additional transistor … wherein the plurality of charge storage sections are commonly connected to the single additional transistor such that the single additional transistor is shared by the plurality of charge storage sections”.
Claims 11-18 and 22 are allowable by virtue of their dependence on claim 10.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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