DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 04/29/2025 amendments of claims 1, 3-5, 7, 15-16 and 20 have been noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks pages 8-17, filed 04/29/2025, with respect to the rejection(s) of claim(s) 1, 3-20 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Ma, US 8497587 B2 (Ma).
New Grounds for Rejection
New grounds for rejection, prior art reference Ma, US 8497587 B2 (Ma) appears below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 10-11, 13-15 and 17-20 are rejected under 35 U.S.C. 102(a)1 as being anticipated by Ma, US 8497587 B2 (Ma)
Regarding claim 1; Ma teaches a fan-out type package, having one or more chips (12) having same or different functions, an adhesive material layer (16) (see Col.: 2, Row 50-55 of the specification of Ma: “The thermal interface material 16 is composed of grease or epoxy and typically contains a thermally conductive filler to improve thermal conductivity.”), a heat dissipation sheet (18) having thermal conductivity and electrical conductivity (see Col.: 3, Row: 3-5 of the specification of Ma: “The heat dissipater 18 may be composed of aluminum, Alloy 42, a copper alloy, or any other thermally conductive material.”), an encapsulation material layer (20), a packaging circuit (14), and a packaging circuit protection layer (22) which is configured for protecting the packaging circuit (14), wherein the heat dissipation sheet (18) has hollowed-out holes (31) that are hollowed out in a thickness direction of the fan- out type package, and the hollowed-out holes (31) are channels configured for allowing an encapsulation material constituting the encapsulation material layer to flow there through (see Col.: 3, Row: 48-52 of the specification of Ma: “The open regions 31 between the heat dissipaters 18 of the frame 29 allow encapsulant material 20 to flow underneath the solid regions of the dissipater 18 and up to the edges of the semiconductor die 12 during encapsulant dispensing.”); wherein a back surface of the chip (12) is mounted to a chip mounting region of the heat dissipation sheet (18) through the adhesive material layer (18); a front surface of the chip is covered by a temporary protection material (30) (see Col.: 3, Row: 63-66 of the specification of Ma: “In FIG. 3A, a foil 30 is laminated onto a carrier 32. The side of the foil 30 not laminated to the carrier 32 includes an adhesive that temporarily holds the semiconductor die 12 onto the foil 30 when the die 12 is placed there.”); the encapsulation material layer (20) is formed by making the encapsulation material flow into the hollowed-out holes (31) from a lower surface of the heat dissipation sheet and fill a gap between the temporary protection material (30) and the heat dissipation sheet (18) and/or cover a side of the heat dissipation sheet (18) opposite to a side thereof mounted with the chip (12), and then removing the temporary protection material (30) (see Figs (3A) – (3G) of Ma), thus the encapsulation material layer covers the chip (12), the adhesive material layer (16), and the heat dissipation sheet (18); and the packaging circuit (14) is formed by being grown on the front surface of the chip (12), the encapsulation material (20), and the heat dissipation sheet (18); wherein the front surface of the chip (12) is a functional surface configured to have a circuit and/or a device thereon (see col.:4, Row: 1-2 of the specification of Ma: “The semiconductor die 12 are placed so that the active face 25 of the die 12 faces the foil 30.”).
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Regarding claim 3; Ma teaches wherein in the thickness direction of the fan-out type package, a surface of the chip mounting region (region where chip (12) is mounted) is located in a same horizontal plane as other regions of the heat dissipation sheet (18).
Regarding claim 4; Ma teaches wherein in the thickness direction of the fan-out type package, a surface of the chip mounting region (region where chip (12) is mounted) is higher than surfaces of other regions of the heat dissipation sheet (18).
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Regarding claim 5; Ma teaches wherein in the thickness direction of the fan-out type package, a surface of the chip mounting region (the region in which the chip (12) is mounted) is lower than surfaces of other regions of the heat dissipation sheet (34) (see Figs (5A)-(5B) and (6A)-(6D) – Ma).
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Regarding claim 6; Ma teaches wherein the heat dissipation sheet (34)+(36) is provided with a projection structure (36), and in the thickness direction of the fan-out type package, a surface of the projection structure (36) is higher than the surface of the chip mounting region (region where chip (12) is mounted) (see Figs (5A)-(5B) and (6A)-(6D) – Ma ).
Regarding claim 7; Ma teaches wherein in the thickness direction of the fan-out type package, the front surface of the chip (12) is higher than a part of the heat dissipation sheet (18) other than the chip mounting region (region where the chip (12) is mounted), and the front surface of the chip (12) is exposed from the encapsulation material layer (20) in a manner of being located in a same plane as an upper surface of the encapsulation material layer (20).
.
Regarding claim 8; Ma teaches wherein in the thickness direction of the fan-out type package, the front surface of the chip (20) is located in a same plane as an upper surface of the projection structure (36) of the heat dissipation sheet (34)+(36), and the front surface of the chip (12) and the upper surface of the projection structure (36) of the heat dissipation sheet (34) are exposed from the encapsulation material layer (20) in a manner of being located in a same plane as the upper surface of the encapsulation material layer (20), and the packaging circuit (see annotated Fig (6F) of Ma reproduced below) is formed by being directly grown on the front surface of the chip (12), the upper surface of the encapsulation material layer (20), and the upper surface of the projection structure (36) of the heat dissipation sheet (34)+(36).
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Regarding claim 10; Ma teaches wherein the temporary protection material (30) consists of a peelable glue and a temporary carrying sheet (see Col.: 3, Row: 63-66 of the specification of Ma: “In FIG. 3A, a foil 30 is laminated onto a carrier 32. The side of the foil 30 not laminated to the carrier 32 includes an adhesive that temporarily holds the semiconductor die 12 onto the foil 30 when the die 12 is placed there.”).
Regarding claim 11; Ma teaches wherein two surfaces of the heat dissipation sheet (34) are each mounted with a chip (12).
Regarding claim 13; Ma teaches wherein the adhesive material (16) is an insulating material (see Col.: 2, Row 50-55 of the specification of Ma: “The thermal interface material 16 is composed of grease or epoxy and typically contains a thermally conductive filler to improve thermal conductivity.”).
Regarding claim 14; Ma teaches wherein the adhesive material (16) has thermal conductivity (see Col.: 2, Row 50-55 of the specification of Ma: “The thermal interface material 16 is composed of grease or epoxy and typically contains a thermally conductive filler to improve thermal conductivity.”).
Regarding claim 15; Ma teaches a preparation method of a fan-out type package, comprising: a step of preparing a chip (12), in which a plurality of chips having same or different functions are prepared; a step of preparing a heat dissipation sheet (18) having thermal conductivity and electrical conductivity (see Col.: 3, Row: 3-5 of the specification of Ma: “The heat dissipater 18 may be composed of aluminum, Alloy 42, a copper alloy, or any other thermally conductive material.”), in which a chip mounting region (the region in which chip (12) is mounted) configured for mounting the chip (12) and hollowed-out holes (31) that are hollowed out in a thickness direction of the heat dissipation sheet (18) are formed on the heat dissipation sheet (18); a step of mounting the chip (12), in which a back surface of the chip (12) is mounted through an adhesive material (16) to the chip mounting region (the region in which chip (12) is mounted) of the heat dissipation sheet (18); an encapsulating step, in which a front surface of the chip (12) is fixed with a temporary protection material (30), so that an encapsulation material (20) is made to flow into the hollowed-out holes (31) from a lower surface of the heat dissipation sheet (18) and fill a gap between the temporary protection material (30) and the heat dissipation sheet (18) and/or cover a side of the heat dissipation sheet (18) opposite to a side thereof mounted with the chip (see Col.: 3, Row: 48-52 of the specification of Ma: “The open regions 31 between the heat dissipaters 18 of the frame 29 allow encapsulant material 20 to flow underneath the solid regions of the dissipater 18 and up to the edges of the semiconductor die 12 during encapsulant dispensing.”), and the temporary protection material (30) is removed, to thus form the encapsulation material layer (20) covering the chip (12), the heat dissipation sheet (18), and the adhesive material (16); a step of preparing a packaging circuit (14), in which an electrically conducting material (14) is grown on the front surface of the chip (12), the heat dissipation sheet (18), and the encapsulation material (20) to form a packaging circuit layer (14); a step of preparing a packaging circuit protection layer (22) and a bonding pad, in which the packaging circuit protection layer (22) configured for protecting the packaging circuit (14) is produced on the packaging circuit (14), and the bonding pad (see annotated Fig (1) of Ma shared below) of the package is formed on the packaging circuit protection layer (22) and configured to be connected to a circuit or a device; and a step of performing cutting to obtain a device, in which a single packaged device is formed by cutting (see Col.: 4, Row: 36-40 of the specification of Ma).
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Regarding claim 17; Ma teaches wherein in the step of preparing a heat dissipation sheet (34)+(36), a projection structure (36) is formed on the heat dissipation sheet (34)+(36), and in the thickness direction of the fan-out type package, a surface of the projection structure (36) is higher than a surface of the chip mounting region (the region in which chip (12) is mounted),in the thickness direction of the fan-out type package, the front surface of the chip (12) mounted to the chip mounting region (the region in which chip (12) is mounted) through the mounting step is located in a same plane as the upper surface of the projection structure (36) of the heat dissipation sheet (34)+(36), in an encapsulation structural body (20) formed through the encapsulating step, the front surface of the chip (12) is exposed from the encapsulation material layer (20) in a manner of being located in a same plane as the upper surface of the encapsulation material layer (20), and the upper surface of the projection structure (36) of the heat dissipation sheet (34)+(36) is exposed from the encapsulation material layer (20) in a manner of being located in the same plane as the upper surface of the encapsulation material layer (20), and in the step of preparing a packaging circuit (packaging circuit – See Fig (6F) - Ma), the packaging circuit is formed by being directly grown on the front surface of the chip (12), the projection structure (36) of the heat dissipation sheet (34)+(36) exposed from the encapsulation material layer (20), and the encapsulation material layer (20).
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Regarding claim 18; Ma teaches wherein in the step of preparing a heat dissipation sheet (34)+(36), in the thickness direction, thickness of the chip mounting region (region where chip (12) is mounted) of the heat dissipation sheet (34)(36) is reduced, so that the chip mounting region is lower than upper surfaces of other parts of the heat dissipation sheet (34)+(36).
Regarding claim 19; Ma teaches wherein in the encapsulating step, the temporary protection material (30) is a temporary carrier, and the front surface of the chip (12) is fixed, by bonding, with the temporary carrier (30) (see Col.: 3, Row: 63-66 of the specification of Ma: “In FIG. 3A, a foil 30 is laminated onto a carrier 32. The side of the foil 30 not laminated to the carrier 32 includes an adhesive that temporarily holds the semiconductor die 12 onto the foil 30 when the die 12 is placed there.”).
Regarding claim 20; Ma teaches wherein in the thickness direction of the fan-out type package, the front surface of the chip (12) is higher than a part of the heat dissipation sheet (18) other than the chip mounting region (region where chip (12) is mounted), and the front surface of the chip (12) is exposed from the encapsulation material layer (20) in a manner of being located in a same plane as an upper surface of the encapsulation material layer (20).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ma, US 8497587 B2 (Ma) in view of Tai et al, US 11004786 B2 (Tai).
Regarding claim 9; Ma does not teach wherein through holes are formed on the encapsulation material layer in the thickness direction, with the through holes vertically running from the upper surface of the encapsulation material layer to an upper surface of a part of the heat dissipation sheet connected to the chip mounting region, wherein the through holes are channels configured for allowing an electrically conducting material forming the packaging circuit to flow therethrough. However, Tai teaches wherein through holes (26) (Fig (2F) – Tai) are formed on the encapsulation material layer (134) in the thickness direction, with the through holes (26) vertically running from the upper surface of the encapsulation material layer (134) to an upper surface of a part of the heat dissipation sheet (20) connected to the chip mounting region (Fig (2F), wherein the through holes (26) are channels configured for allowing an electrically conducting material forming the packaging circuit (PKG2) to flow therethrough. Ma and Tai are considered analogous art. Thus, it would have been obvious to one of ordinary skill in the art at the time of filing this application to modify Ma by using the through holes in the encapsulation layer and the heat dissipation layer to make the electrical connections for the circuit easier to implement leading to a more efficient device construction process.
Regarding claim 12; Ma does not teach wherein the adhesive material (16) is an electrically conducting material. However, Tai teaches wherein the adhesive material (27) is an electrically conducting material (see Col.: 4, Row: 61-64 in the specifications of Tai: “In some embodiments, the die 32 is attached to the thermal dissipation structure 20 through an adhesive layer 27 such as a die attach film (DAF), silver paste, or the like.”). Ma and Tai are considered analogous art. Thus, it would have been obvious to one of ordinary skill in the art at the time of filing this application to modify Ma by making the adhesive material out of an electrically conductive material to improve the conductivity of the layer to improve the heat dissipation from the device leading to a more reliable device.
Regarding claim 16; Ma teaches wherein in the thickness direction of the fan-out type package, a front surface of the chip (12) mounted to the chip mounting region (region where chip (12) is mounted) through the mounting step is higher than an upper surface of a part of the heat dissipation sheet (18) other than the chip mounting region, in an encapsulation structural body (20) formed through the encapsulating step, the front surface of the chip (12) is exposed from the encapsulation material layer (20) in a manner of being located in a same plane as the upper surface of the encapsulation material layer (20), and the upper surface of the part of the heat dissipation sheet (18) other than the chip mounting region is covered by the encapsulation material layer (20), and in the step of preparing a packaging circuit (14).
Ma does not teach through holes are formed on the encapsulation material layer in the thickness direction, with the through holes vertically running from the upper surface of the encapsulation material layer to the upper surface of the part of the heat dissipation sheet connected to the chip mounting region, and an electrically conducting material forming the packaging circuit flows in the through holes to reach the upper surface of the part of the heat dissipation sheet connected to the chip mounting region. However, Tai teaches wherein through holes (26) (Fig (2F) – Tai) are formed on the encapsulation material layer (134) in the thickness direction, with the through holes (26) vertically running from the upper surface of the encapsulation material layer (134) to the upper surface of the part of the heat dissipation sheet (20) connected to the chip mounting region (Fig (2F), and an electrically conducting material forming the packaging circuit (PKG2) flows in the through holes (26) to reach the upper surface of the part of the heat dissipation sheet (20) connected to the chip mounting region. Ma and Tai are considered analogous art. Thus, it would have been obvious to one of ordinary skill in the art at the time of filing this application to modify Ma by using the through holes in the encapsulation layer and the heat dissipation layer to make the electrical connections for the circuit easier to implement leading to a more efficient device construction process
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
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/MOATAZ KHALIFA/Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815