DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species IV-Figure 6 in the reply filed on January 7, 2025 is acknowledged.
Claims 7 and 12-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim.
Specification
The amendment filed on August 26, 2025 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: “supplies high-frequency powers in different values”.
Applicant is required to cancel the new matter in the reply to this Office Action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-2, 5, and 7-11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In lines 9-10, claim 1 recites the limitation, “a single high frequency power source that supplies high-frequency powers in different values to the sample stage and the thin film electrode respectively”. There is no support for this limitation. Paragraph [0030] indicates during the processing of the semiconductor wafer109, high-frequency power at a predetermined frequency is supplied from the high frequency power source124 to the electrode substrate108 (i.e., the sample stage ST). Additionally, paragraph [0033] indicates that the electrode substrate108 of the sample stage ST on which the semiconductor wafer109 is placed and the thin film electrode139b of the dielectric ring139 are connected to the high frequency power source124 that is a single power supply, and the high-frequency power is supplied from the high frequency power source124 to the electrode substrate108 and the thin film electrode139b. Hence, the specification supports a single high frequency power source that supplies a high-frequency power to the sample stage and the thin film electrode, respectively.
For purposes of examination, a single high frequency power source supplies a high-frequency power to the sample stage and the thin film electrode
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 5, 7-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ichino et al. (U.S. 2020/0083026) in view of Aramaki et al. (U.S. 2016/0351404) and Seo et al. (U.S. 2019/0006156)
Referring to Figures 1-5 and paragraphs [0033]-[0044], Ichino et al. disclose a plasma processing apparatus, comprising: (a) a sample stage 108, 140, 151, 152 including a placement surface on which a semiconductor wafer is placed and having a first circular shape in a plan view (par.[0033]); (b) a dielectric ring 139 surrounding the sample stage in a peripheral region of the sample stage and equipped with a ring-shaped thin film electrode 170 including an inner peripheral end and an outer peripheral end in a plan view (pars.[0034]-[0035], [0044]); and (c) a susceptor ring 138 made of a dielectric placed on the dielectric ring and covering the thin film electrode (pars.[0034]-[0035], [0044]), wherein the semiconductor wafer includes a main surface and a rear surface having a second circular shape in a plan view and an end portion being a circumference portion of the main surface, wherein a first radius of the first circular shape is smaller than a second radius of the second circular shape (Fig. 3).
Ichino et al. teach that a separate power source can be applied to the sample stage and the thin film electrode (Fig. 3). However, Ichino et al. is silent on the plasma processing apparatus further comprising: (d) a single high frequency power source that supplies high-frequency power to the sample stage and the thin film electrode.
Referring to Figures 1-2 and par.[0051]-[0054], Aramaki et al. teach that it is conventionally known in the art for a single high frequency power source 124 that supplies high-frequency power to the sample stage 111 and the thin film electrode 132 as an alternate and equivalent means to supply power to both sample stage and the thin film electrode which would reduce footprint and manufacturing costs. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the apparatus of Ichino et al. with a single high frequency power source that supplies high-frequency power to the sample stage and the thin film electrode as taught by Aramaki et al. since it is an alternate and equivalent means to supply power to both sample stage and the thin film electrode which would reduce footprint and manufacturing costs. Additionally, an express suggestion to substitute one equivalent component or process for another is not necessary to render such substitution obvious (In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982)).
Ichino et al. is silent on wherein the thin film electrode includes, between the inner peripheral end and the outer peripheral end, a first portion located lower than the rear surface of the semiconductor wafer, a second portion located higher than the main surface of the semiconductor wafer, and a third portion connecting the first portion and the second portion, and wherein the first portion of the thin film electrode has an overlap region that overlaps the semiconductor wafer in a plan view.
Referring to Figure 2 and paragraphs [0031]-[0042], Seo et al. teach a plasma processing apparatus wherein the thin film electrode includes, between the inner peripheral end and the outer peripheral end, a first portion 124a located lower than the rear surface of the semiconductor wafer, a second portion 124c located higher than the main surface of the semiconductor wafer, and a third portion 124b connecting the first portion and the second portion, and wherein the first portion of the thin film electrode has an overlap region that overlaps the semiconductor wafer in a plan view is used as a configuration that will ensure etching reliability of a wafer edge and extend the life of the focus ring (par.[0051]). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the apparatus of Ichino et al. with a wherein the thin film electrode includes, between the inner peripheral end and the outer peripheral end, a first portion located lower than the rear surface of the semiconductor wafer, a second portion located higher than the main surface of the semiconductor wafer, and a third portion connecting the first portion and the second portion, and wherein the first portion of the thin film electrode has an overlap region that overlaps the semiconductor wafer in a plan view as taught by Seo et al. since it is a configuration that will ensure etching reliability of a wafer edge and extend the life of the focus ring.
The resulting apparatus of Ichino et al. in view of Aramaki et al. and Seo et al. would yield wherein the thin film electrode includes, between the inner peripheral end and the outer peripheral end, a first portion located lower than the rear surface of the semiconductor wafer, a second portion located higher than the main surface of the semiconductor wafer, and a third portion connecting the first portion and the second portion, and wherein the first portion of the thin film electrode has an overlap region that overlaps the semiconductor wafer in a plan view.
Additionally, the plasma processing apparatus of Ichino et al. in view of Aramaki et al. and Seo et al. further includes wherein the inner peripheral end of the thin film electrode has a third circular shape with a third radius in a plan view, the third radius being larger than the first radius and smaller than the second radius (Seo et al.-Fig. 2. Note. The semiconductor wafer is considered intended use and any size semiconductor wafer can be used in the plasma processing apparatus. Note. The inclusion of material or article worked upon by a structure being claimed does not impart patentability to the claims (In re Young, 75 F.2d 966, 25 USPQ 69 (CCPA 1935) (as restated in In re Otto, 312 F.2d 937, 136 USPQ 458, 459 (CCPA 1963)))).
With respect to claim 2, the plasma processing apparatus of Ichino et al. in view of Aramaki et al. and Seo et al. further includes wherein the overlap region encompasses the whole area of the circumference portion of the semiconductor wafer (Seo et al.-Fig. 2).
With respect to claim 5, the plasma processing apparatus of Ichino et al. in view of Aramaki et al. and Seo et al. further includes wherein the sample stage includes a conductive electrode substrate (Ichino et al. & Aramaki et al.-111) and a dielectric film (Ichino et al.-140) arranged on the electrode substrate (Ichino et al.-108, Aramaki et al.-131) and wherein a top surface of the dielectric film constitutes the placement surface (Ichino et al.-Fig. 3, Aramaki et al.-Fig. 2).
With respect to claim 7, the plasma processing apparatus of Ichino et al. in view of Aramaki et al. and Seo et al. further includes wherein the dielectric film includes a conductive film 111 therein, and wherein high-frequency power 124 is supplied from the high frequency power source to the conductive film (Aramaki et al.-Fig. 2, par.[0053]).
With respect to claim 8, the plasma processing apparatus of Ichino et al. in view of Aramaki et al. and Seo et al. further includes wherein a first distance between the rear surface of the semiconductor wafer and the first portion of the thin film electrode in a vertical direction is smaller than a second distance between the end portion of the semiconductor wafer and the third portion of the thin film electrode in a horizontal direction (Seo et al.-Fig. 2, Additionally, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed thin film electrode and a thin film electrode having the claimed relative dimensions would not perform differently than the prior art thin film electrode, the claimed thin film electrode was not patentably distinct from the prior art thin film electrode).
With respect to claim 9, the plasma processing apparatus of Ichino et al. in view of Aramaki et al. and Seo et al. further includes wherein the susceptor ring is (Ichino et al.-138, Seo et al.-122) interposed between the third portion of the thin film electrode (Ichino et al.-170, Seo et al.-124b) and the end portion of the semiconductor wafer (Ichino et al.-9, Seo et al.-10) (Ichino et al.-Fig. 3, Seo et al.-Fig. 2).
With respect to claim 10, the plasma processing apparatus of Ichino et al. in view of Aramaki et al. and Seo et al. further includes wherein the first portion and the second portion of the thin film electrode include horizontal planes parallel to the main surface of the semiconductor wafer, and wherein the third portion of the thin film electrode includes a vertical plane perpendicular to the main surface. Note. Seo et al. shows the first portion and the second portion of the thin film electrode include horizontal planes parallel to the main surface of the semiconductor wafer as seen in Figure 2, but is silent on the wherein the third portion of the thin film electrode includes a vertical plane perpendicular to the main surface. However, Seo et al. does show the thin film electrode 124 can have alternative shapes that would ensure etch reliability of a wafer edge and extend the life of the focus ring as seen in Fig. 3. Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify the third portion of Ichino et al. in view of Aramaki et al. and Seo et al. such that the third portion of the thin film electrode includes a vertical plane perpendicular to the main surface in order to ensure etch reliability of a wafer edge and extend the life of the focus ring. Additionally, the shape of the claimed thin film electrode was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular shape of the claimed thin film electrode was significant.
With respect to claim 11, the plasma processing apparatus of Ichino et al. in view of Aramaki et al. and Seo et al. further includes wherein the first portion 124a and the second portion 124c of the thin film electrode include horizontal planes parallel to the main surface of the semiconductor wafer, and wherein the third portion 124b of the thin film electrode includes an inclination that gets closer to the sample stage along the vertical direction (Seo et al.-Fig. 2).
Response to Arguments
Applicant's arguments filed August 26, 2025 have been fully considered but they are not persuasive.
Applicant has argued that Ichino and Seo (as well as secondary reference Aramaki) does not teach or suggest that "a first radius of the first circular shape is smaller than a second radius of the second circular shape" and also does not teach or suggest that "the first portion of the thin film electrode has an overlap region that overlaps the semiconductor wafer in a plan view," as recited in Applicant's Claim 1, and also does not teach or suggest that "the inner peripheral end of the thin film electrode has a third circular shape with a third radius in a plan view, the third radius being larger than the first radius and smaller than the second radius," as now additionally recited in Applicant's amended Claim 1.
It should be noted that applicant has presented several arguments; however, has failed to give specifics of why Ichino, Aramaki, and specifically Seo fail to teach "a first radius of the first circular shape is smaller than a second radius of the second circular shape" and "the first portion of the thin film electrode has an overlap region that overlaps the semiconductor wafer in a plan view." Also, applicant has failed to give specifics of why Ichino, Aramaki, and specifically Seo not teach or suggest that "the inner peripheral end of the thin film electrode has a third circular shape with a third radius in a plan view, the third radius being larger than the first radius and smaller than the second radius". Therefore, arguments presented by applicant cannot take the place of factually supported objective evidence (MPEP 716.01(c)II).
Additionally, as stated above, the semiconductor wafer of Seo is considered intended use and any size semiconductor wafer can be used in the plasma processing apparatus (Seo-Fig. 2). Hence, the inclusion of material or article worked upon by a structure being claimed does not impart patentability to the claims (In re Young, 75 F.2d 966, 25 USPQ 69 (CCPA 1935) (as restated in In re Otto, 312 F.2d 937, 136 USPQ 458, 459 (CCPA 1963)))). Therefore, the apparatus of Seo is capable of supporting a larger diameter semiconductor wafer and when a larger diameter semiconductor wafer is used, then the apparatus of Seo would yield a first radius of the first circular shape is smaller than a second radius of the second circular shape" and "the first portion of the thin film electrode has an overlap region that overlaps the semiconductor wafer in a plan view."
Lastly, for evidentiary and additional support, Figure 2c of Srinaman et al. show that it is conventionally known chamber arrangement wherein the first portion of the thin film electrode 106 has an overlap region that overlaps the semiconductor wafer 105 in a the plan view, and the inner peripheral end of the thin film electrode 106 has a third circular shape with a third radius in the plan view, the third radius 106 being larger than the first radius 103 and smaller than the second radius 105. Thus, it is an obvious design choice for the apparatus of Seo to be configured such that a first radius of the first circular shape is smaller than a second radius of the second circular shape" and "the first portion of the thin film electrode has an overlap region that overlaps the semiconductor wafer in a plan view."
Therefore, for the reasons above, the apparatus of Ichino et al. in view of Seo and Aramaki et al. satisfies the claimed requirements.
Applicant determined that Ichino, the Japanese equivalent of which is discussed in Applicant's specification as "Patent Literature 1," may have certain limitations with respect to controlling the electric field around the wafer end portion with a thin film electrode. See, e.g., pages 3-4 of Applicant's specification (paragraphs [0008] and [0010] of Applicant's published application). Accordingly, Applicant respectfully submits that one skilled in the art would have had no reason attempt to provide such a combination of Ichino and Seo in the manner asserted in the Office Action.
As stated above, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In the instant case, Ichino in view of Seo teach all of the claimed structural limitations except for a single high frequency power source that supplies high-frequency power to the sample stage and the thin film electrode respectively. Aramaki et al. teach two chamber configurations with two different power arrangements. In Figure 1, Aramaki et al. teach that the sample stage 111 and the thin film electrode 132 have separate dedicated power sources 124, 127. Alternatively, in Figure 2, Aramaki et al teach that a it is conventionally known in the art to use a single high frequency power source 124 that supplies high-frequency power to the sample stage 111 and the thin film electrode 132 as an alternate and equivalent means to supply power to both sample stage and the thin film electrode which would reduce footprint and manufacturing costs (Figures 1-2 and par.[0051]-[0054]). Hence, Aramaki et al. teach the motivation to use a single power source for both the sample stage and the thin film electrode. Therefore, the apparatus of Ichino et al. in view of Seo and Aramaki et al. satisfies the claimed requirements.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zhao et al.’155, Ikegami et al.’605, and Maeda et al.’957 teach single high frequency power source that supplies high-frequency power to the sample stage and the thin film electrode respectively. Sriraman et al.’411 teach the inner peripheral end of the thin film electrode has a third circular shape with a third radius in the plan view, the third radius being larger than the first radius and smaller than the second radius.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Michelle CROWELL/Examiner, Art Unit 1716
/SYLVIA MACARTHUR/Primary Examiner, Art Unit 1716