DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the previously rejected claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The 35 USC §112(b) rejections of claims 1, 9, and 13 (and applicable dependent claims) have been overcome by the present amendments. The updated rejections follow below.
Claim Objections
Claim 35 is objected to because of the following informalities: line 1 recites “tthe”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 13, 20, and 34-35 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 5, it recites “the stretching (or pulling)” of the first semiconductor layer in lines 5-6. Along with the functional language of this claim, this limitation lacks antecedence and leaves the claim unclear as to what structural feature(s) are required by these limitations.
Regarding Claim 13, it recites “the first semiconductor layer comprising an at least partially relaxed semiconductor layer” in line 5. It is unclear if this limitation is meant to refer to “the partially relaxed InGaN layer” recited in claim 1 or if this requires another partially relaxed semiconductor layer.
Regarding Claim 20, it recites “a bond between the device structure and the top surface flips a polarity of the additional III-nitride layer so that the additional III-nitride layer has an opposite polarity”. This is unclear as to what type of polarity the additional III-nitride is supposed to be “opposite” to what polarity of which layer. The claim does not positively recite structural limitations and relies upon an active step of “bonding to flip a polarity”, leaving the claim unclear as to precisely what structure is required by these limitations. Applicant pointed to a definition of “polarity” in the specification at page 32 which describes “growing” material on various planes, but does not provide definition for what is required by the actively recited steps of the claim, leaving claim 20 indefinite and unclear. This is a device claim, and the language of a claim must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. For the purpose of applying prior art, this limitation is satisfied by meeting the structural limitation of “the device structure comprising an additional III-Nitride layer”.
Regarding Claim 34, it recites “the second semiconductor layer having been deposited after the porosification”. There is a lack of antecedence for the limitation “the porosification”, which is a method step in this device claim. This leaves the claim unclear as to what “the porosification” refers to.
Regarding Claim 35, it recites “the second semiconductor layer having been deposited after the porosification”. There is a lack of antecedence for the limitation “the porosification”, which is a method step in this device claim. This leaves the claim unclear as to what “the porosification” refers to.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 11-14, 17, 19-21, 24-25, and 34-35 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jonathan Wierer Jr. et al. (US 2009/0140274 A1; hereinafter Wierer).
Regarding Claim 1, Wierer discloses a device (Fig. 4), comprising:
a substrate, comprising:
III-Nitride layers including:
at least one first semiconductor layer (26; ¶0039) comprising a first at least partially relaxed InGaN layer (¶0039 with 5% In and up to 100nm thick) on a porous semiconductor GaN layer (16; wherein 16 is a porous layer formed by EC etching the GaN layer 12; ¶0023-¶0024, ¶0026; ¶0039); and
a second semiconductor layer (32/34) on the first semiconductor layer (26), wherein:
the second semiconductor layer (32/34) comprises a second at least partially relaxed InGaN layer (as described in ¶0035-¶0039) having a higher indium composition (32/34 comprises 15% In) and a larger thickness (32/34 is at least 300nm thick; ¶0037) than the first at least partially relaxed InGaN layer (26, as above).
Regarding Claim 5, Wierer discloses the device of claim 1, further comprising an additional III-Nitride layer (36; ¶0029) on a top surface of the second semiconductor layer (32/34) so as to form a heterostructure, wherein the porous semiconductor layer (16) is patterned with a shape and/or size to locally tailor a lattice constant of the second semiconductor layer (32/34) in the heterostructure that is larger (or smaller) than a lattice constant of the first semiconductor layer (26) so that the stretching (or pulling) of the first semiconductor layer to conform the first semiconductor layer to the second semiconductor layer comprises straining the first semiconductor layer (26) so that the first semiconductor layer has a lattice constant between a relaxed value for the lattice constant of the first semiconductor layer (26) and a relaxed value for the lattice constant of the second semiconductor layer (32/34) (these limitations are implicitly satisfied by meeting the structural limitations of claim 1 and the additional III-nitride layer in addition to forming the III-Nitride layers in the same order as in the instant application which is after the porosification of the GaN layer 12 to become porous layer 16; ¶0028).
Regarding Claim 11, Wierer discloses the device of claim 1, wherein the porous semiconductor layer (16) is comprised of nano-feature arrays (array of nano-sized pores; ¶0026).
Regarding Claim 12, Wierer discloses the device of claim 1, wherein the porous semiconductor layer (16) comprises etched pores (this is a product-by-process limitation and therefore adds no structural limitation to the claim thereby being implicitly satisfied. Regardless, Wierer also teaches this formation method in ¶0025).
Regarding Claim 13, Wierer discloses the device of claim 1, wherein the substrate further comprises:
a growth substrate (10; ¶0023);
the porous semiconductor layer (16) on or above the growth substrate (10) (as shown in Fig. 4); and
the first semiconductor layer (26) comprising an at least partially relaxed semiconductor layer (as in claim 1) having a lattice constant that is different than a lattice constant of the growth substrate (10) such that the at least partially relaxed semiconductor layer (26) would be coherently strained if grown directly on the growth substrate (as described in ¶0020-¶0029 and as implicitly satisfied by the different lattice constants of InGaN 26 compared to the material of growth substrate 10 in ¶0023), or
such that the at least partially relaxed semiconductor layer would plastically relax under formation of crystal defects if grown directly on the growth substrate.
Regarding Claim 14, Wierer discloses the device of claim 1, further including an intermediate semiconductor layer (14; ¶0024) between a growth substrate (10) and the porous semiconductor layer (12) (as shown in Fig. 4).
Regarding Claim 17, Wierer discloses the device of claim 1, wherein the porous semiconductor layer (16) comprises n-type gallium nitride (¶0023) and one or both of the at least partially relaxed semiconductor layers (26 and/or 32/34) comprises a stack of layers comprising nitrogen and at least one of Indium, gallium, or aluminum (wherein 32/34 is a stack of layers comprising nitrogen and Indium; ¶0039).
Regarding Claim 19, Wierer discloses the device of claim 1, wherein the substrate comprises a compliant substrate for a device structure (Fig. 8; p-type layers 36/42; ¶0029/¶0051) formed on a top surface of the second semiconductor layer (top of 32/34 in Fig. 4) such that a lattice constant of the second semiconductor layer (32/34) conforms to a lattice constant of the device structure (36/42) bonded or grown on the second semiconductor layer (32/34) (this is a product-by-process limitation implicitly satisfied by the structure and formation of the layers of Wierer) and wherein the device structure comprises all p-type layers (wherein 36/42 are p-type as described in ¶0029/¶0051) for the device structure.
Regarding Claim 20, Wierer discloses the device of claim 19, further comprising the device structure (36/42) on the top surface comprising an additional III-Nitride layer (wherein 36 is the additional III-Nitride layer of the device structure; ¶0029) bonded to the second semiconductor layer (32/34) (wherein “bonded” is a product-by-process limitation, and the two layers are contacting and therefore implicitly satisfy this limitation) and a bond between the device structure and the top surface flips a polarity of the additional III-nitride layer so that the additional III-nitride layer has an opposite polarity (this is implicitly satisfied by having a polarity).
Regarding Claim 21, Wierer discloses a device, comprising,
a substrate, comprising:
III-Nitride layers including:
a first at least partially relaxed semiconductor layer comprising comprising GaN, InGaN, or AIGaN (26; ¶0039) on a porous semiconductor layer comprising GaN (16; wherein 16 is a porous layer formed by EC etching the GaN layer 12; ¶0023-¶0024, ¶0026; ¶0039),
wherein the porous semiconductor layer (16) does not comprise a distributed bragg reflector (DBR) (16 is not a DBR or part of a DBR), and
a second at least partially relaxed semiconductor layer (32/34 comprising InGaN; as described in ¶0035-¶0039) on the first at least partially relaxed semiconductor layer (26), the second semiconductor layer comprising at least one of InGaN or AIGaN (¶0035-¶0039).
Regarding Claim 24, Wierer discloses the device of claim 1, wherein at least one of the first semiconductor layer or second semiconductor layer (32/34) are patterned (multiple portions of 34 are removed or “patterned” which is an array (commensurate in scope with instant specification ¶0281), to form contacts 44; Fig. 8 and ¶0051-¶0053) with an array of openings on which a selective area regrowth of can be performed (this is an intended use limitation implicitly satisfied by meeting the structural limitations of the claim).
Regarding Claim 25, Wierer discloses the device of claim 1, wherein the porous semiconductor layer (16) is on a sapphire substrate (10; ¶0024).
Regarding Claim 34, Wierer discloses the device of claim 1, wherein the at least one first semiconductor layer (26) has at least one of a first strain or first composition (¶0027), and the second semiconductor layer (32/34) is at least partially relaxed (¶0027) and has at least one of a second composition or second strain, and the first strain, the second strain, the first composition, and/or second composition are characteristic of the second semiconductor layer (32/34) having been deposited after the porosification (32/34 is formed after making the porous layer 16, as shown in Fig. 2, Fig. 3, and Fig. 4).
Regarding Claim 35, Wierer discloses the device of claim 21, wherein tthe at least one first semiconductor layer (26) has at least one of a first strain or first composition (¶0027), and the second semiconductor layer (32/34) is at least partially relaxed (¶0027) and has at least one of a second composition or second strain, and the first strain, the second strain, the first composition, and/or second composition are characteristic of the second semiconductor layer (32/34) having been deposited after the porosification (32/34 is formed after making the porous layer 16, as shown in Fig. 2, Fig. 3, and Fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Jonathan Wierer Jr. et al. (US 2009/0140274 A1; hereinafter Wierer) in view of Rachel Oliver et al. (US 2021/0057601 A1, hereinafter Oliver).
Regarding Claim 9, Wierer discloses the device of claim 1, wherein the second semiconductor layer (32/34) has a top surface for deposition of a device structure (Fig. 8; p-type layers 36/42; ¶0029/¶0051).
However, Wierer is silent regarding wherein the top surface of the second semiconductor layer (32/34) has a surface roughness of no more than 0.5 nanometers as measured over a 2 micron by 2 micron area.
In the same field of endeavor, Oliver teaches a III-Nitride surface layer (¶0088) suitable for further epitaxial growth (such as the III-Nitride 36 of Wierer), wherein the surface layer is provided with a surface roughness of less than 0.5nm over a 5 micron by 5 micron area (Oliver; ¶0181).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide the top surface of Wierer’s second semiconductor layer with the low surface roughness (as in Oliver) to provide an epi-ready surface for further epitaxial growth (such as Wierer’s 36) without intermediate processing steps (Oliver; ¶0181).
Regarding Claim 10, modified Wierer teaches the device of claim 9, wherein the porous semiconductor layer (16) comprises pores having a diameter in a range of 0.001 (1nm)-1000 micrometers (Wierer; ¶0026; 10-500nm).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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