DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Group I, semiconductor device, was elected.
Amendment filed November 24, 2025 is acknowledged. Claim 4 has been cancelled. Claims 1, 3, 6 and 11 have been amended. Non-elected invention, claim 11 has been withdrawn from consideration. Claims 1-11 are pending.
Action on merits of Group I, claims 1-3, 5-10 follows.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-3, 5-6 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over KIYOSAWA et al. (US. Pub. No. 2015/0137221) in view of KAWADA et al. (US. Pub. No. 2008/0220620) and TEGA et al. (JP 2019091754) all of record.
With respect to claim 1, KIYOSAWA ‘221 teaches a semiconductor device substantially as claimed including:
a semiconductor substrate (1) of a first conductivity type made of silicon carbide;
a first semiconductor layer (2) of the first conductivity type formed on the semiconductor substrate and made of silicon carbide;
a first impurity region (3) of a second conductivity type formed in the first semiconductor layer (2), the second conductivity type being opposite to the first conductivity type;
a second impurity region (4, left) of the first conductivity type and a third impurity region (4, right) of the first conductivity type each formed in the first impurity region (3) and having an impurity concentration higher than that of the first semiconductor layer (2);
a trench (5) formed so as to penetrate the second impurity region (4, left) and the third impurity region (4, right); and
a gate electrode (9) formed in the trench (5) with a gate insulating film (8) interposed between the gate electrode (9) and the trench (5), wherein
the trench (5) has a bottom surface located in the first semiconductor layer (2), a first side surface (5L) in contact with the second impurity region (4, left), and a second side surface (5R) in contact with the third impurity region (4, right) and facing the first side surface (5L),
in an upper surface layer of the first semiconductor layer (2) outside the trench (5), at the bottom surface of the trench, at the first side surface (5L) of the trench, and at the second side surface (5R) of the trench, a composition ratio of silicon to carbon is higher than in other portions of the first semiconductor layer,
a surface roughness of the bottom and side surfaces of the trench reduced,
an angle θ2 at which the upper surface of the first semiconductor layer (2) on a first side surface (5L) side is inclined with respect to the first side surface is smaller than an angle θ1 at which the upper surface of the first semiconductor layer (2) on a second side surface (R) side is inclined with respect to the second side surface, and
an angle θ4 formed by the upper surface of the first semiconductor layer (2) or the bottom surface of the trench after a heat treatment, and a direction perpendicular to a <0001> direction of the first semiconductor layer (2) , is 4 degrees with a variation of +/- 2 degrees. (See FIGs. 1, 3).
Regarding the limitation “a composition ratio of silicon to carbon is higher than in other portions of the first semiconductor layer”, due to the heat treatment, the composition ratio of silicon to carbon is higher than in other portions of the first semiconductor layer.
Product by process limitation:
The expression “an angle θ4 formed by the upper surface of the first semiconductor layer or the bottom surface of the trench after a heat treatment, and a direction perpendicular to a <0001> Direction of the first semiconductor layer, is 4 degrees with a variation of +/- 2 degrees”. is/are taken to be a product by process limitation and is given no patentable weight. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al., 218 USPQ 289, 292 (Fed. Cir. 1983); In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old and obvious product produced by a new method is not a patentable product, whether claimed in “product by process” claims or not.
Note that Applicant has burden of proof in such cases as the above case law makes clear.
Since the semiconductor device of KIYOSAWA being formed after the heat treatment, the limitation “an angle θ4 formed by the upper surface of the first semiconductor layer (2) or the bottom surface of the trench after a heat treatment, and a direction perpendicular to a <0001> direction of the first semiconductor layer (2) , is 4 degrees with a variation of +/- 2 degrees” is met.
Thus, KIYOSAWA ‘221 is shown to teach all the features of the claim with the exception of explicitly disclosing the trench has a bottom surface located in the first impurity region; and the surface roughness of the bottom and side surface of the trench being 1.5 nm or less.
However, TEGA teaches a semiconductor device including:
a trench (T) formed so as to penetrate second impurity region (8) and the third impurity region (9), wherein
the trench (T) has a bottom surface located in first impurity region (7B), a first side surface (L) in contact with the second impurity region (8), and a second side surface (R) in contact with the third impurity region (9) and facing the first side surface (L).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the bottom surface of the trench of KIYOSAWA being located in the first impurity region as taught by TEGA to alleviate electric field applied to gate insulation layer.
Further, KAWADA teaches a semiconductor device including:
after the heat treatment, a surface of the bottom and side surfaces of the trench (2) being 1.5 nm or less. (See Table 4, conditions 4-5, Table 5, conditions 8-12).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to reduce the surface roughness of the trench of KIYOSAWA ‘221 including performing the heat treatment conditions as taught by KAWADA to reduce surface roughness of the bottom and side surfaces of the trench being 1.5 nm or less, thus, providing the semiconductor device with high channel mobility.
With respect to claim 2, the angle θ1 and the angle θ2 of KIYOSAWA ‘221 and TEGA are each within a range of 80 degrees or more to 100 degrees or less.
With respect to claim 3, in view of KAWADA, a surface roughness of the upper surface of the first semiconductor layer (5) or the surface roughness of the bottom surface (12) of the trench (2) is 1 nm or less. (See Table 5).
With respect to claim 5, a planar shape of the trench (5) of KIYOSAWA ‘221 is a polygon having more corners than a quadrangle.
With respect to claim 6, an angle θ3 formed by the upper surface of the first semiconductor layer (2) or the bottom surface of the trench (5) and the <0001> direction of the first semiconductor layer of KIYOSAWA ‘221 is 88 degrees to 92 degrees.
With respect to claim 9, In view of TEGA, the first impurity region (7B) constitutes a channel region of a MISFET, the second impurity region (8) constitutes a part of a source region of the MISFET, and the third impurity region (9b) constitutes a part of a drain region of the MISFET. (See FIG. 6).
With respect to claim 10, in view of TEGA, a fourth impurity region (11) of the second conductivity type having an impurity concentration higher than that of the first impurity region (7B) is formed above the second impurity region (8S), and a fifth impurity region (11) of the second conductivity type having an impurity concentration higher than that of the first impurity region (7B) is formed above the third impurity region (9b).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over KIYOSAWA ‘221, KAWADA ‘620 and TEGA ‘754 as applied to claim 1 above, and further in view of SIEMIENIEC et al. (US. Pub. No. 2016/0163852) of record.
With respect to claim 7, KIYOSAWA teaches the semiconductor device as described in claim 1 above including a curvature radius of a first corner portion formed by the bottom surface (5B) and the first side surface (5L) of the trench.
Thus, KIYOSAWA, in view of KAWADA and TEGA, is shown to teach all the features of the claim with the exception of explicitly disclosing a curvature radius of the first corner.
However, SIEMIENIEC teaches a semiconductor device including a trench (110) formed in a substrate having a curvature radius of a first corner portion formed by a bottom surface (1103) and the first side surface (1101,2) of the trench is 300 nm, hence within 100 nm to 500 nm. (See FIG. 6D).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first corner of the trench of KIYOSAWA ‘221, in view of KAWADA and TEGA, having curvature radius as taught by SIEMIENIEC to for the same intended purpose of preventing the electric field from localizing thereto.
With respect to claim 8, in view of SIEMIENIEC, a curvature radius of a second corner portion formed by the upper surface or the first semiconductor layer and the first side surface is 300 nm, hence within 100 nm to 500 nm.
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANH D MAI/ Primary Examiner, Art Unit 2893