DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
Applicant’s amendments filed 2/20/2026 have been entered and considered. The amendment to claim 1 and the newly added claim 16 are acknowledged.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 and 15-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “one end of a side of the substrate of the first portion does not extend beyond a first surface on a side of the substrate of the first conductive layer in the first direction, as viewed from a side of the second conductive layer”. The limitation appears to suggest that the conductive layer has a side that faces the substrate. However, it can also be interpreted as suggesting the first portion has a substrate with a side but is being viewed from the perspective of the second conductive layer. It is not clear that structural feature the limitation is trying to convey. For purposes of examination, the limitation will be interpreted as the first portion does not extend in a direction from the second conductive layer to the substrate past a surface of the first conductive layer.
Claims 2-6, 9-12, and 15-16 are rejected based on their dependency on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6, 9-12 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. US 20220302150 A1 (hereinafter referred to as Zhang), in view of Kanamori et al. US 20210296358 A1 (hereinafter referred to as Kanmori).
Regarding claim 1, Zhang teaches
A semiconductor memory device (“3D memory device 100” para. 0064 FIG. 1A) comprising:
a substrate (“substrate 101” para. 0033 FIG. 1A), a first conductive layer (“source select gate line 201” para. 0047 FIG. 2), and a second conductive layer (“plate 121” of “doped semiconductor layer 122” para. 0050 FIG. 1A) arranged in this order in a first direction and separated from each other (they are arranged in a vertical direction and are separated);
a plurality of third conductive layers (“word lines 203” para. 0047 FIG. 1A and 2) provided between the first conductive layer and the substrate and stacked in the first direction (“word lines 203” are disposed between “source select gate line 201” and “substrate 101”, FIG. 1A and 2);
a first semiconductor film (“semiconductor channel 128” in rightmost “channel structure 124”, para. 0047 FIG. 1A and 2) including one end (the end of “doped portion 128a” of “semiconductor channel 128” in contact with “plate 121”, FIG. 1A) and another end (the end of “semiconductor channel 128” nearest the “substrate 101”, FIG. 1A) extending in the first direction, and intersecting the first conductive layer and the third conductive layers, the one end of the first semiconductor film being located on the second conductive layer (“semiconductor channel 128” extends through “memory stack 114”, which comprises “word lines 203” and “source select gate line 201”, and “doped portion 128a” and “plug 123” contact a lower surface portion of “plate 121”, para. 0049 FIG. 1A and 2.);
a first insulating layer (“filling layer 120”, which can be a high-k dielectric, para. 0043 FIG. 1A) provided between the first conductive layer and the second conductive layer;
a second insulating layer (“capping layer 127” para. 0044 FIG. 2) extending in the first direction and provided in the first semiconductor film; and
a first charge storage film (“storage layer (also known as a “charge trap layer”)” as part of “memory film 126” para. 0044 FIG. 2) arranged between the first semiconductor film, and the first conductive layer and the third conductive layers, and being in contact with the second conductive layer (“upper end of memory film 126 is flush with the upper end of semiconductor channel 128” para. 0046 FIG. 1A, where “semiconductor channel 128” is in contact with “plate 121” such that it is understood that “memory film 126” is also in contact with “plate 121”), wherein
the second insulating layer has one end located between the first conductive layer and one of the third conductive layers that is closest to the first conductive layer among the third conductive layers (“capping layer 127” has an end between topmost “word line 203” and “source select gate line 201”, FIG. 1A and 2),
the first semiconductor film includes a first portion formed of an n-type semiconductor at approximately a same height as the first conductive layer (“doped portion 128a” of “semiconductor channel 128” and “plug 123” extend to a similar height to where “source select gate line 201” is disposed, para. 0047 and 0050 FIG. 2. “Doped portion 128a” and “plug 123” are n-doped polysilicon, para. 0054.),
However, Zhang fails to teach one end of a side of the substrate of the first portion does not extend beyond a first surface on a side of the substrate of the first conductive layer in the first direction, as viewed from a side of the second conductive layer.
Nevertheless, Kanamori teaches
one end of a side of the substrate of the first portion does not extend beyond a first surface on a side of the substrate of the first conductive layer in the first direction, as viewed from a side of the second conductive layer (“tube 124” of “first impurity pattern 120” has a surface between upper and lower surfaces of “erasing control line ECL”, para. 0075 FIG. 4A).
Zhang and Kanamori teach three-dimensional memory that induces erase operations through gate induced drain leakage. While Zhang has an end of “doped portion 128a” and “plug 123” extending beyond “source select gate line 201” (Zhang para. 0047 FIG. 2), Kanamori has an end of “tube 24” in line with “erasing control line ECL”. Kanamori indicates that “the erasing control line ECL may overlap (e.g., overlap in a direction perpendicular to the extending direction of the channel hole) at least a part of the first impurity pattern 120, and the erasing operation through the gate induced drain leakage GIDL may be smoothly performed.” (para. 0075). Both configurations achieve gate induced drain leakage and are obvious to try. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having the end of “doped portion 128a” and “plug 123” not extending past “source select gate line 201” is a known alternative that also successfully produces gate induced drain leakage.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first portion of the first semiconductor film in Zhang as taught in Kanamori. The first portion not extending beyond the first surface of the first conductive layer is also suitable for performing an erase operation and was obvious to try.
Regarding claim 2, Zhang, modified by Kanamori, teaches the device of claim 1 and further teaches
wherein the first semiconductor film, at approximately a same height as the third conductive layer, has an impurity concentration lower than an impurity concentration of the first portion (“undoped portion 128b” is undoped and therefore has less impurity than “doped portion 128a” which ranges between 1019cm-3 and 1021cm-3, para. 0048).
Regarding claim 3, Zhang, modified by Kanamori, teaches the device of claim 1. Zhang further teaches
wherein the first portion includes phosphorous as an impurity (“doped portion 128a of semiconductor channel 128 includes N-type doped polysilicon” where “The dopant can be any suitable N-type dopants, such as phosphorus (P)”, para. 0048).
Regarding claim 4, Zhang, modified by Kanamori, teaches the device of claim 3 and further teaches
wherein a phosphorus concentration in the first portion (“doped portion 128a” of “semiconductor channel 128”, para. 0047, and “plug 123”, para. 0050 FIG. 2) is 1x10^19 atoms/cm3 or higher (“the doping concentration of doped portion 128a is between about 10.sup.19 cm.sup.-3 and about 10.sup.21 cm.sup.-3.” with “suitable N-type dopants, such as phosphorus (P), arsenic (Ar), or antimony (Sb)”, para. 0043.).
Regarding claim 5, Zhang teaches the device of claim 1 but fails to teach wherein the second conductive layer includes a metal material
Nevertheless, Kanamori teaches
wherein the second conductive layer includes a metal material (“first source structure 190 may include a first conductive plate 192a and a first barrier conductive film 194a”, para. 0052, where “first conductive plate 192a” is made of metal, para. 0053, and “first barrier conductive film 194a may include, but is not limited to, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof”, para. 0056, FIG. 10 and 11B.).
Zhang and Kanamori teach 3D memory devices with doping variations in the channel structure. The “first source structure 190” in Kanamori is connected to each channel just as the “plate 121” in Zhang connects to the channels. The “first barrier conductive film 194a” prevents diffusion of the material in “first conductive plate 192a” into the memory stack region. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that metal materials are known alternatives suitable for use are source signal lines. Furthermore, the use of a barrier layer can improve the integrity of the source signal line.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device taught in Zhang with the second conductive layer taught in Kanamori. Metals are known materials used as source signal lines and the electrical performance can be ensured with the inclusion of a barrier layer.
Regarding claim 6, Zhang, modified by Kanamori, teaches the device of claim 5. Zhang further teaches
the first insulating layer (“filling layer 120”, which can be a high-k dielectric, para. 0043 FIG. 1A) arranged between the first conductive layer (“source select gate line 201”) and the second conductive layer (“plate 121”) in such a manner as to intersect the first semiconductor film and the first charge storage film (“filling layer 120” extends horizontally along FIG. 1A and 2 and intersects the “memory film 126” and “semiconductor channel 128” as seen in FIG. 2), the first insulating layer is in contact with the second conductive layer (“filling layer 120” contacts “plate 121” , as seen in FIG. 1A).
Regarding claim 9, Zhang, modified by Kanamori, teaches the device of claim 1 and further teaches
wherein the second conductive layer is a source line (“doped semiconductor layer 122 may provide electrical connections between the sources of an array of NAND memory strings in the same block”, para. 0049, such that “plate 121” is at least part of a source line).
Regarding claim 10, Zhang, modified by Kanamori, teaches the device of claim 1 and further teaches
the device further comprising: a second semiconductor film extending in the first direction (leftmost “semiconductor channel 128”, para. 0068, para. 0047 FIG. 1A), intersecting the first conductive layer, and being in contact with the second conductive layer (“semiconductor channel 128” intersects the “source select gate line 201” and is in contact with the “plate 121” of “doped semiconductor layer 122”, para. 0049 FIG. 1A); and
a second charge storage film arranged between the second semiconductor film and the first conductive layer (“storage layer (also known as a “charge trap layer”)” as part of “memory film 126” para. 0044, in the leftmost “channel structure 124” in FIG. 1A), and being in contact with the second conductive layer (“upper end of memory film 126 is flush with the upper end of semiconductor channel 128” para. 0046 FIG. 1A, where “semiconductor channel 128” is in contact with “plate 121” such that it is understood that “charge trap layer is in contact with “plate 121”), wherein
the second semiconductor film includes a second portion (“semiconductor channel 128” has a “doped portion 128a” para. 0047 FIG. 2) formed of an n-type semiconductor (“doped portion 128a of semiconductor channel 128 includes N-type doped polysilicon” where “The dopant can be any suitable N-type dopants, such as phosphorus (P)”, para. 0048) at approximately a same height as the first conductive layer (“doped portion 128a” extends to a similar height to where “source select gate line 201” is disposed, para. 0047 FIG. 2), and
the first portion has approximately a same impurity concentration as an impurity concentration of the second portion (it is understood from the disclosure in Zhang, in particular para. 0044, that each “channel structure 124” and the layers within are all the same, such that the materials and impurities of “semiconductor layer 128” in each “channel structure 124” are the same).
Regarding claim 11, Zhang, modified by Kanamori, teaches the device of claim 1 and further teaches
a fifth conductive layer arranged between the substrate and the first conductive layer (“Each channel local contact 150 can be electrically connected to a bit line contact (not shown) for bit line fan-out”, para. 0062. Though not explicitly shown in FIG. 1A, it is understood that the connection of “channel contacts 150” to a bit line occurs between “substrate 101” and “source select gate line 201”) and electrically coupled to the first semiconductor film (“channel local contacts 150 each below and in contact with the lower end of respective channel structure 124” para. 0153),
wherein the fifth conductive layer is a bit line (as the name “bit line contact” suggests).
Regarding claim 12, Zhang teaches the device of claim 1 and further teaches
the device further comprising: an electrode pad arranged above the first conductive layer (“contact pad 140”, para. 0059, above “source select gate line 201” as seen in FIG. 1A) and configured to be connectable with an external device (“contact pads 140 for wire bonding and/or bonding with an interposer”, para. 0059 FIG. 1A);
a first contact (“peripheral contact 148” para. 0061) extending in the first direction between the substrate and the electrode pad and being in contact with the electrode pad (“peripheral contact 148” is connected to the “contact pad 140” through the “contact 144”, para. 0061, and is between “contact pad 140” and “substrate 101” as seen in FIG. 1A);
a first circuit (rightmost “peripheral circuits 108” para. 0034 annotated FIG. 1A) and a second circuit (leftmost “peripheral circuits 108” FIG. 1A) arranged on the substrate and configured to control storage of charges in the first charge storage film at portions intersecting the third conductive layers (from para. 0035 “peripheral circuit 108 is configured to control and sense 3D memory device 100. Peripheral circuit 108 can be any suitable digital, analog, and/or mixed-signal control and sensing circuits used for facilitating the operation of 3D memory device 100”, the examiner understands that the first and second circuits have the capability to control the current flow and the charges held in the nonvolatile memory device);
a first joint metal (“bonding contact 113” connected to “peripheral contact 148”, para. 0038 FIG. 1A),
a second joint metal (“bonding contact 113” connected to “channel local contacts 150” FIG. 1A),
wherein the first joint metal and the second joint metal are on a same plane orthogonal to the first direction (“bonding contacts 113” are part of the “bonding layer 112” on the bottom of the “semiconductor structure 104” and can be considered to be on the same plane, as seen in FIG. 1A).
However, Zhang fails to teach a second contact extending in the first direction between the substrate and the fifth conductive layer and being in contact with the fifth conductive layer; a first joint metal coupled to the first circuit and coupled to the first contact; and a second joint metal coupled to the second circuit and coupled to the second contact; the first contact, the second contact, the first joint metal, and the second joint metal are arranged for coupling a part comprising the first conductive layer, the second conductive layer, the third conductive layers, the first charge storage film, and the electrode pad, and a part comprising the first circuit and the second circuit.
Nevertheless, Kanamori teaches
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a second contact (“first via 24” under “bit line BL” para. 0094 annotated FIG. 10) extending in the first direction between the substrate and the fifth conductive layer and being in contact with the fifth conductive layer (“first wiring structure PW1 may include a first wiring 22 and a first via 24”, para. 0094, and “bit line BL may be connected to the first peripheral circuit element PT1 through the first wiring structure PW1 and the second wiring structure PW2”, para. 0101. As seen in annotated FIG. 10, a “first via 24” is connected to “bit line BL” above the “substrate 30”);
a first joint metal (“first wiring 22” above “fourth peripheral circuit element PT4”, para. 0094 annotated FIG. 10) coupled to the first circuit and coupled to the first contact (“first wiring 22” is part of “first wiring structure PW1” and it can be seen in annotated FIG. 10 that “(“input/output contact 176”, “first wiring structure PW1” and “fourth peripheral circuit element PT4” are electrically coupled); and
a second joint metal (“first wiring 22” above “first peripheral circuit element PT1” in annotated FIG. 10) coupled to the second circuit and coupled to the second contact (“first wiring 22” is electrically coupled to “first peripheral circuit element PT1” and the “first via 24” above it as seen in annotated FIG. 10),
the first contact, the second contact, the first joint metal, and the second joint metal are arranged for coupling a part comprising the first conductive layer, the second conductive layer, the third conductive layers, the first charge storage film, and the electrode pad, and a part comprising the first circuit and the second circuit (“input/output contact 176” and “first wiring 22” above “fourth peripheral circuit element PT4” are electrically coupled to the “input/output pad 195” while the “first via 24” under “bit line BL” and the “first wiring 22” above “first peripheral circuit element PT1” are electrically coupled to the “erasing control line ECL”, “first source structure 190”, “ground selection line GSL” and “plurality of word lines WL11 to WL1n” and “a charge storage film 132b” through the “first bit line contact 170”, para. 0087 annotated FIG. 10. Meanwhile, “input/output contact 176” and “first wiring 22” above “fourth peripheral circuit element PT4” are electrically coupled to the “fourth peripheral circuit element PT4” while the “first via 24” under “bit line BL” and the “first wiring 22” above “first peripheral circuit element PT1” are electrically coupled to the “first peripheral circuit element PT1”, as seen in annotated FIG. 10).
Zhang and Kanamori teach 3D memory devices with doping variations in the channel structure. Though the “peripheral circuits 108” in Zhang are taught to control the “3D memory device 100”, no interconnect structures between them are shown. Meanwhile, Kanamori teaches a how the “fourth peripheral circuit element PT4”, a “first wiring 22”, “input/output contact 176”, and “input/output pad 195” are interconnected and how the “first peripheral circuit element PT1”, a “first wiring 22”, “first via 24”, “bit line BL”, “erasing control line ECL”, “first source structure 190”, “ground selection line GSL” and “plurality of word lines WL11 to WL1n” and “a charge storage film 132b” are interconnected. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the interconnection structure in Kanamori can be used to connect the “peripheral circuits 108” with the “channel structures 124”, “peripheral structures 148”, and “contact pad 140” in Zhang.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device taught in Zhang with the first contact, the second contact, the first joint metal, and the second joint metal as taught in Kanamori. The conductive structures interconnect the first and second circuits to the rest of the device so they may operate the device.
Regarding claim 15, Zhang, modified by Kanamori, teaches the device of claim 1, wherein the first insulating layer is a single layer of insulating material between the first conductive layer and the second conductive layer (as the name and the figures suggest, “filling layer 120” is a layer of a high-k dielectric and it is understood to be a single layer).
Regarding claim 16, Zhang, modified by Kanamori, teaches the device of claim 1, wherein the one end on the side of the substrate of the first portion is positioned between a position in the first direction of the first surface of the first conductive layer and a position in the first direction of a second surface opposite to the first surface of the first conductive layer in the first direction (“tube 124” of “first impurity pattern 120” has a surface between upper and lower surfaces of “erasing control line ECL”, para. 0075 FIG. 4A).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached on (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC MANUEL MULERO FLORES/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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