DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Applicant’s amendments to claims 1, 8, 9, 16, and 17 in the reply dated 27 October 2025 are acknowledged. Claims 3, 5, 11, 13, and 19 were previously cancelled.
Claim Objections
Claim 17 is objected to because of the following informalities: The phrase “...and a second sidewall of the sidewall of the top via...” appears to include a meaningless prepositional phrase --of the sidewall--. For the purpose of examination, this prepositional phrase will be ignored. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 7, 9-10, 12, 15, 17-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ren et al (US 20210233770 A1, hereafter “Ren”), in view of Nelle et al (US 20060035458 A1, hereinafter “Nelle”), and further in view of Jiang et al (US 20200135459 A1, hereinafter “Jiang”).
Regarding Claim 1 – Ren discloses the metal line directly contacting a top via (Ren [0045], Metal Line and Top Vias in annotated Ren Fig. 13); the metal line and top via are composed of a horizontally oriented alternating stack of layers (108 Ren [0058], 110 [0059], 112 [0078], and 114 [0080] and Ren Fig. 5A represent alternating layers) of a first metal (108 [0058], and 112 [0078]) and a second metal (110 [0059], and 114 [0080]).
Ren fails to disclose an interconnect structure comprising: a metal line composed of a horizontally oriented alternating stack of layers of a first metal and a second metal; the first metal is between 5 nanometers (nm) and 9 nm; and each layer of the second metal is between 0.1 nm and 0.4 nm.
However, Nelle discloses an interconnect structure comprising: a metal line composed of a horizontally oriented alternating stack of layers ([0035] and Fig. 2) of a first metal (11, 13, 15, and 17 [0035]) and a second metal (12, 14, 16, and 18 [0035]); the first metal is between 5 nanometers (nm) and 9 nm (1 to 1000 nm [0037]); and each layer of the second metal is between 0.1 nm and 0.4 nm (less than 40 nm [0036]).
Nelle is in the same field of metallization for semiconductor devices as Ren. Nelle teaches using four first and four second alternating metal layers for the benefit of preventing stress cracks in surrounding dielectric (Nelle [0008]-[0010], [0035]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Ren and Nelle by using layered metal with alternating layers in a subtractively formed self-aligned top via on metal line structure to achieve the expected outcome of preventing stress cracks in the surrounding dielectric.
The claimed thickness ranges for first and second metal layers are within the overlapping ranges disclosed by Nelle. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have selected the overlapping portion of the ranges disclosed by Nelle because selection of overlapping portion of ranges has been held to be a prima facie case of obviousness. See MPEP § 2144.05(I).
The combination of Ren and Nelle fails to expressly disclose a first sidewall of the top via is coplanar with a sidewall of the metal line; a second sidewall of the top via, directly opposite the first sidewall and laterally offset from any sidewall of the metal line, terminates on a top surface of the metal line.
However, Jiang discloses a first sidewall of the top via is coplanar with a sidewall of the metal line (SW1 in annotated Jiang Fig. 10A); a second sidewall of the top via, directly opposite the first sidewall and laterally offset from any sidewall of the metal line, terminates on a top surface of the metal line (SW2 (hidden from view) in annotated Jiang Fig. 10A).
Jiang discloses a very similar metal line and via structure to Ren. Jiang teaches a first sidewall of the top via can be coplanar with a sidewall of the metal line for the benefit of placing a via at the end of a metal line (as shown in Jiang Fig. 10A). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to find the teachings of Ren and Jiang to consider placing a first sidewall of the top via coplanar with the sidewall of the metal line for the benefit of placing of via at the end of a metal line.
PNG
media_image1.png
295
575
media_image1.png
Greyscale
PNG
media_image2.png
361
471
media_image2.png
Greyscale
PNG
media_image3.png
482
476
media_image3.png
Greyscale
PNG
media_image4.png
287
351
media_image4.png
Greyscale
Regarding Claim 2 – Ren modified by Nelle and Jiang discloses all the limitations of claim 1.
The combination of Ren, Nelle, and Jiang further discloses the metal line and the top via each include at least four layers of the first metal (11, 13, 15, and 17, Nelle [0035] and Fig. 2) and at least four layers of the second metal (12, 14, 16, and 18, Nelle [0035] and Fig. 2).
Regarding Claim 4 – Ren modified by Nelle and Jiang discloses all the limitations of claim 1.
The combination of Ren, Nelle, and Jiang further discloses a dielectric material surrounding the metal line and the top via (Ren [0055]).
Regarding Claim 7 – Ren modified by Nelle and Jiang discloses all the limitations of claim 1.
The combination of Ren, Nelle, and Jiang further discloses the second metal (etch stop layer 110 interpreted as the second metal) is molybdenum (Ren [0059]).
Regarding Claim 9 – Ren discloses an interconnect structure comprising: a diffusion barrier (106 [0057]), a metal line (108 [0057] and 110 [0059]) above and contacting the diffusion barrier ([0077] and Fig. 5A), and a top via (Top Vias in annotated Fig. 13, 202 and 204 [0086] and [0095]) above and directly contacting the metal line, and the top via includes a horizontally oriented alternating stack of a plurality of layers of a first metal and second metal (108 [0058], 110 [0059], 112 [0078], and 114 [0080] and Ren Fig. 5A represent alternating layers).
Ren fails to disclose the metal line and the top via each include a horizontally oriented alternating stack of a plurality of layers of a first metal and a second metal; the first metal is between 5 nanometers (nm) and 9 nm; and each layer of the second metal is between 0.1 nm and 0.4 nm.
However, Nelle discloses the metal line includes a horizontally oriented alternating stack of a plurality of layers ([0035] and Fig. 2) of a first metal (11, 13, 15, and 17 [0035]) and a second metal (12, 14, 16, and 18 [0035]); the first metal is between 5 nanometers (nm) and 9 nm (1 to 1000 nm [0037]); and each layer of the second metal is between 0.1 nm and 0.4 nm (less than 40 nm [0036]).
Nelle is in the same field of metallization for semiconductor devices as Ren. Nelle teaches using four first and four second alternating metal layers for the benefit of preventing stress cracks in surrounding dielectric (Nelle [0008]-[0010], [0035]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Ren and Nelle by using layered metal with alternating layers in a subtractively formed self-aligned top via on metal line structure to achieve the expected outcome of preventing stress cracks in the surrounding dielectric.
Nelle fails to disclose the top via includes a horizontally oriented alternating stack of a plurality of layers of a first metal and second metal. However, since the metal line and top via of Ren have the same structure and are formed together, applying the alternating stack of a plurality of layers to the top via is the same as applying it to the metal line and represents a duplication of parts. Therefore, applying the same alternating layer structure to the top via has no patentable significance. See MPEP 2144.04(VI)(B).
The claimed thickness ranges for first and second metal layers are within the expected ranges disclosed in the prior art as disclosed by Nelle. More specifically, the claimed ranges are at the low end of both ranges, consistent with the expectation of shrinking feature sizes in semiconductor chips as suggested by Ren ([0002]-[0003]), and further motivates the top via and metal line structure disclosed by Ren in order to minimize the resistance of shrinking interconnect feature sizes ([0046] and [0099]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have selected the overlapping portion of the ranges disclosed by Nelle because selection of overlapping portion of ranges has been held to be a prima facie case of obviousness. See MPEP § 2144.05(I).
The combination of Ren and Nelle fails to expressly disclose a first sidewall of the top via is coplanar with a sidewall of the metal line; a second sidewall of the top via, directly opposite the first sidewall and laterally offset from any sidewall of the metal line, terminates on a top surface of the metal line.
However, Jiang discloses a first sidewall of the top via is coplanar with a sidewall of the metal line (SW1 in annotated Jiang Fig. 10A); a second sidewall of the top via, directly opposite the first sidewall and laterally offset from any sidewall of the metal line, terminates on a top surface of the metal line (SW2 (hidden from view) in annotated Jiang Fig. 10A).
Jiang discloses a very similar metal line and via structure to Ren. Jiang teaches a first sidewall of the top via can be coplanar with a sidewall of the metal line for the benefit of placing a via at the end of a metal line (as shown in Jiang Fig. 10A). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to find the teachings of Ren and Jiang to consider placing a first sidewall of the top via coplanar with the sidewall of the metal line for the benefit of placing of via at the end of a metal line.
Regarding Claim 10 – Ren modified by Nelle and Jiang discloses all the limitations of claim 9.
The combination of Ren, Nelle, and Jiang further discloses the metal line and the top via each include at least four layers of the first metal (11, 13, 15, and 17, Nelle [0035] and Fig. 2) and at least four layers of the second metal (12, 14, 16, and 18, Nelle [0035] and Fig. 2).
Regarding Claim 12 – Ren modified by Nelle and Jiang discloses all the limitations of claim 9.
The combination of Ren, Nelle, and Jiang further discloses a dielectric material surrounding the metal line and the top via (Ren [0055]).
Regarding Claim 15 – Ren modified by Nelle and Jiang discloses all the limitations of claim 9.
The combination of Ren, Nelle, and Jiang further discloses the second metal (etch stop layer 110 interpreted as the second metal) is molybdenum (Ren [0059]).
Regarding Claim 17 – Ren discloses a method comprising: forming a diffusion barrier (106 [0057]); forming, on the diffusion barrier, a horizontally oriented alternating stack of layers of a first metal and a second metal (108 [0058], 110 [0059], 112 [0078], and 114 [0080] and Ren Fig. 5A represent alternating layers); and forming a plurality of top vias ([0045]) within the alternating stack by patterning a hardmask ([0082]) and etching a first subset of layers of the alternating stack (etch stop second metal 204, and via first metal 202 [0090] and [0094], and Ren Fig. 13), such that a second subset of layers of the alternating stack remain (metal line first metal 212 and etch stop second metal 210 [0094]), wherein the second subset of layers of the alternating stack form a metal line (Metal Line layers 210 and 212 in annotated Ren Fig. 13) contacting each top via (Top Vias in annotated Ren Fig. 13) of the plurality of top vias (stack of layers including line metal and etch stop to form conductive pillars considered as vias [0099]); forming a second hardmask on top of the plurality of top vias (124 [0091] and Fig. 10), wherein the second hardmask is also on top of a location between the plurality of top vias (Fig. 10); and etching portions of the second subset of layers of the alternating stack that are unprotected by the second hardmask ([0094] and Fig. 12).
Ren fails to disclose each layer of the first metal is between 5 nanometers (nm) and 9 nm; and each layer of the second metal is between 0.1 nm and 0.4 nm; the first subset of layers comprises a first plurality of layers of the first metal and a first plurality of layers of the second metal; the second subset of layers comprises a second plurality of layers of the first metal and a second plurality of layers of the second metal.
However, Nelle discloses each layer of the first metal is between 5 nanometers (nm) and 9 nm (1 to 1000 nm [0037]); and each layer of the second metal is between 0.1 nm and 0.4 nm (less than 40 nm [0036]); the second subset of layers comprises a second plurality of layers of the first metal (11, 13, 15, and 17 ([0035] and Fig. 2) and a second plurality of layers of the second metal (12, 14, 16, and 18 ([0035] and Fig. 2).
Nelle is in the same field of metallization for semiconductor devices as Ren. Nelle teaches using four first and four second alternating metal layers for the benefit of preventing stress cracks in surrounding dielectric (Nelle [0008]-[0010], [0035]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Ren and Nelle by using layered metal with alternating layers in a subtractively formed self-aligned top via on metal line structure to achieve the expected outcome of preventing stress cracks in the surrounding dielectric.
The combination of Ren and Nelle further discloses the first subset of layers comprises a first plurality of layers of the first metal and a first plurality of layers of the second metal, since the first subset is a repeated instance of the second subset. The first and second subsets of layers are a case of duplication of parts. See MPEP 2144.04(VI)(B).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the metal line and top via structures by applying the multilayer metal stack to both the first and second subsets of layers in a duplication of parts.
The combination of Ren and Nelle fails to expressly disclose for a first top via of the plurality of top vias, a first sidewall of the top via is coplanar with a sidewall of the metal line; and a second sidewall of the top via, directly opposite the first sidewall and laterally offset from any sidewall of the metal line, terminates on a top surface of the metal line.
However, Jiang discloses for a first top via of the plurality of top vias, a first sidewall of the top via is coplanar with a sidewall of the metal line (SW1 in annotated Jiang Fig. 10A); a second sidewall of the top via, directly opposite the first sidewall and laterally offset from any sidewall of the metal line, terminates on a top surface of the metal line (SW2 (hidden from view) in annotated Jiang Fig. 10A).
Jiang discloses a very similar metal line and via structure to Ren. Jiang teaches a first sidewall of the top via can be coplanar with a sidewall of the metal line for the benefit of placing a via at the end of a metal line (as shown in Jiang Fig. 10A). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to find the teachings of Ren and Jiang to consider placing a first sidewall of the top via coplanar with the sidewall of the metal line for the benefit of placing of via at the end of a metal line.
PNG
media_image5.png
437
560
media_image5.png
Greyscale
PNG
media_image6.png
432
519
media_image6.png
Greyscale
Regarding Claim 18 – Ren modified by Nelle and Jiang discloses all the limitations of claim 17.
The combination of Ren, Nelle, and Jiang further discloses the metal line and the plurality of top vias each include at least four layers of the first metal (11, 13, 15, and 17, Nelle [0035] and Fig. 2) and at least four layers of the second metal (12, 14, 16, and 18, Nelle [0035] and Fig. 2).
Regarding Claim 20 – Ren modified by Nelle and Jiang discloses all the limitations of claim 17.
The combination of Ren, Nelle, and Jiang further discloses forming a dielectric material surrounding the metal line and the plurality of top vias (Ren [0055]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ren et al (US 20210233770 A1, hereafter “Ren”), in view of Nelle et al (US 20060035458 A1, hereinafter “Nelle”), and further in view of Jiang et al (US 20200135459 A1, hereinafter “Jiang”), and further in view of Park et al (US 20210313264 A1, hereinafter “Park”).
Regarding Claim 6 – Ren modified by Nelle and Jiang discloses all the limitations of claim 1.
The combination of Ren, Nelle, and Jiang fails to disclose the first metal is rhodium.
However, Park discloses the first metal is rhodium (layers 18 and 20 [0038] and Fig. 11).
Park is analogous in describing a metallization structure for semiconductor devices. Park teaches using rhodium as the first metal for the benefit of stability in contact with dielectrics (Park [0038]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Ren, Nelle, Jiang and Park to use rhodium as the first metal for the benefit of stability in contact with dielectrics.
Regarding Claim 14 – Ren modified by Nelle and Jiang discloses all the limitations of claim 9.
The combination of Ren, Nelle, and Jiang fails to disclose the first metal is rhodium.
However, Park discloses the first metal is rhodium (layers 18 and 20 [0038] and Fig. 11).
Park is analogous in describing a metallization structure for semiconductor devices. Park teaches using rhodium as the first metal for the benefit of stability in contact with dielectrics (Park [0038]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Ren, Nelle, Jiang, and Park to use rhodium as the first metal for the benefit of stability in contact with dielectrics.
PNG
media_image7.png
406
552
media_image7.png
Greyscale
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ren et al (US 20210233770 A1, hereafter “Ren”), in view of Nelle et al (US 20060035458 A1, hereinafter “Nelle”), and further in view of Jiang et al (US 20200135459 A1, hereinafter “Jiang”), and further in view of Rocklein et al (US 20150102460 A1, hereinafter “Rocklein”).
Regarding Claim 8 – Ren modified by Nelle and Jiang discloses all the limitations of claim 1.
The combination of Ren, Nelle, and Jiang fails to expressly disclose the second metal is molybdenum nitride.
However, Ren teaches the etch stop layers 110 and 114 (considered to be second metal layers) may include molybdenum or tantalum nitride (Ren [0059] and [0080]), and molybdenum nitride is a combinations of these materials. It is prima facie obvious to combine two known compositions to form a third composition for the same purpose. See MPEP 2144.06(I).
Furthermore, Rocklein discloses using molybdenum nitride in semiconductor structures for the benefit of low leakage through adjacent dielectric material (Rocklein [0033]). Therefore, it would have been obvious to one skilled in the art prior to the effective filing date of the claimed invention to consider using molybdenum nitride for the second metal for the benefit of low leakage through adjacent dielectric material.
Regarding Claim 16 – Ren modified by Nelle and Jiang discloses all the limitations of claim 9.
The combination of Ren, Nelle, and Jiang fails to expressly disclose the second metal is molybdenum nitride.
However, Ren teaches the etch stop layers 110 and 114 (considered to be second metal layers) may include molybdenum or tantalum nitride (Ren [0059] and [0080]), and molybdenum nitride is a combinations of these materials. It is prima facie obvious to combine two known compositions to form a third composition for the same purpose. See MPEP 2144.06(I).
Furthermore, Rocklein discloses using molybdenum nitride in semiconductor structures for the benefit of low leakage through adjacent dielectric material (Rocklein [0033]). Therefore, it would have been obvious to one skilled in the art prior to the effective filing date of the claimed invention to consider using molybdenum nitride for the second metal.
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON MCDONALD/Examiner, Art Unit 2898
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898