Prosecution Insights
Last updated: October 02, 2026
Application No. 17/643,594

PILLAR MEMORY TOP CONTACT LANDING

Non-Final OA §102§103§112
Filed
Dec 10, 2021
Examiner
MCDONALD, JASON ANDREW
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
4 (Non-Final)
57%
Grant Probability
Moderate
4-5
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 57% of resolved cases
57%
Career Allowance Rate
4 granted / 7 resolved
-10.9% vs TC avg
Strong +80% interview lift
Without
With
+80.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
48 currently pending
Career history
63
Total Applications
across all art units

Statute-Specific Performance

§103
65.2%
+25.2% vs TC avg
§102
20.5%
-19.5% vs TC avg
§112
13.9%
-26.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 7 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Status The examiner acknowledges amendments made to claims 1, 4, and 9 in the reply dated 17 July 2026. Claims 5 and 11-20 were previously withdrawn. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claim 3 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Claim 3 is a product-by-process claim containing a limitation referring to a via, wherein the structural element included as a via is unclear. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed conductive etch stop layer need not be formed by the process of forming a via. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 6-7, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Doyle et al (US 20160351238 A1, hereinafter “Doyle”). Regarding Claim 1 – Doyle discloses a semiconductor device comprising: a first electrode (202 [0020] and Fig. 2I); an MRAM stack formed on the first electrode (210 [0021] and Fig. 2I); a hardmask structure formed on the MRAM stack (240 [0024] and Fig. 2I); a conductive etch stop layer formed around the hardmask structure (252 [0028] and Fig. 2I); and a second electrode formed on the hardmask structure and formed on and directly contacting at least a portion of the conductive etch stop layer (204 [0033] and Fig. 2I). Regarding Claim 2 – Doyle further discloses the semiconductor device according to claim 1, wherein a top surface of the conductive etch stop layer is coplanar with a top surface of the hardmask layer (Fig. 2I). Regarding Claim 3 – Doyle further discloses the semiconductor device according to claim 1, further comprising: an encapsulation layer formed around the MRAM stack and the hardmask structure (201 [0033] and Fig. 2I); wherein the conductive etch stop layer is formed in a via that is formed into the encapsulation layer (252 and the additional layers surrounded by 201 can be considered to be in a via, Fig. 2I). Regarding Claim 6 – Doyle further discloses the semiconductor device according to claim 3, wherein the encapsulation layer is a Si-based oxide or nitride (201 same as 200, which may be Si-based oxide or nitride, Doyle [0020] and Fig. 2G). PNG media_image1.png 178 469 media_image1.png Greyscale Regarding Claim 7 – Doyle further discloses the semiconductor device according to claim 1, wherein the hardmask structure comprises at least one of Nb, NbN, W, WN, Ta, TaN, Ti, TiN, Ru, Mo, Cr, V, Pd, Pt, Rh, Sc, Al and other high melting point metals or conductive metal nitrides (Doyle [0024]). Regarding Claim 10 – Doyle further discloses the semiconductor device according to claim 1, wherein a material composition of the hardmask structure is the same as a material composition of the etch stop layer (240 and 250 (layer which forms 252) may comprise the same material, Doyle [0027]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Doyle et al (US 20160351238 A1, hereinafter “Doyle”), in view of Rizzolo et al (US 20200127194 A1, hereinafter “Rizzolo”). Regarding Claim 4 – Doyle discloses all the limitations of claim 3. Doyle fails to disclose a liner layer between the encapsulation layer and the conductive etch stop layer. However, Rizzolo discloses a liner layer between the encapsulation layer and the conductive etch stop layer (462, Rizzolo [0039]). Rizzolo discloses an MTJ stack with surrounding layers, similar to Doyle. Rizzolo teaches using a liner layer between the encapsulation layer (438, Rizzolo [0036] and Fig. 9) and the top contact (464 [0039] and Fig. 9), which is an example of placing a barrier between a metal and a dielectric. Positioning a barrier between a metal and a dielectric is a common industry practice to prevent metal diffusion into the dielectric. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Doyle and Rizzolo to position a liner layer between the encapsulation layer and the conductive etch stop layer for the benefit of preventing metal diffusion into the dielectric. PNG media_image2.png 587 619 media_image2.png Greyscale Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Doyle et al (US 20160351238 A1, hereinafter “Doyle”), in view of Chuang et al (US 20220352457 A1, hereinafter “Chuang”). Regarding Claim 8 – Doyle discloses all the limitations of claim 3. Doyle fails to disclose a width of a bottom surface of the second electrode is less than a combined width of the hardmask structure and the encapsulation layer. However, Chuang discloses a width of a bottom surface of the second electrode is less than a combined width of the hardmask structure and the encapsulation layer (The width Y1 is less than the width X1, Chuang [0060] and Fig. 19). Chuang Discloses an MTJ stack with surrounding layers, similar to Rizzolo. Chuang teaches a second electrode on the hardmask structure with a width less than a combined width of the hardmask structure and the encapsulation layer for the benefit of good overlay control and improved process window of the top electrode (Chuang [0060]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Rizzolo and Chuang to include a second electrode on the hardmask structure with a width less than a combined width of the hardmask structure and the encapsulation layer for the benefit of good overlay control and improved process window of the top electrode. PNG media_image3.png 434 598 media_image3.png Greyscale Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Doyle et al (US 20160351238 A1, hereinafter “Doyle”), in view of Muthinti et al (US 20200219932 A1, hereinafter “Muthinti”). Regarding Claim 9 – Doyle discloses all the limitations of claim 1. Doyle further discloses the second electrode includes a metal layer (204, Doyle [0033]). Doyle fails to disclose a metal liner layer formed between the hardmask structure and metal layer. However, Muthinti discloses a metal liner layer formed between the underlying structure and metal layer (Muthinti [0045]). Muthinti discloses stacked interconnect structures analogous to the combination of Rizzolo and Doyle. Muthinti teaches liner layers may be used for the benefit of ensuring that a bulk metal will not further diffuse into underlying dielectric layers or along sidewall interfaces during subsequent annealing processes (Muthinti [0045]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to include a liner layer for the benefit of ensuring that a bulk metal will not further diffuse into underlying dielectric layers or along sidewall interfaces during subsequent annealing processes. Response to Arguments Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JASON MCDONALD/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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Prosecution Timeline

Show 10 earlier events
May 18, 2026
Final Rejection mailed — §102, §103, §112
Jul 08, 2026
Interview Requested
Jul 17, 2026
Response after Non-Final Action
Aug 18, 2026
Request for Continued Examination
Aug 20, 2026
Response after Non-Final Action
Sep 17, 2026
Non-Final Rejection mailed — §102, §103, §112
Sep 29, 2026
Applicant Interview (Telephonic)
Sep 29, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12697688
SEMICONDUCTOR DEVICE MANUFACTURING DEVICE AND MANUFACTURING METHOD
3y 5m to grant Granted Aug 04, 2026
Patent 12666616
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 5m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 2 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
57%
Grant Probability
99%
With Interview (+80.0%)
3y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 7 resolved cases by this examiner. Grant probability derived from career allowance rate.

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