Prosecution Insights
Last updated: July 17, 2026
Application No. 17/643,594

PILLAR MEMORY TOP CONTACT LANDING

Final Rejection §102§103
Filed
Dec 10, 2021
Examiner
MCDONALD, JASON ANDREW
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
3 (Final)
50%
Grant Probability
Moderate
4-5
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 50% of resolved cases
50%
Career Allowance Rate
2 granted / 4 resolved
-18.0% vs TC avg
Strong +100% interview lift
Without
With
+100.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
41 currently pending
Career history
57
Total Applications
across all art units

Statute-Specific Performance

§103
93.1%
+53.1% vs TC avg
§102
4.3%
-35.7% vs TC avg
§112
2.1%
-37.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 4 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Status The amendment to claim 1 is acknowledged in the response dated 26 February 2026. Claims 5 and 11-20 were previously withdrawn. Claim Objections Claim 1 is objected to because of the following informalities: The phrase “...on a least a portion of the conductive etch stop layer” appears to be intended to read “...on at least a portion of the conductive etch stop layer”, with the word --at-- replacing --a--. Examination will follow this interpretation. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chuang et al (US 20200365795 A1, hereinafter “Chuang”). Regarding Claim 1 – Chuang discloses a semiconductor device comprising: a first electrode (106 [0027] and Fig. 2B); an MRAM stack formed on the first electrode (104 [0018] and Fig. 2B); a hardmask structure formed on the MRAM stack (118 [0019] and Fig. 2B); a conductive etch stop layer formed around the hardmask structure (120 [0017] and Fig. 2B); and a second electrode layer formed on the hardmask structure and on at least a portion of the conductive etch stop layer (224 is directly on 118, and 224 is on 120 as seen by “Direction of View” indicators in annotated Fig. 2B). PNG media_image1.png 321 366 media_image1.png Greyscale Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4 and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Rizzolo et al (US 20200127194 A1, hereinafter “Rizzolo”), in view of Chuang et al (US 20200365795 A1, hereinafter “Chuang”). Regarding Claim 1 – Rizzolo discloses a semiconductor device comprising: a first electrode (442 [0033]); an MRAM stack (450A [0033]) formed on the first electrode; a hardmask structure (considered as 456A [0033]) formed on the MRAM stack; a conductive etch stop layer (considered as 464 [0039]) formed around the hardmask structure. Rizzolo fails to disclose a second electrode layer formed on the hardmask structure and on at least a portion of the conductive etch stop layer. However, Chuang discloses a second electrode layer (224, Chuang [0026] and Fig. 2B) formed on the hardmask structure (118, Chuang [0019] and Fig. 2B) and on at least a portion of the conductive etch stop layer (224 is on 120 as seen by “Direction of View” indicators in annotated Fig. 2B). Chuang Discloses an MTJ stack with surrounding layers, similar to Rizzolo. Chuang teaches a second electrode on the hardmask structure to enable the well-known benefit of connecting the device to a top conductive wire (Chuang [0030]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Rizzolo and Chuang to include a second electrode on top of the MTJ device for the well-known benefit of connecting the device to a top conductive wire. PNG media_image2.png 587 619 media_image2.png Greyscale Regarding Claim 2 – Rizzolo modified by Chuang discloses all the limitations of claim 1. The combination of Rizzolo and Chuang further discloses a top surface of the conductive etch stop layer (120, Chuang [0017] and Fig. 2B) is coplanar with a top surface of the hardmask layer. Chuang Discloses an MTJ stack with surrounding layers, similar to Rizzolo. Rizzolo’s conductive etch stop layer is simply not etched back to be coplanar with the hardmask. Chuang teaches a conductive etch stop layer coplanar with a hardmask layer for the benefit of coupling the two electrically (Chuang [0033]) to reduce series resistance (Chuang [0021]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Rizzolo and Chuang to make the etch stop layer coplanar with the top surface of the hardmask layer to enable a reduction in series resistance. Regarding Claim 3 – Rizzolo modified by Chuang discloses all the limitations of claim 1. The combination of Rizzolo and Chuang further discloses an encapsulation layer (446, Rizzolo [0034]) formed around the MRAM stack and the hardmask structure; wherein the conductive etch stop layer is formed in a via (902, Rizzolo [0037]) that is formed into the encapsulation layer (446 recessed around 456A, and 464 deposited there as in annotated Rizzolo Fig. 9). Regarding Claim 4 – Rizzolo modified by Chuang discloses all the limitations of claim 3. The combination of Rizzolo and Chuang further discloses a liner layer (462, Rizzolo [0039]) between the encapsulation layer and the etch stop layer. Regarding Claim 6 – Rizzolo modified by Chuang discloses all the limitations of claim 3. The combination of Rizzolo and Chuang further discloses the encapsulation layer is a Si-based oxide or nitride (446, Rizzolo [0046]). Regarding Claim 7 – Rizzolo modified by Chuang discloses all the limitations of claim 1. The combination of Rizzolo and Chuang further discloses the hardmask structure comprises at least one of Nb, NbN, W, WN, Ta, TaN, Ti, TiN, Ru, Mo, Cr, V, Pd, Pt, Rh, Sc, Al and other high melting point metals or conductive metal nitrides (456, Rizzolo [0046]). Regarding Claim 8 – Rizzolo modified by Chuang discloses all the limitations of claim 3. The combination of Rizzolo and Chuang further discloses a width of a bottom surface of the second electrode is less than a combined width of the hardmask structure and the encapsulation layer (The width of 224 is less than the width of 118, even before adding the encapsulation layer, as shown in annotated Chuang Fig. 2B). Regarding Claim 9 – Rizzolo modified by Chuang discloses all the limitations of claim 1. The combination of Rizzolo and Chuang further discloses a metal liner layer (462, Rizzolo [0039]) formed between the hardmask structure and the second electrode. Regarding Claim 10 – Rizzolo modified by Chuang discloses all the limitations of claim 1. The combination of Rizzolo and Chuang further discloses a material composition of the hardmask structure is the same as a material composition of the etch stop layer (456 and 464 share at least W and Ru as common candidates, Rizzolo [0046]). Response to Arguments The applicant asserts that no portion of layer 224 of Chuang is formed on layer 120. The examiner respectfully submits that layer 224 is on 120 as seen by “Direction of View” indicators in annotated Fig. 2B. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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Prosecution Timeline

Show 4 earlier events
Jul 29, 2025
Non-Final Rejection mailed — §102, §103
Oct 29, 2025
Examiner Interview Summary
Oct 29, 2025
Applicant Interview (Telephonic)
Oct 29, 2025
Response Filed
Nov 26, 2025
Non-Final Rejection mailed — §102, §103
Feb 26, 2026
Response Filed
May 18, 2026
Final Rejection mailed — §102, §103
Jul 08, 2026
Interview Requested

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12666616
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 5m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 1 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
50%
Grant Probability
99%
With Interview (+100.0%)
3y 3m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 4 resolved cases by this examiner. Grant probability derived from career allowance rate.

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