DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 15 October 2025 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites without “performing digital bit shift operations”. This is inferentially included and it is unclear if the applicant is positively reciting or functionally reciting performing digital bit shift operations. If the digital bit shift operations are being functionally recited, it is suggested to use functional terms such as “adapted to be” or “configured for”. If the digital bit shift operations are being positively recited, it is suggested to first state performing the digital bit shift operations before it is used to not generate the output voltage as in the claim. Claims 3-20 inherit the same deficiency by reasons of dependence, and are similarly rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 8, 10-17 are rejected under 35 U.S.C. 103 as being unpatentable over R. Khaddam-Aljameh, P. -A. Francese, L. Benini and E. Eleftheriou, "An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 2, pp. 372-385, Feb. 2021. (hereinafter “Khaddam-Aljameh”)
in view of US 20210158854 A1 Sinangil (hereinafter “Sinangil”).
Regarding claim 1, Khaddam-Aljameh teaches a semiconductor integrated circuit comprising:
a plurality of storage devices (Fig. 2, SRAM) arranged in a form of a plurality of rows, each of the storage devices being configured to store a bit position value of a weight of multiple bits (Pg. 2, Col. 2, Para. 5,
w
n
,
m
; Fig. 2,
b
1
N
,
1
…
b
n
w
N
,
1
, Pg. 3, Col. 1, Para. 1);
a plurality of multiplication circuits (Fig. 2, (b)) arranged in a form of a plurality of rows (Fig. 2,
I
M
C
U
1,1
,
I
M
C
U
N
-
1,1
,
.
.
.
I
M
C
U
N
,
1
; Pg. 6, Col. 1, Para. 2) and configured to receive a plurality of input voltages (Fig. 2, (b)
i
p
N
found in
x
N
; Pg. 4, Col. 1, Para. 2,
i
s
i
g
n
n
found in
x
n
) in parallel with each other and to multiply (Pg. 3, Col. 2, Para. 1) the plurality of input voltages by the weight of multiple bits to generate a plurality of multiplication results (Pg. 4, Col. 1, Para. 2, multiplication results –
s
r
e
s
u
l
t
n
) in plurality with each other, the plurality of input voltages have different amplitudes (Pg. 4, Col. 1, Para. 3, Eqn. 8,
i
p
n
∙
2
-
p
; Pg. 6, Col. 1, Para. 1,
x
n
2
n
x
), each of the input voltages being associated with a corresponding bit position of the weight (Pg. 3, Col. 1, Para. 1, corresponding weight
b
k
n
and input bits
i
p
n
);
a plurality of capacitive devices (Fig. 2, (c)
C
o
u
t
,
N
and duplicates found directly above it; Fig. 2,
C
0
…
C
n
w
; Pg. 4, Col. 2, Para. 1-2) configured to accumulate charges corresponding to the plurality of multiplication results (Fig. 2 description, Pg. 4, Col. 1, Para. 1) in parallel with each other; and
an adder circuit (Fig. 2, (c)) configured to generate an output voltage (Fig. 2,
V
c
o
l
,
1
;
Pg. 6, Col. 1, Para. 2,
V
c
o
l
) by redistributing (abstract; Pg. 4, Col. 2, Para. 2; Pg. 6, Col. 1, Para. 2-3) collectively the charges accumulated (Fig. 2,
V
C
,
o
u
t
,
1
…
N
; Pg. 6, Col. 1, Para. 1-2,
V
C
,
o
u
t
,
f
i
n
a
l
,
n
) in the plurality of capacitive devices, without performing digital bit shift operations (Pg. 6, Col. 1, Sec. C, Para. 1, last operation performed in analog domain, shorting all capacitors, and thus not performing digital bit shift operations to generate the output voltage).
Although Khaddam-Aljameh describes parallel read operations (Fig. 11 description) and appears Khaddam-Aljameh may do operations in parallel, they do not explicitly describe receiving the plurality of input voltages in parallel with each other, generating multiplications results in parallel with each other, and accumulating charges in parallel with each other. Further, Khaddam-Aljameh while describing redistributing accumulated charges generally, they do not explicitly describe redistributing these charges collectively in the plurality of capacitive devices.
Sinangil teaches receiving the plurality of input voltages in parallel with each other (Figs. 2A and 3A, RWL[] and 156[], [0017], [0018], [0021], [0023-0026], [0036], [0042]), generating multiplication results in parallel with each other (Figs. 2A and 3A, RBL[] and 190[], [0019], [0022-0026], [0036], [0040-0042], [0063]), and accumulating charges in parallel with each other (Fig. 3C, 310, [0056]; Fig. 3A, Cn[3]…Cn[0] and Cm[3]…Cm[0], [0026]). Further, Sinangil teaches redistributing charges accumulated collectively (Fig. 3C, 330, [0057]; Fig. 3B,Cn[j] and Cm[j], [0028]).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Khaddam-Aljameh’s circuitry with Sinangil’s receiving, generating, and accumulating in parallel with each other and accumulating charges collectively feature because they are in the claimed invention’s same field of endeavor of MAC computations and devices ([0014]). It would have been obvious to one of ordinary skill in the art to receive, generate, and accumulate in parallel with each other and thus transmit the accumulated charges collectively as it allows the device to activate multiple RWL’s simultaneously without upsetting voltages stored (at Q or QB for instance) ([0034]) or upsetting the stored state of any memory cell ([0060]). Making this modification would be beneficial, as this allows Khaddam-Aljameh’s system to perform operations more effectively and accurately by avoiding unnecessary actions to reapply the voltages/stored state of memory cell, thereby achieving computational speedups ([0060]).
Regarding claim 3, in addition to the teachings addressed in the claim 2 analysis, the rejection of claim 2 is incorporated and Khaddam-Aljameh teaches wherein:
an amount of the redistributed charges includes an amount of a charge obtained by averaging an amount of the charges accumulated in the capacitive devices among the plurality of capacitive devices (Pg. 6, Col. 1, Para. 2-3, Eqn. 17).
Regarding claim 4, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Khaddam-Aljameh teaches wherein the adder circuit (see claim 1 mapping) is configured to:
add the charges accumulated in the plurality of capacitive devices to generate a voltage corresponding to an added charges as the output voltage (Pg. 4, Col. 2, Para. 2; Pg. 6, Col. 1, Para. 1,
V
p
r
e
+
V
C
M
; Pg. 6, Col. 1, Para. 2,
∑
n
=
1
N
V
C
,
o
u
t
,
f
i
n
a
l
,
n
).
Regarding claim 5, in addition to the teachings addressed in the claim 4 analysis, the rejection of claim 4 is incorporated and Khaddam-Aljameh teaches wherein:
an amount of the added charges includes an amount of a charge obtained by summing an amount of the charges accumulated in the capacitive devices among the plurality of capacitive devices (Pg. 4, Col. 2, Para. 2; Pg. 6, Col. 1, Para. 1-3).
Regarding claim 6, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Khaddam-Aljameh teaches wherein:
a pattern of the multiple bits included in the weight represents a positive integer (Pg. 3, Col. 1, Para. 1,
b
s
i
g
n
n
,
m
, Pg. 3, Col. 2, Para. 3), and each of the plurality of input voltages is associated with a corresponding bit of the multiple bits (Pg. 3, Col. 1, Para. 1) and has a positive amplitude different from an amplitude of an input voltage corresponding to an adjacent bit by a power of 2 (Pg. 3, Col. 2, Para. 3,
b
k
n
∙
2
k
-
n
w
-
1
for weight; Pg. 4, Col. 1, Para. 3, Eqn. 8,
i
p
n
∙
2
-
p
and Pg. 6, Col. 1, Para. 1,
x
n
2
n
x
for input).
Regarding claim 8, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Khaddam-Aljameh teaches wherein the plurality of capacitive devices (see claim 1 mapping):
have respective first ends (Fig. 2, nodes at
V
C
,
o
u
t
,
1
,
V
C
,
o
u
t
,
N
-
1
,
…
V
C
,
o
u
t
,
N
), each of the plurality of multiplication circuits (in addition to claim 1 mapping, encompasses switches and capacitors of Fig. 2 before blue highlight) has an input node (Fig. 2, nodes where two sets of vertical switches meet and before other vertical switches marked (
ϕ
0
,
ϕ
1
,
ϕ
(
k
-
1
)
m
o
d
3
,
ϕ
n
w
-
2
m
o
d
3
,
ϕ
n
w
-
1
m
o
d
3
)), one capacitive device of the plurality of capacitive devices (Fig. 2,
C
0
…
C
n
w
,
C
o
u
t
,
N
; Pg. 4, Col. 2, Para. 1-2), a first switching device (Fig. 2, unmarked branched switches), and a second switching device (Fig. 2, switches marked with (
ϕ
0
,
ϕ
1
,
ϕ
(
k
-
1
)
m
o
d
3
,
ϕ
n
w
-
2
m
o
d
3
,
ϕ
n
w
-
1
m
o
d
3
)), the first switching device turning ON or OFF depending on a first global signal (Fig. 2, Q or
Q
-
from SRAM), the second switching device being connected in series with the first switching device between the input node and the first end of the one capacitive device (Fig. 2, unmarked switches followed by node followed by marked switches (
ϕ
0
,
ϕ
1
,
ϕ
(
k
-
1
)
m
o
d
3
,
ϕ
n
w
-
2
m
o
d
3
,
ϕ
n
w
-
1
m
o
d
3
) followed by capacitors (
C
0
…
C
n
w
)) and being maintained ON or OFF depending on a bit value of the weight (Fig. 2,
ϕ
0
,
ϕ
1
,
ϕ
(
k
-
1
)
m
o
d
3
,
ϕ
n
w
-
2
m
o
d
3
,
ϕ
n
w
-
1
m
o
d
3
and
ϕ
0
,
ϕ
1
,
ϕ
k
m
o
d
3
,
ϕ
n
w
-
1
m
o
d
3
,
ϕ