DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 15 October 2025 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites without “performing digital bit shift operations”. This is inferentially included and it is unclear if the applicant is positively reciting or functionally reciting performing digital bit shift operations. If the digital bit shift operations are being functionally recited, it is suggested to use functional terms such as “adapted to be” or “configured for”. If the digital bit shift operations are being positively recited, it is suggested to first state performing the digital bit shift operations before it is used to not generate the output voltage as in the claim. Claims 3-20 inherit the same deficiency by reasons of dependence, and are similarly rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 8, 10-17 are rejected under 35 U.S.C. 103 as being unpatentable over R. Khaddam-Aljameh, P. -A. Francese, L. Benini and E. Eleftheriou, "An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 2, pp. 372-385, Feb. 2021. (hereinafter “Khaddam-Aljameh”)
in view of US 20210158854 A1 Sinangil (hereinafter “Sinangil”).
Regarding claim 1, Khaddam-Aljameh teaches a semiconductor integrated circuit comprising:
a plurality of storage devices (Fig. 2, SRAM) arranged in a form of a plurality of rows, each of the storage devices being configured to store a bit position value of a weight of multiple bits (Pg. 2, Col. 2, Para. 5,
w
n
,
m
; Fig. 2,
b
1
N
,
1
…
b
n
w
N
,
1
, Pg. 3, Col. 1, Para. 1);
a plurality of multiplication circuits (Fig. 2, (b)) arranged in a form of a plurality of rows (Fig. 2,
I
M
C
U
1,1
,
I
M
C
U
N
-
1,1
,
.
.
.
I
M
C
U
N
,
1
; Pg. 6, Col. 1, Para. 2) and configured to receive a plurality of input voltages (Fig. 2, (b)
i
p
N
found in
x
N
; Pg. 4, Col. 1, Para. 2,
i
s
i
g
n
n
found in
x
n
) in parallel with each other and to multiply (Pg. 3, Col. 2, Para. 1) the plurality of input voltages by the weight of multiple bits to generate a plurality of multiplication results (Pg. 4, Col. 1, Para. 2, multiplication results –
s
r
e
s
u
l
t
n
) in plurality with each other, the plurality of input voltages have different amplitudes (Pg. 4, Col. 1, Para. 3, Eqn. 8,
i
p
n
∙
2
-
p
; Pg. 6, Col. 1, Para. 1,
x
n
2
n
x
), each of the input voltages being associated with a corresponding bit position of the weight (Pg. 3, Col. 1, Para. 1, corresponding weight
b
k
n
and input bits
i
p
n
);
a plurality of capacitive devices (Fig. 2, (c)
C
o
u
t
,
N
and duplicates found directly above it; Fig. 2,
C
0
…
C
n
w
; Pg. 4, Col. 2, Para. 1-2) configured to accumulate charges corresponding to the plurality of multiplication results (Fig. 2 description, Pg. 4, Col. 1, Para. 1) in parallel with each other; and
an adder circuit (Fig. 2, (c)) configured to generate an output voltage (Fig. 2,
V
c
o
l
,
1
;
Pg. 6, Col. 1, Para. 2,
V
c
o
l
) by redistributing (abstract; Pg. 4, Col. 2, Para. 2; Pg. 6, Col. 1, Para. 2-3) collectively the charges accumulated (Fig. 2,
V
C
,
o
u
t
,
1
…
N
; Pg. 6, Col. 1, Para. 1-2,
V
C
,
o
u
t
,
f
i
n
a
l
,
n
) in the plurality of capacitive devices, without performing digital bit shift operations (Pg. 6, Col. 1, Sec. C, Para. 1, last operation performed in analog domain, shorting all capacitors, and thus not performing digital bit shift operations to generate the output voltage).
Although Khaddam-Aljameh describes parallel read operations (Fig. 11 description) and appears Khaddam-Aljameh may do operations in parallel, they do not explicitly describe receiving the plurality of input voltages in parallel with each other, generating multiplications results in parallel with each other, and accumulating charges in parallel with each other. Further, Khaddam-Aljameh while describing redistributing accumulated charges generally, they do not explicitly describe redistributing these charges collectively in the plurality of capacitive devices.
Sinangil teaches receiving the plurality of input voltages in parallel with each other (Figs. 2A and 3A, RWL[] and 156[], [0017], [0018], [0021], [0023-0026], [0036], [0042]), generating multiplication results in parallel with each other (Figs. 2A and 3A, RBL[] and 190[], [0019], [0022-0026], [0036], [0040-0042], [0063]), and accumulating charges in parallel with each other (Fig. 3C, 310, [0056]; Fig. 3A, Cn[3]…Cn[0] and Cm[3]…Cm[0], [0026]). Further, Sinangil teaches redistributing charges accumulated collectively (Fig. 3C, 330, [0057]; Fig. 3B,Cn[j] and Cm[j], [0028]).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Khaddam-Aljameh’s circuitry with Sinangil’s receiving, generating, and accumulating in parallel with each other and accumulating charges collectively feature because they are in the claimed invention’s same field of endeavor of MAC computations and devices ([0014]). It would have been obvious to one of ordinary skill in the art to receive, generate, and accumulate in parallel with each other and thus transmit the accumulated charges collectively as it allows the device to activate multiple RWL’s simultaneously without upsetting voltages stored (at Q or QB for instance) ([0034]) or upsetting the stored state of any memory cell ([0060]). Making this modification would be beneficial, as this allows Khaddam-Aljameh’s system to perform operations more effectively and accurately by avoiding unnecessary actions to reapply the voltages/stored state of memory cell, thereby achieving computational speedups ([0060]).
Regarding claim 3, in addition to the teachings addressed in the claim 2 analysis, the rejection of claim 2 is incorporated and Khaddam-Aljameh teaches wherein:
an amount of the redistributed charges includes an amount of a charge obtained by averaging an amount of the charges accumulated in the capacitive devices among the plurality of capacitive devices (Pg. 6, Col. 1, Para. 2-3, Eqn. 17).
Regarding claim 4, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Khaddam-Aljameh teaches wherein the adder circuit (see claim 1 mapping) is configured to:
add the charges accumulated in the plurality of capacitive devices to generate a voltage corresponding to an added charges as the output voltage (Pg. 4, Col. 2, Para. 2; Pg. 6, Col. 1, Para. 1,
V
p
r
e
+
V
C
M
; Pg. 6, Col. 1, Para. 2,
∑
n
=
1
N
V
C
,
o
u
t
,
f
i
n
a
l
,
n
).
Regarding claim 5, in addition to the teachings addressed in the claim 4 analysis, the rejection of claim 4 is incorporated and Khaddam-Aljameh teaches wherein:
an amount of the added charges includes an amount of a charge obtained by summing an amount of the charges accumulated in the capacitive devices among the plurality of capacitive devices (Pg. 4, Col. 2, Para. 2; Pg. 6, Col. 1, Para. 1-3).
Regarding claim 6, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Khaddam-Aljameh teaches wherein:
a pattern of the multiple bits included in the weight represents a positive integer (Pg. 3, Col. 1, Para. 1,
b
s
i
g
n
n
,
m
, Pg. 3, Col. 2, Para. 3), and each of the plurality of input voltages is associated with a corresponding bit of the multiple bits (Pg. 3, Col. 1, Para. 1) and has a positive amplitude different from an amplitude of an input voltage corresponding to an adjacent bit by a power of 2 (Pg. 3, Col. 2, Para. 3,
b
k
n
∙
2
k
-
n
w
-
1
for weight; Pg. 4, Col. 1, Para. 3, Eqn. 8,
i
p
n
∙
2
-
p
and Pg. 6, Col. 1, Para. 1,
x
n
2
n
x
for input).
Regarding claim 8, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Khaddam-Aljameh teaches wherein the plurality of capacitive devices (see claim 1 mapping):
have respective first ends (Fig. 2, nodes at
V
C
,
o
u
t
,
1
,
V
C
,
o
u
t
,
N
-
1
,
…
V
C
,
o
u
t
,
N
), each of the plurality of multiplication circuits (in addition to claim 1 mapping, encompasses switches and capacitors of Fig. 2 before blue highlight) has an input node (Fig. 2, nodes where two sets of vertical switches meet and before other vertical switches marked (
ϕ
0
,
ϕ
1
,
ϕ
(
k
-
1
)
m
o
d
3
,
ϕ
n
w
-
2
m
o
d
3
,
ϕ
n
w
-
1
m
o
d
3
)), one capacitive device of the plurality of capacitive devices (Fig. 2,
C
0
…
C
n
w
,
C
o
u
t
,
N
; Pg. 4, Col. 2, Para. 1-2), a first switching device (Fig. 2, unmarked branched switches), and a second switching device (Fig. 2, switches marked with (
ϕ
0
,
ϕ
1
,
ϕ
(
k
-
1
)
m
o
d
3
,
ϕ
n
w
-
2
m
o
d
3
,
ϕ
n
w
-
1
m
o
d
3
)), the first switching device turning ON or OFF depending on a first global signal (Fig. 2, Q or
Q
-
from SRAM), the second switching device being connected in series with the first switching device between the input node and the first end of the one capacitive device (Fig. 2, unmarked switches followed by node followed by marked switches (
ϕ
0
,
ϕ
1
,
ϕ
(
k
-
1
)
m
o
d
3
,
ϕ
n
w
-
2
m
o
d
3
,
ϕ
n
w
-
1
m
o
d
3
) followed by capacitors (
C
0
…
C
n
w
)) and being maintained ON or OFF depending on a bit value of the weight (Fig. 2,
ϕ
0
,
ϕ
1
,
ϕ
(
k
-
1
)
m
o
d
3
,
ϕ
n
w
-
2
m
o
d
3
,
ϕ
n
w
-
1
m
o
d
3
and
ϕ
0
,
ϕ
1
,
ϕ
k
m
o
d
3
,
ϕ
n
w
-
1
m
o
d
3
,
ϕ
M
S
B
,
a
d
d
,
ϕ
M
S
B
,
r
s
t
,
ϕ
o
u
t
,
a
d
d
; Pg. 3, Col. 2, Para. 2), and
the adder circuit (in addition to claim 1 mapping, encompasses switches and capacitors of Fig. 2 before (c)) includes an output node (Fig. 2,
V
c
o
l
,
1
node), a third switching device (Fig. 2, unmarked switches only with direct connections
V
C
M
), and a plurality of fourth switching devices (Fig. 2,
ϕ
a
c
c
switches along each row), the third switching device being provided between a common voltage having a reference potential (Fig. 2,
V
C
M
at ground) and the first end of the one capacitive device of the plurality of capacitive devices (Fig. 2,
C
0
…
C
n
w
,
C
o
u
t
,
N
; Pg. 4, Col. 2, Para. 1-2) and turning ON or OFF depending on a second global signal (Fig. 2,
Q
-
from SRAM), and each of the plurality of fourth switching devices being provided between the first end of each of the plurality of capacitive devices and the output node (Fig. 2,
ϕ
a
c
c
switches after output
V
c
o
l
,
1
and before
C
0
…
C
n
w
,
C
o
u
t
,
N
) and turning ON or OFF depending on a third global signal (Fig. 2,
ϕ
a
c
c
; Pg. 6, Col. 1, Para. 2).
Regarding claim 10, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Khaddam-Aljameh teaches wherein the plurality of capacitive devices (see claim 1 mapping):
are arranged in a form of a plurality of rows and a plurality of columns (Fig. 2,
C
0
…
C
n
w
,
C
o
u
t
,
N
in a row;
C
o
u
t
,
N
and duplicates in column), the plurality of multiplication circuits is arranged in a form of a plurality of rows and a plurality of columns (Fig. 2, duplicated and equivalent for
I
M
C
U
N
-
1,1
and
I
M
C
U
1,1
for column), and a plurality of the adder circuits are configured to generate a plurality of output voltages corresponding to the total value of charges accumulated in a capacitive device (Fig. 2,
V
C
,
o
u
t
,
1
,
V
C
,
o
u
t
,
N
-
1
,
…
,
V
C
,
o
u
t
,
N
) in each column (Pg. 6, Col. 1, Para. 2) among the plurality of capacitive devices (see claim 1 mapping).
Regarding claim 11, in addition to the teachings addressed in the claim 10 analysis, the rejection of claim 10 is incorporated and Khaddam-Aljameh teaches wherein the adder (see claim 1 mapping) is configured to:
redistribute charges accumulated in the capacitive devices in a first column among the capacitive devices in the first column (Fig. 2,
C
0
…
C
n
w
are in separate columns) and generate a voltage corresponding to the charges redistributed in the first column as the output voltage of the first column (Fig. 2,
V
C
0
,
V
C
1
,
…
V
C
,
n
w
; abstract; Pg. 4, Col. 2, Para. 1-2), and
the adder circuit is configured to redistribute charges accumulated in the capacitive devices in a second column among the capacitive devices in the second column (Fig. 2,
C
o
u
t
,
N
and duplicates in column) and generate a voltage corresponding to the charges redistributed in the second column as the output voltage of the second column (Fig. 2,
V
C
,
o
u
t
,
1
,
V
C
,
o
u
t
,
N
-
1
,
…
V
C
,
o
u
t
,
N
; abstract; Pg. 4, Col. 2, Para. 2; Pg. 6, Col. 1, Para. 2-3).
Regarding claim 12, in addition to the teachings addressed in the claim 10 analysis, the rejection of claim 10 is incorporated and Khaddam-Aljameh teaches wherein the adder (see claim 1 mapping) is configured to:
add the charges accumulated in the capacitive devices in the first column to generate a voltage corresponding to the charges added in the first column as the output voltage of the first column (Fig. 2,
V
C
0
,
V
C
1
,
…
V
C
,
n
w
; Pg. 4, Col. 2, Para. 1), and
the adder circuit is configured to add the charges accumulated in the capacitive devices in the second column to generate a voltage corresponding to the charges added in the second column as the output voltage of the second column (Fig. 2,
V
C
,
o
u
t
,
1
,
V
C
,
o
u
t
,
N
-
1
,
…
V
C
,
o
u
t
,
N
; Pg. 4, Col. 2, Para. 2).
Regarding claim 13, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Khaddam-Aljameh teaches an arithmetic logic operation system comprising:
an input circuit configured to convert data of multiple bits into a plurality of voltages (Fig. 2, pipelined D/A converter, Pg. 3, Col. 1, Para. 2-3, DAC); and the semiconductor integrated circuit of claim 1 (see claim 1 & 9 mapping) configured to receive the plurality of converted voltages as the plurality of input voltages (Fig. 2 description; Pg. 3, Col. 2, Para. 2).
Regarding claim 14, in addition to the teachings addressed in the claim 13 analysis, the rejection of claim 13 is incorporated and Khaddam-Aljameh teaches an arithmetic logic operation system wherein:
a pattern of the multiple bits included in the weight represents a positive integer, and each of the plurality of input voltages is associated with a corresponding bit of the multiple bits and has a positive amplitude different from an amplitude of an input voltage corresponding to an adjacent bit by a power of 2 (see claim 6 mapping).
Regarding claim 15, in addition to the teachings addressed in the claim 13 analysis, the rejection of claim 13 is incorporated and Khaddam-Aljameh teaches an arithmetic logic operation system wherein:
a pattern of the multiple bits included in the weight represents a positive or negative integer in two's complement representation, and each of the plurality of input voltages is associated with a corresponding bit of the multiple bits and has a positive or negative amplitude different from an amplitude of an input voltage corresponding to an adjacent bin by a power of 2 (see claim 7 mapping).
Regarding claim 16, in addition to the teachings addressed in the claim 13 analysis, the rejection of claim 13 is incorporated and Khaddam-Aljameh teaches an arithmetic logic operation system wherein:
the plurality of capacitive devices have respective first ends, each of the plurality of multiplication circuits has an input node, one capacitive device of the plurality of capacitive devices, a first switching device, and a second switching device, the first switching device turning ON or OFF depending on a first global signal, the second switching device being connected in series with the first switching device between the input node and the first end of the one capacitive device and being maintained ON or OFF depending on a hit value of the weight, and the adder circuit includes an output node, a third switching device, and a plurality of fourth switching devices, the third switching device being provided between a common voltage having a reference potential and the first end of the one capacitive device of the plurality of capacitive devices and turning ON or OFF depending on a second global signal, and each of the plurality of fourth switching devices being provided between the first end of each of the plurality of capacitive devices and the output node and turning ON or OFF depending on a third global signal (see claim 8 mapping).
Regarding claim 17, in addition to the teachings addressed in the claim 13 analysis, the rejection of claim 13 is incorporated and Khaddam-Aljameh teaches an arithmetic logic operation system wherein:
the plurality of capacitive devices are arranged in a form of a plurality of rows and a plurality of columns, the plurality of multiplication circuits is arranged in a form of a plurality of rows and a plurality of columns, and a plurality of the adder circuits are configured to generate a plurality of output voltages corresponding to the total value of charges accumulated in a capacitive device in each column among the plurality of capacitive devices (see claim 10 mapping).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Khaddam-Aljameh in view of Sinangil in further view of Patterson, David A., and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface (5th Edition). Morgan Kaufmann, 2013. (hereinafter “Patterson”).
Regarding claim 7, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Khaddam-Aljameh teaches wherein a pattern of the multiple bits included in the weight represents (see claim 6 mapping):
a positive or negative integer (Pg. 3, Col. 1, Para. 1,
b
s
i
g
n
n
,
m
, Pg. 3, Col. 2, Para. 3) and each of the plurality of input voltages is associated with a corresponding bit of the multiple bits and has a positive or negative (Pg. 3, Col. 1, Para. 1,
b
s
i
g
n
n
and
i
s
i
g
n
n
) amplitude different from an amplitude of an input voltage corresponding to an adjacent bit by a power of 2 (Pg. 3, Col. 2, Para. 3,
b
k
n
∙
2
k
-
n
w
-
1
for weight; Pg. 4, Col. 1, Para. 3, Eqn. 8,
i
p
n
∙
2
-
p
and Pg. 6, Col. 1, Para. 1,
x
n
2
n
x
for input).
While Khaddam-Aljameh generally teaches the weight can be positive or negative, they and the combination in view of Sinangil are silent with explicitly describing the format as being in two’s complement.
Patterson teaches two's complement representation (Pg. 75, Para. 5-7).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Khaddam-Aljameh in view of Sinangil’s modified circuitry with Patterson’s representation because they are in the claimed invention’s same field of endeavor of calculating using positive and negative numbers (Pg. 75, Para. 1-2). It would have been obvious to one of ordinary skill in the art to implement the representation as it allows the device to work with numbers in a representation in which all negative number have a 1 in the most significant bit, thereby only needing to test this bit to determine if the value is negative or positive (Pg. 76, Para. 1). Making this modification would be beneficial, as this allows Khaddam-Aljameh in view of Sinangil’s system to perform operations without using much computation time, power, or energy to determine the sign of the number, thereby accelerating computations and reducing unnecessary time, power, or energy usage.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Khaddam-Aljameh in view of Sinangil in further view of US 9069995 B1 Cronie (hereinafter “Cronie”).
Regarding claim 9, in addition to the teachings addressed in the claim 8 analysis, the rejection of claim 8 is incorporated and Khaddam-Aljameh teaches wherein:
the semiconductor integrated circuit (Pg. 2, Col. 1, Para. 3, 5; Pg. 13, Table III, “This Work” column; Pg. 12, Table I; Pg. 13, Col. 1, Para. 1; Pg. 8, Col. 2, Para. 1, transistor; Pg. 2, Col. 2, Para. 3).
Khaddam-Aljameh in view of Sinangil in view of Cronie teach the sequence of combinations of which the switching occurs.
Cronie teaches a sequence of combinations of which the switching occurs (Fig. 3; Col. 5, lines 25-32).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Khaddam-Aljameh in view of Sinangil’s modified circuity with Cronie’s switching combinations because they are in the claimed invention’s same field of endeavor of analog multiply accumulate operations (abstract). In practicality, there are only a finite number of combinations possible considering the finite number of switches in the circuit over a period of time, so it would have been obvious to try different combinations (Col. 5, lines 25-35). Cronie teaches that when the waveform 310 is high, assigned switches 214 and 212 are closed, or “ON”, and when the waveform is low, the switches are open, or “OFF” (Fig. 3; Col. 5, lines 26-28). Cronie further teaches that when another waveform 320 is high, assigned switches 210 are closed, or “ON”, and when the waveform is low, the switches are open, or “OFF” (Fig. 3; Col. 5, lines 28-30). Cronie concludes with teaching that waveforms 320 and 310 are non-overlapping (Col. 5, lines 30-32), and that these waveforms are alternating high and low, so when one is high with those corresponding switches as “ON”, the other is low with those corresponding switches as “OFF”. As it relates to Khaddam-Aljameh in view of Sinangil’s modified circuitry, this means it would have been obvious to try assigning different waveforms to switches, and thus having the first switching device (Fig. 2, unmarked branched switches) follow the sequence of being “OFF”, “ON”, “OFF”; the third switching device (Fig. 2, unmarked switches only with direct connections
V
C
M
) follow the sequence of being “ON”, “OFF”, “OFF”; and the fourth switching device (Fig. 2,
ϕ
a
c
c
switches along each row) follow the sequence of being “ON”, “OFF”, “ON”. Making this modification would have been obvious, as a person skilled in the art would recognize the finite combinations of having switches “ON”/”OFF” over a time period to perform the functions of the circuit.
Regarding claim 9, the preamble is given patentable weight. Claim 9 contains the
limitation “the semiconductor integrated circuit ” in the body, which is referring to the circuit as recited in the preamble. A skilled person in the art reading the claims would consider the claim in view of the body and preamble, and identify them limited to the semiconductor integrated circuit. The body of the claim depends on the preamble for completeness, and gives life, meaning, and vitality to this claim. Therefore, the preamble of claim 9 should be afforded patentable weight.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Khaddam-Aljameh in view of Sinangil in further view of Wang, F-J., Gabor C. Temes, and Simon Law. "A quasi-passive CMOS pipeline D/A converter." IEEE journal of solid-state circuits 24.6 (1989): 1752-1755. (hereinafter “Wang”).
Regarding claim 18, in addition to the teachings addressed in the claim 13 analysis, the rejection of claim 13 is incorporated and Khaddam-Aljameh teaches an arithmetic logic operation system wherein:
the input circuit has a plurality of unit configurations corresponding to the multiple bits (Pg. 3, Col. 2, Para. 2, each SRAM cell).
Khaddam-Aljameh in view of Sinangil in view of Wang disclose a driver.
Wang teaches a driver (Wang, Pg. 3, Col. 2, Para. 3, driver).
Khaddam-Aljameh teaches that the DAC design from Wang (Pg. 3, Col. 2, Para. 1) is used to build their circuitry, therefore it would have been obvious to one of ordinary skill in the art to recognize that Khaddam-Aljameh in view of Sinangil’s modified circuitry was ready for this modification as doing so would be a simple substitution. Wang is in the claimed invention’s same field of endeavor of switched-capacitor circuitry design (Abstract). It would have been obvious to implement this simple substitution of the DAC design as the results are predictable, DAC’s in both references are taught to convert values from digital to analog (Abstract; Pg. 1, Col. 2, Para. 4).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Khaddam-Aljameh in view of in view of Sinangil in view of Wang in further view of US 20180182278 A1 Kim et al. (hereinafter “Kim”).
Regarding claim 19, in addition to the teachings addressed in the claim 18 analysis, the rejection of claim 18 is incorporated and Khaddam-Aljameh teaches an arithmetic logic operation system wherein each of the plurality of unit configurations (see claim 18 mapping) and a D/A converter (Fig. 11, (c), CDAC; Pg. 12, Col. 1, Para. 1; Fig. 2, pipelined D/A converter, Pg. 3, Col. 1, Para. 2-3, DAC).
Khaddam-Aljameh in view of in view of Sinangil in view of Wang in view of Kim disclose— with Kim specifically teaching an D/A converter a fifth switching device having a first end connected to the D/A converter (Fig. 2, SW2; [0057]) and a second end connected (Fig. 2, 15; [0068]) to the driver; and a sixth switching device (Fig. 2, SW1; [0057]) having a first end connected to an output node (Fig. 2, 15; [0068]) of the driver of another unit configuration and a second end connected (Fig. 2, Vpre; [0068]) to an input node of the driver thereof.
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Khaddam-Aljameh in view of Sinangil in view of Wang’s circuitry with Kim’s components because they are in the claimed invention’s same field of endeavor of analog computer architecture devices using voltages and currents ([0034-0035]). It would have been obvious to one of ordinary skill in the art to implement the components as described by Kim as they are known components in the art (See Neil Weste and David Harris. 2010. CMOS VLSI Design: A Circuits and Systems Perspective (4th. ed.). Addison-Wesley Publishing Company, USA. (hereinafter “Weste”), Pg. 627-628, 14.3.1 and Pg. 687, Para. 1-2 for A/D converter; Pg. 628-629, 14.3.2 for switches).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Khaddam-Aljameh in view of Sinangil in view of Wang in view of Kim in view of Cronie.
Regarding claim 20, in addition to the teachings addressed in the claim 19 analysis, the rejection of claim 19 is incorporated and Khaddam-Aljameh teaches an arithmetic logic operation system wherein the input circuit (see claim 18 mapping).
Khaddam-Aljameh in view of Sinangil in view of Wang in view of Kim in view of Cronie disclose the sequence of combinations of which the switching occurs.
Cronie teaches a sequence of combinations of which the switching occurs (Fig. 3; Col. 5, lines 25-32).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Khaddam-Aljameh in view of Sinangil in view of Wang in view of Kim’s circuity with Cronie’s switching combinations because they are in the claimed invention’s same field of endeavor of analog multiply accumulate operations (abstract). In practicality, there are only a finite number of combinations possible considering the finite number of switches in the circuit based on the unit configuration as taught by Khaddam-Aljameh, so it would have been obvious to try different combinations (Col. 5, lines 25-35). Cronie teaches that when the waveform 310 is high, assigned switches 214 and 212 are closed, or “ON”, and when the waveform is low, the switches are open, or “OFF” (Fig. 3; Col. 5, lines 26-28). Cronie further teaches that when another waveform 320 is high, assigned switches 210 are closed, or “ON”, and when the waveform is low, the switches are open, or “OFF” (Fig. 3; Col. 5, lines 28-30). Cronie concludes with teaching that waveforms 320 and 310 are non-overlapping (Col. 5, lines 30-32), and that these waveforms are alternating high and low, so when one is high with those corresponding switches as “ON”, the other is low with those corresponding switches as “OFF”. As it relates to Kim’s circuitry, this means it would have been obvious to try assigning different waveforms to switches, having the fifth switching device (Fig. 2, SW2; [0057]) follow the sequence of being “ON” for a first unit configuration and “OFF” for a second unit configuration; the sixth switching device (Fig. 2, SW1; [0057]) follow the sequence of being “OFF” for a first unit configuration and “OFF” for a second unit configuration. These switches simply alternate being “ON” and “OFF”, as taught by the example in Fig. 3. Making this modification would have been obvious, as a person skilled in the art would recognize the finite combinations of having switches “ON”/”OFF” to perform the functions of the circuit.
Response to Arguments
35 USC 103. Applicant’s arguments, see Remarks, Pg. 12, Para. 1, filed 15 October 2025, with respect to the rejection(s) of claim(s) 1-20 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Sinangil, as necessitated by the amendment.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARKUS A VILLANUEVA whose telephone number is (703)756-1603. The examiner can normally be reached M - F 8:30 am - 5:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
Prosecution Insights