DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-9 and 11-25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention.
Applicant has amended claims 1, 11 and 24 to include the feature “width of the trench at a surface of the backside is substantially constant as the trench traverses the semiconductor substrate.” Applicant points to Figure 7 which includes a meandering trench 730 with a “visually uniform surface width.” Applicant Figure 7 is shown below does not have a constant width in the trench 730 and applicant is not clear if they are referring to the cross-sectional view or top view, but the cross-sectional view clearly shows the width is not constant on the trench.
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Claims 2-9, 12-23, and 25 inherit the deficiency and stand rejected as well.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9, and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Jun et al. (US 2015/0194363 A1) in view of Jha et al. (US 2021/0183741 A1).
Regarding claim 1, Jun et al. discloses (Fig. 1-12) a semiconductor die, comprising:
a plurality of transistors arranged at a front side of a semiconductor substrate (Jun discloses an active region 120 that may function as a transistor but does not clearly recite transistors); and
a trench (130) extending from a backside of the semiconductor substrate (120) into the semiconductor substrate,
wherein a length of the trench (130) is equal or larger than a lateral dimension of the semiconductor substrate (¶¶0062-0063); and
wherein a width of the trench at a surface of the backside is substantially constant as the trench traverses the semiconductor substrate (see Figure 3 below where the width of the channels 190 in direction D2 is shown to be substantially constant).
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As stated above Jun does not explicitly disclose that the semiconductor device layer (120) includes a plurality of transistors.
In the same field of endeavor, Jha discloses (Fig. 1) a semiconductor die (105) with a plurality of semiconductor devices such as transistors arranged on one side (106) with a fluid cooled manifold (130) on the opposite side (Jha, Fig. 1, ¶¶16-20).
It would have been obvious to a person of ordinary skill in the art before the effective filing date to modify Jun’s semiconductor substrate having a backside trench cooling structure to include the transistor-device arrangement taught by Jha, because both references are directed to semiconductor packages and thermal management of integrated circuit devices. Jha teaches a die having a device side with contacts to transistor devices and circuits, and further teaches stacked-die/package integration in which heat-generating semiconductor devices are arranged within a package structure. Incorporating Jha’s transistor-containing die into Jun’s substrate-based cooling architecture would have been a predictable substitution of one known semiconductor device configuration for another to improve package integration while maintaining thermal management benefits. Such a modification would have been motivated by the recognized need to manage heat from active transistor circuitry in embedded or stacked semiconductor packages, and would merely combine known elements according to their established functions without changing the basic principle of Jun’s cooling trench structure.
Regarding claim 2, Jun in view of Jha teaches the semiconductor die according to claim 1.
Jun in view of Jha does not explicitly teach the width of the trench is at least 10µm.
It would have been obvious to a person of ordinary skill in the art at the time of the invention to modify Jun’s backside trench so that the trench width at the backside surface is at least 10 µm. The claimed width is a matter of routine optimization of a known thermal-management feature, because trench width is a result-effective variable affecting fluid flow, manufacturability, and heat-transfer performance. A person of ordinary skill would have recognized that selecting a trench width of at least 10 µm would have been a predictable design choice to provide sufficient passage for cooling medium and effective thermal coupling, while preserving the basic operating principle of Jun’s trench cooling structure.
Regarding claim 3, Jun in view of Jha discloses the semiconductor die according to claim 1, wherein a depth of the trench (130) is at least 10 µm (Jun ¶0048).
Regarding claim 4, Jun in view of Jha discloses the semiconductor die according to claim 1, wherein the trench (130, Jun ¶0062-0063) extends in a meandering pattern (Jun Fig. 1) along the backside of the semiconductor substrate (Jun Fig. 2).
Regarding claim 5, Jun in view of Jha discloses the semiconductor die according to claim 1, wherein the trench (130, Jun ¶0062-0063) extends from a first edge of the semiconductor substrate to an opposing second edge of the semiconductor substrate (Jun Fig. 1).
Regarding claim 6, Jun in view of Jha discloses the semiconductor die according to claim 5, comprising a plurality of trenches (Jun Fig. 2 and 11, ¶0047, where a plurality of trench cavities 130 form the microchannel array 190, Jun Fig. 12).
Regarding claim 7, Jun in view of Jha discloses the semiconductor die according to claim 1, further comprising a supply recess (160 inlet channel), wherein a width of the supply recess is larger than a width of the trench (see Figure 2 of Jun below).
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Regarding claim 9, Jun in view of Jha discloses the semiconductor die of claim 1, including a semiconductor substrate having one or more trenches extending from a backside of the substrate into the substrate for thermal management. Jun further teaches a trench-based cooling structure formed across the backside of the substrate, and the use of one or more trenches to remove heat from the semiconductor die.
However, Jun does not expressly disclose that the trench or plurality of trenches covers at least 5% of the backside of the semiconductor substrate.
It would have been obvious to a person of ordinary skill in the art at the time of the invention to configure the trench or plurality of trenches of Jun so as to cover at least 5% of the backside surface, because the extent and distribution of backside trenching is a result-effective design parameter affecting coolant access, heat transfer area, and thermal performance. Selecting a backside trench coverage of at least 5% would have involved routine optimization of the cooling structure to achieve predictable improvements in heat dissipation, especially in view of the semiconductor device and thermal-management context taught by Jha.
Regarding claim 24, Jun discloses a method for forming a semiconductor die, comprising:
forming a plurality of transistors arranged at a front side of a semiconductor substrate (Jun discloses an active region on the substrate functioning as a transistor, diode, CPU, ASIC, etc. See Jun, Abstract; ¶¶ 0008, 0040–0042, 0059. However, Jun does not expressly describe forming a plurality of transistors); and
forming a trench extending from a backside of the semiconductor substrate into the semiconductor substrate (Jun expressly teaches patterning the substrate by etching to form trenches in the substrate. See Jun ¶¶ 0023–0026, 0062–0064; the trenches are formed from the top side in the described process, but they are subsequently converted into buried open cavities / cooling channels within the substrate),
wherein a length of the trench is equal or larger than a lateral dimension of the semiconductor substrate (Jun describes microchannels / cavities extending through substantial portions of the substrate, and the cooling structure spans the substrate region. See Jun ¶¶ 0043–0051, 0062–0064.); and
wherein a width of the trench at a surface of the backside is substantially constant as the trench traverses the semiconductor substrate (Jun teaches trenches with defined dimensions formed by anisotropic etching, followed by isotropic etching to form open cavities. See Jun ¶¶ 0024–0026, 0062–0064; see Figure 3 above where the width of the channels 190 in direction D2 is shown to be substantially constant).
As stated above Jun does not explicitly disclose that the semiconductor device layer (120) includes a plurality of transistors.
In the same field of endeavor, Jha discloses (Fig. 1) a semiconductor die (105) with a plurality of semiconductor devices such as transistors arranged on one side (106) with a fluid cooled manifold (130) on the opposite side (Jha, Fig. 1, ¶¶16-20).
It would have been obvious to a person of ordinary skill in the art before the effective filing date to modify Jun’s semiconductor substrate having a backside trench cooling structure to include the transistor-device arrangement taught by Jha, because both references are directed to semiconductor packages and thermal management of integrated circuit devices. Jha teaches a die having a device side with contacts to transistor devices and circuits, and further teaches stacked-die/package integration in which heat-generating semiconductor devices are arranged within a package structure. Incorporating Jha’s transistor-containing die into Jun’s substrate-based cooling architecture would have been a predictable substitution of one known semiconductor device configuration for another to improve package integration while maintaining thermal management benefits. Such a modification would have been motivated by the recognized need to manage heat from active transistor circuitry in embedded or stacked semiconductor packages, and would merely combine known elements according to their established functions without changing the basic principle of Jun’s cooling trench structure.
Regarding claim 25, Jun in view of Jsu teach the method according to claim 24, wherein the trench is formed by an etching process (Jun expressly teaches etching to form the trenches, including anisotropic dry etching, RIE, deep RIE, plasma etching, and gas phase etching. See Jun ¶¶ 0023–0027, 0062–0064).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Jun et al. in view of Jha et al. as applied to claim 1 above, further in view of Neal et al. (US 2020/0227341 A1).
Regarding claim 7, Jun in view of Jha discloses the semiconductor die according to claim 1.
In the same field of endeavor, Neal discloses further comprising a supply recess (105a/105b, Neal ¶0040, ¶0043), wherein a width (Neal, ¶0025, ¶0051) of the supply recess is larger than a width (Neal, ¶0051) of the trench (201, Neal, ¶0051).
It would have been obvious to one of ordinary skill in the art at the time of filing to use a supply recess with a larger width than the trench, allowing “coolant may flow with low pressure drop down the fluid distribution channels so that the supply of coolant to the intersecting microchannels below is constant,” (Neal ¶0030).
Regarding claim 8, Jun in view of Jha discloses the semiconductor die according to claim 7.
Jun does not disclose wherein a depth of the supply recess is equal to a depth of the trench.
In the same field of endeavor, Neal discloses wherein a depth of the supply recess (105a/105b, Neal ¶40, 43) is equal to a depth of the trench (201, Neal, ¶51) (Neal, Fig. 3, where the supply recesses reach the same depth at the base of 108 on 202).
It would have been obvious to one of ordinary skill in the art at the time of the invention to configure the supply recess of Jun in view of Jha to have the same depth as the trench, as taught by Neal, because matching the recess depth to the trench depth would have provided a continuous coolant flow path and improved thermal performance while using known, predictable cooling geometry.
Claim 10 is rejected under 35 U.S.C. § 103 as being unpatentable over Hsu et al. (US 2021/0074608 A1) in view of Jha et al. and Neal et al.
Hsu et al. discloses a semiconductor package having a lid mounted on a die and on a perimeter of a substrate, wherein the lid includes a cover plate and four walls formed integral with the cover plate, and further discloses a liquid-cooling channel situated between the cover plate and a rear surface of the die for circulating coolant relative to the semiconductor package (Hsu ¶¶ 0009, 0047-0053, Figs. 1-5, 11-12). Hsu further teaches that the lid includes liquid inlet and outlet openings communicating with the liquid-cooling channel, thereby teaching a heat spreading structure attachable to a package structure and including an opening for conducting a cooling fluid.
Jha teaches integrated circuit packages having embedded thermal-management structures and fluid conduits within the package substrate for removing heat from semiconductor devices, thereby confirming that it was known in the art to integrate fluid-cooling paths into semiconductor package-level thermal structures (Jha ¶¶ 0035-0046, 0038-0045, 0047-0048, claims 1, 7-8, 17-24). Neal teaches semiconductor thermal-management structures having fluid distribution channels, manifolds, and heat-exchange surfaces used to improve coolant delivery and heat removal in semiconductor cooling assemblies (Neal ¶¶ 0024-0032, 0039-0047, 0050-0059, claims 1, 7-10, 17-20). Together, these references show that it would have been within the level of ordinary skill in the art to provide a package-mounted heat spreading structure with a coolant opening for conducting fluid through the structure.
Although Hsu does not expressly disclose that the heat spreading structure is hermetically attached to the package structure by a sealing structure comprising solder, it would have been obvious to one of ordinary skill in the art at the time of the invention to employ a solder-based sealing arrangement to secure the heat spreading structure to the package structure, because solder attachment was a well-known packaging technique for forming secure, fluid-resistant, and mechanically stable joints in semiconductor assemblies. Such a modification would have predictably improved sealing reliability of the liquid-cooling lid assembly while maintaining package integrity, and would merely have involved applying a known attachment/sealing technique to the liquid-cooled lid structure taught by Hsu.
Claims 11-14 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jun et al. in view of Arana et al. (US 2009/0057881 A1) and Jha et al.
Jun. teaches a semiconductor device having a substrate, an active region on the substrate, and a plurality of trenches/open cavities formed in the substrate by etching, with a microchannel array and heat sink structures arranged to cool the device. (See Jun, Abstract; ¶¶ 0008–0010, 0023–0027, 0040–0051, 0058–0064, 0062–0064, claims 1–19).
Arana teaches a stacked-die microelectronic package having a substrate, a first die over the substrate, and a second die over the first die, thereby teaching the stacked package context recited in claim 11. (See Arana, Abstract; ¶¶ 0010–0018, 0023–0027).
Jha further teaches semiconductor packages with embedded integrated circuit devices and integrated heat-transfer fluid conduits within the substrate, confirming the general desirability of integrating cooling structures into semiconductor package architecture. (See Jha, Abstract; ¶¶ 0035–0048, 0051–0054, claims 1–24).
It would have been obvious to modify the stacked-die semiconductor package of Arana and Jha to include Jun’s trench-based cooling structure in order to improve heat removal from the stacked dies, particularly because Jun teaches that cooling structures may be buried in the substrate and arranged to facilitate fluid flow and heat dissipation. The claimed trench location and general trench geometry would have been an obvious design variation in view of Jun’s trench and cavity teachings.
Regarding claim 12, Jun in view of Arana and Jha discloses the semiconductor package according to claim 11.
Arana expressly teaches a first die over a substrate and a second die over the first die in a chip stack, thereby teaching stacked die attachment in a semiconductor package. (See Arana, Abstract; ¶¶ 0010–0014, 0019–0022).
Jha teaches integrated circuit structures in which a device is embedded in a substrate and electrically attached during package formation, further evidencing standard package/die attachment arrangements. (See Jha, Abstract; ¶¶ 0035–0040, 0047–0051, claim 1).
It would have been obvious to arrange the dies in the backside/front-side attachment relationship recited by claim 12 as an ordinary stacked-die packaging modification.
Regarding claim 13, Jun in view of Arana and Jha discloses the semiconductor package according to claim 11. Jun teaches forming trenches in a semiconductor substrate by etching to define buried cooling cavities. (See Jun, ¶¶ 0023–0026, 0040–0051, 0062–0064, claims 1, 15–18). Jun further teaches that these cavities/trenches may extend across substantial portions of the substrate and may be formed using anisotropic and isotropic etching processes, thereby satisfying the claimed trench location and elongation relative to substrate dimension. (See Jun, ¶¶ 0024–0027, 0062–0064, claims 16–19).
Regarding claim 14, Jun in view of Arana and Jha teach the semiconductor package according to claim 11. Jun teaches trench/cavity formation in semiconductor substrates for cooling. See (Jun, ¶¶ 0023–0027, 0040–0051, 0062–0064, claims 1, 15–19). Arana and Jha teach semiconductor dies in stacked package configurations. (See Arana, Abstract; ¶¶ 0010–0014; Jha, Abstract; ¶¶ 0035–0040).
It would have been obvious to apply Jun’s backside trench cooling structure to either die in a stacked semiconductor package as a predictable thermal-management variation.
Regarding claim 19, Jun in view of Arana and Jha teaches the semiconductor package according to claim 1.
Jun teaches a semiconductor device having a substrate with buried trench/open-cavity cooling structures formed by etching. (See Jun et al., Abstract; ¶¶ 0023–0027, 0040–0051, 0058–0064, claims 1, 15–19). Arana teaches a stacked-die microelectronic package including a substrate and a first die over the substrate, with a second die over the first die, thereby teaching the package-substrate context and stacked-die arrangement. (See Arana et al., Abstract; ¶¶ 0010–0018, 0020–0022). Jha et al. further teaches an integrated circuit structure having a substrate with embedded integrated circuit devices and heat-transfer fluid conduit structures within the substrate. (See Jha et al., Abstract; ¶¶ 0035–0040, 0047–0051, claims 1–8, 17–24).
In view of these teachings, it would have been obvious to provide the claimed package substrate and to attach the first semiconductor die with its front side to the package substrate as a routine and predictable stacked-package implementation in the semiconductor packaging art.
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jun et al. in view of Arana et al. and Jha et al. as applied to claim 11 above, further in view of Neal et al.
Regarding claim 15, Jun in view of Arana and Jha teach the semiconductor package according to claim 11.
Arana teaches fluidic vias and fluidic channels in a stacked-die package, including a fluidic microchannel system with inlet and outlet openings connected by a fluidic passage, and further teaches that the fluidic passage may extend through the substrate, underfill, and die layers. (See Arana, Abstract; ¶¶ 0010–0018, 0020–0022, 0024–0027, claims 1–15).
Jha similarly teaches a heat transfer fluid conduit within a substrate and fluid channels for package thermal management. (See Jha, Abstract; ¶¶ 0035–0040, 0047–0048, claims 1–8, 15–24).
Neal teaches fluid distribution channels fluidically coupled to microchannels in a thermal module, including manifold structures and stacked fluid delivery channels. (See Neal, Abstract; ¶¶ 0024–0032, 0040–0059, claims 1, 7–10, 17–20).
It would have been obvious to provide through-package holes or fluidic openings facing a trench or recess to improve fluid delivery and heat rejection in a stacked-die cooling arrangement. Although the exact facing relationship is not expressly shown in the references, the claimed arrangement would have been an obvious design expedient in view of the fluidic passage and fluid-distribution teachings.
Regarding claim 16, Jun in view of Arana and Jha teach the semiconductor package according to claim 11.
Jun teaches trench formation in a semiconductor substrate for cooling. (See Jun, ¶¶ 0023–0027, 0040–0051, 0062–0064, claims 1, 15–19).
Neal teaches fluid distribution channels stacked over microchannels and fluidically coupled thereto, with walls/baffles extending into the microchannels to guide coolant flow. (See Neal, Abstract; ¶¶ 0024–0032, 0040–0059, claims 1, 7–10, 17–20).
Jha further teaches package-level fluid conduits within a substrate and molded/dielectric package structures. (See Jha, Abstract; ¶¶ 0035–0040, 0047–0048, claims 1–8, 13–24).
It would have been obvious to locate a supply channel beside a die and over another die, with an opening facing a trench or recess, as part of a known package thermal-fluid routing architecture.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Jun et al. in view of Arana et al., Jha et al. and Neal et al. as applied to claim 16 above, further in view of Hsu et al.
Regarding claim 17, Jun in view of Arana and Jha and further in view of Neal teach the semiconductor package according to claim 16.
The modified device teaches a substrate formed from a plurality of dielectric layers and, in other embodiments, molded layers, with metallization and integrated thermal structures. (See Jha, Abstract; ¶¶ 0035–0040, 0047–0051, claims 1–8, 13–24).
Hsu teaches a substrate that may include a molded layer and a heat transfer fluid conduit formed in the substrate, including embodiments where the fluid conduit extends through the molded layer. (See Hsu, Abstract; ¶¶ 0035–0046, claims 1, 5–8, 13–16, 21–22).
It would have been obvious to form the supply channel in mold material or dielectric material to integrate cooling passages into the package structure.
Claim 18 are rejected under 35 U.S.C. 103 as being unpatentable over Jun et al. in view of Arana et al. and Jha et al. as applied to claim 11 above, further in view of Elsherbini et al. (US 10,943,851).
Regarding claim 18, Jun in view of Arana and Jha and further in view of Neal teach the semiconductor package according to claim 16.
Jun teaches a semiconductor device having trench/open-cavity cooling structures formed in a substrate, Arana teaches a stacked-die semiconductor package including a first die over a substrate and a second die over the first die, and Jha teaches integrated circuit package structures with embedded thermal-management features. (See Jun et al., Abstract; ¶¶ 0023–0027, 0040–0051, 0058–0064; Arana et al., Abstract; ¶¶ 0010–0018, 0020–0022; Jha et al., Abstract; ¶¶ 0035–0040, 0047–0051).
Elsherbini further teaches that integrated circuit devices may be electrically attached using “a hybrid bonding technique”, in which a dielectric material layer forms a chemical bond with a dielectric material on an opposing device surface at room temperature, and subsequent heating causes the electrical interconnects and bond pads to fuse to form a permanent bond. (See Elsherbini, ¶ [0046]).
It would have been obvious to one of ordinary skill in the art to employ hybrid bonding as taught by Elsherbini in the stacked-die package of claim 11 to attach the first semiconductor die to the second semiconductor die, because hybrid bonding was a known technique for providing a compact, low-resistance, high-density electrical attachment and would have been a predictable variation of the stacked-die integration taught by Jun in view of Arana and Jha.
Claims 20-23 are rejected under 35 U.S.C. 103 as being unpatentable over Jun et al. in view of Arana et al. and Jha et al. as applied to claim 11 above, further in view of Hsu et al.
Regarding claim 20, Jun in view of Arana and Jha teaches the semiconductor package according to claim 11.
Hsu further teaches an integrated circuit assembly having a heat spreading structure or lid attached to a package structure, with fluid inlet and outlet ports for conducting cooling fluid, and teaches the use of a thermal interface material between the die and the heat spreading structure.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the stacked semiconductor package to further include the heat spreading structure and fluid-cooling arrangement of Hsu in order to improve thermal management of the package, as well as to use the thermal interface and sealing features taught by Hsu and Arana to facilitate heat transfer and fluid containment in the package assembly.
Regarding claim 21, Jun in view of Arana, Jha and Hsu teaches the semiconductor package according to claim 20.
Jun teaches a semiconductor device having buried trench/open-cavity cooling structures in a substrate. Arana teaches stacked-die semiconductor package structures including a substrate and a first die over the substrate with a second die over the first die, and Jha teaches integrated circuit package structures having embedded devices and integrated thermal-management features. Hsu further teaches a heat spreading structure or lid attached to a package structure.
It would have been obvious to modify the stacked semiconductor package of to include the heat spreading structure attached to the package structure, as taught by Hsu, in order to improve heat dissipation and thermal control in the semiconductor package.
Regarding claim 22, Jun in view of Arana, Jha and Hsu teaches the semiconductor package according to claim 20.
Jun teaches a semiconductor device having buried trench/open-cavity cooling structures in a substrate. Arana teaches stacked-die semiconductor package structures including a substrate and a first die over the substrate with a second die over the first die, and Jha teaches integrated circuit package structures having embedded devices and integrated thermal-management features. Hsu further teaches attaching a heat spreading structure to the backside of a die by a thermal interface material, and Arana likewise teaches use of a thermal interface material between a die and an integrated heat spreader.
It would have been obvious to provide the claimed thermal backside interface material between the die and the heat spreading structure in the modified package, as such thermal interface materials were known to improve thermal conduction and package cooling performance.
Regarding claim 23, Jun in view of Arana, Jha and Hsu teaches the semiconductor package according to claim 20.
Jun teaches a semiconductor device having buried trench/open-cavity cooling structures in a substrate. Arana teaches stacked-die semiconductor package structures including a substrate and a first die over the substrate with a second die over the first die, and Jha teaches integrated circuit package structures having embedded devices and integrated thermal-management features. Hsu further teaches a heat spreading structure or lid attached to a package structure with fluidic cooling passages, and Arana teaches gaskets and sealing materials including solder material, elastomer material, and curable material for sealing fluidic package structures and preventing leakage.
It would have been obvious to provide the claimed sealing interface material around the heat spreading structure in the modified package in order to seal the fluidic cooling arrangement and prevent leakage, as suggested by the combination of Hsu and Arana.
Response to Arguments
Applicant’s arguments with respect to claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues Jun does not disclose a “trench” because Jun allegedly discloses a plurality of open cavities or a discontinuous array, and further argues Jun fails to teach a trench having a substantially constant width at the backside surface as it traverses the semiconductor substrate.
However, applicant’s argument is not persuasive. Jun teaches a semiconductor substrate having trench- or cavity-based cooling structures formed in the substrate by etching, and the rejection relied on Jun for the disclosure of a trench extending through the semiconductor substrate. The fact that Jun describes a plurality of channels/cavities or a micro heat sink array does not negate that the structure is trench-like and spans the substrate in a cooling configuration. Further, Applicant has amended the claims to recite that the trench width at the backside surface is substantially constant as the trench traverses the substrate. Jun’s disclosure of etched cooling structures with defined geometry would have suggested to one of ordinary skill in the art controlling feature dimensions to achieve manufacturable and functional cooling channels. Applicant’s reliance on Jun’s discussion of microloading does not amount to a teaching away from the claimed structure; rather, it identifies a process consideration that a POSITA would have addressed through routine process optimization. See MPEP § 2143; In re Gurley, 27 F.3d 551 (Fed. Cir. 1994).
Applicant argues Arana’s fluidic channel is located in underfill layer 115 and therefore cannot satisfy the claim requirement that the trench be located at a surface of a semiconductor substrate.
Response: This argument is likewise not persuasive in view of the combination applied. The rejection does not rely on Arana alone for the trench structure; rather, Arana is used to supply the stacked-die package context and cooling arrangement. As amended, claim 11 recites a trench located at a surface of the semiconductor substrate and a substantially constant trench width. Jun provides the substrate trench/cavity cooling structure, while Arana provides the stacked semiconductor package environment. The combination would have rendered the claimed arrangement obvious to a POSITA because it merely places known cooling and stacked package features together in a predictable manner to improve thermal performance.
Applicant further argues the Examiner’s motivation to combine concedes that Arana avoids trenching the substrate. That is not persuasive. The proposed combination is not premised on adopting Arana’s channel location literally, but on using Arana’s stacked package architecture in conjunction with Jun’s substrate trench cooling. A reference need not disclose the exact final arrangement to support obviousness where the combination would have been a predictable use of prior art elements according to their established functions.
Applicant argues Jha’s solder 125 and Neal’s solder joints 103 are merely die-to-substrate interconnects and do not attach a heat spreading structure hermetically to a package structure.
Applicant’s argument is not persuasive because the rejection relied on the combined teachings of Jha and Neal for the claimed sealing structure, not on a single reference in isolation. Jha teaches solder interconnects in a semiconductor package context, while Neal teaches hermetic sealing in a thermal module assembly. A POSITA would have found it obvious to apply known solder-based attachment/sealing techniques in a package having a heat spreading structure to provide both mechanical attachment and fluid containment. Applicant’s attempt to distinguish the particular location of Neal’s hermetic seal is unavailing because the rejection is directed to the claimed functional relationship of a solder-containing sealing structure hermetically attaching the heat spreading structure to the package structure, which would have been a predictable variation of known package sealing techniques.
Applicant’s arguments on the method claims largely mirror the apparatus arguments. The arguments are not persuasive for the same reasons discussed above. Jun expressly teaches forming trench/cavity cooling structures by etching, which supports claim 25. For claim 24, the method of forming a semiconductor die with backside trench formation would have been obvious over Jun in view of the other cited references because the claimed trench geometry and location are a predictable design choice in semiconductor thermal management. The inclusion of a substantially constant width at the backside surface does not distinguish over the art where the prior art teaches dimension-controlled trenching and ordinary process optimization.
In view of the above, Applicant’s arguments do not overcome the prima facie case of obviousness. The cited references, taken as a whole, would have suggested the claimed subject matter to a person of ordinary skill in the art at the time of the invention. Accordingly, the rejections should be maintained, subject to any necessary clarification of the applied references in the rejection language.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUE A PURVIS whose telephone number is (571)272-1236. The examiner can normally be reached M-F 0830 to 1630.
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/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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