DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on December 21, 2021, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on September 19, 2025, including amendments to claim 1, and new claim 19, has been entered.
Claims 1-2, 4-6 and 8-19 are pending.
Response to Amendment
The amendments to the Claims filed September 19, 2025 have been entered. Applicant’s amendments to the Claims have failed to overcome each and every rejection set forth in the previous Office Action filed May 19, 2025.
Double Patenting
In the previous Office Action filed May 19, 2025, claims 1, and claims 2, 4-6, and 8-18, dependent therefrom, were provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, and 13 - 16 of Application No. 18/224,585, filed July 21, 2023, and issued as U.S. Pat. No. 12,355,436 on July 8, 2025, after the previous Office Action was filed.
However, Applicant’s amendments have overcome the provisional nonstatutory double patenting rejection, therefore the rejection has been withdrawn.
Response to Arguments
Applicant's arguments filed September 19, 2025 have been fully considered but they are not persuasive.
Applicant’s arguments B – E, on pages 9-11, that each of dependent claims 2, 4-6 and 8-18 separately recite subject matter not described or suggested by any of the cited references, whether taken individually or in combination, are not persuasive. Applicant has not provided any arguments pointing out the specific distinctions believed to render the claims patentable over the applied references.
In response to Applicant’s arguments on pages 9-11, that the dependent claims are patentably distinct over the prior art, and are also allowable based at least on their dependency from the independent claim 1, as amended, see the rejections of the claims below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-6, 8, 9, 13-15, and 19 are rejected under 35 U.S.C. 103 as being anticipated by Kanschat, et al., U.S. Pub. No. 2011/0148549 A1 (hereinafter Kanschat) in view of Nakashiba, U.S. Pub. No. 2010/0264515 A1 (hereinafter Nakashiba), and further in view of Ng et al., US 2009/0206817 A1 (hereinafter Ng).
Regarding claim 1, as amended, Kanschat teaches: An insulating chip (Kanschat, Fig. 1, Fig. 4) that is able to connect a low voltage circuit (Kanschat, Fig. 4, transmitter circuit 5, [para 0027]) and a high voltage circuit (Kanschat, Fig. 4, receiver circuit 6, [para 0027]; Kanschat teaches “Circuits that have different voltage domains are circuits that process voltage signals that are related to different references voltages. Such circuits having different voltage domains are, for example, circuits that are galvanically decoupled and/or circuits that are ‘separated’ by a potential barrier.” [para 0027] For purposes of examination, the transmitter circuit 5 will be referred to as a low voltage circuit, and receiver circuit 6 will be referred to as a high voltage circuit. Because there are two different voltages, one is necessarily higher than the other. This interpretation is supported by Applicant’s disclosure, wherein low voltage is interpreted as a first voltage, and high voltage is interpreted as a voltage higher than the first voltage [See Applicant’s disclosure, para 0005]), the insulating chip comprising: a substrate (Kanschat, Fig. 4, substrate 110, [para 0030]); an insulating layer formed on the substrate (Kanschat, Fig. 4, dielectric layer 120, [para 0030]); (Kanschat, Fig. 1, first transformer 2, [para 0024]) including a first conductor (Kanschat, primary winding 21 of the first transformer, Fig. 4, [para 0024]) and a second conductor (Kanschat, secondary winding 22 of the first transformer, Fig. 4, [para 0024]), wherein the first conductor and the second conductor are embedded into the insulating layer (Kanschat, Fig. 4, “the two transformers 2, 3 are realized in a common dielectric layer 120”, [para 0047]) and arranged to face each other (Kanschat, See Fig. 4); and a second element (Kanschat, second transformer 3, Fig. 1, [para 0024]) including a third conductor (Kanschat, secondary winding 32 of the second transformer, Fig. 4, [para 0024]) and a fourth conductor (Kanschat, primary winding 31 of the second transformer, Fig. 4, [para 0024]), wherein the third conductor and the fourth conductor are embedded into the insulating layer (Kanschat, Fig. 4, “the two transformers 2, 3 are realized in a common dielectric layer 120”, [para 0047]) and arranged to face each other (Kanschat, See Fig. 4), wherein the first element and the second element are connected in series (Kanschat, See Fig. 4; “by providing two transformers 2, 3 that are connected in series with each other for a given layer thickness of dielectric layer 120 a maximum blocking voltage between the input and the output of the signal transmission arrangement can be obtained that is twice the maximum blocking voltage that can be obtained when using only one transformer.” see also [para 0037]), the low voltage circuit and the high voltage circuit are connected through the first element and the second element (Kanschat, Shown in Fig. 1; see also [para 0025-0026]) and are configured to transmit signals through the first element and the second element (Kanschat, Fig. 1, “first transformer 2 receives the input signal Sin at its primary winding 21 and generates a first intermediate signal V22 from the input signal Sin at its secondary winding 22. The second transformer 3 receives the intermediate signal V22 at its primary winding 31 and generates the output signal Sout from the intermediate signal V22.” [para 0028]), the first conductor (Kanschat, FIG. 6, primary winding 21 of the first transformer) is arranged closer to the substrate (Kanschat, Fig. 6, first substrate 210) than the second conductor (Kanschat, FIG. 6, secondary winding 22 of the first transformer) in a thickness direction (vertical direction, as shown in Kanschat, Fig. 6) of the insulating layer (Kanschat, Fig. 6, dielectric layer 220), the third conductor (Kanschat, secondary winding 32 of the second transformer, Fig. 6) is arranged closer to the substrate (Kanschat, Fig. 6, second substrate 310) than the fourth conductor (Kanschat, primary winding 31 of the second transformer, Fig. 6) in the thickness direction of the insulating layer (Kanschat, Fig. 6, dielectric layer 320), (Kanschat, Fig. 6, “the transmitter circuit 5 [the low voltage circuit] (that is only schematically shown) is integrated in the first semiconductor substrate 210 and is electrically connected to the primary winding 21 of the first transformer [the first conductor].” [para 0047]; “The receiver circuit 6 [the high voltage circuit] (that is only schematically shown) is integrated in the second semiconductor substrate 310 and is connected to the secondary winding 32 of the second transformer [the third conductor].” [para 0050]).
Kanschat does not explicitly teach: a distance between the first conductor and the second conductor is larger than a distance between the third conductor and the fourth conductor, and a distance between the third conductor and the substrate is larger than a distance between the first conductor and the substrate.
However, Nakashiba, in the same field of endeavor, teaches: a distance between the first conductor and the second conductor is larger than a distance between the third conductor and the fourth conductor (Nakashiba, FIG. 9 shows distance between first inductor 302 [the first conductor] and the third inductor [the second conductor]) is larger than a distance between the second inductor [the third conductor] and the fourth inductor 324 [the fourth conductor], and a distance between the third conductor and the substrate is larger than a distance between the first conductor and the substrate (Nakashiba, FIG. 9 shows a larger distance between the second inductor [the third conductor] and the substrate than the distance between first inductor 302 [the first conductor] and the substrate.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kanschat with the teachings of Nakashiba, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Nakashiba, to maximize the efficiency of signal transfer between the low voltage circuit and the high voltage circuit, thereby improving accuracy of signal transmission and device reliability.
Kanschat in view of Nakashiba is silent regarding: a first structure configured to transmit a set signal from the low voltage circuit to the high voltage circuit; and a second structure configured to transmit a reset signal from the low voltage circuit to the high voltage circuit, wherein each of the first structure and the second structure includes. However, Ng, in the same field of endeavor, discloses a high voltage drive circuit with means for signal transfer between drive and receive circuits, comprising: a first structure configured to transmit a set signal from the low voltage circuit to the high voltage circuit (Ng, FIG. 10, the first structure is shown as the upper components on the low voltage side 80 [the low voltage circuit], including logic driver 84a and corresponding capacitor pairs 10a/10b and 11a/11b, configured to transmit set/reset signal [a set signal] from low power oscillator 81 across capacitive isolation barrier 88 to the high voltage side 90 [the high voltage circuit], [0053-0055]); and a second structure configured to transmit a reset signal from the low voltage circuit to the high voltage circuit (Ng, FIG. 10, the second structure is shown as the lower components on the low voltage side 80 [the low voltage circuit], including logic driver 84b and corresponding capacitor pairs 12a/12b and 13a/13b, configured to transmit set/reset signal [a reset signal] from low power oscillator 81 across capacitive isolation barrier 88 to the high voltage side 90 [the high voltage circuit], [0053-0055]). Ng teaches that this structural arrangement is advantageous because “by using a single pair of capacitors for signal coupling in each channel, excellent common mode rejection characteristics are provided,” (Ng, [0053]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kanschat in view of Nakashiba with the teachings of Ng, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Ng, to improve common mode rejection, thereby improving circuit performance.
Regarding claim 2, Kanschat in view of Nakashiba and further in view of Ng teaches: The insulating chip according to claim 1, wherein the insulating chip is mounted (Kanschat, “mounted on the board such that the secondary winding 22 of the first transformer and the primary winding 31 of the second transformer are interconnected through the connection lines of the board.” [para 0049]) on a low voltage die pad (Kanschat, See Fig. 6, terminals 23, 24 are equivalent to the low voltage die pad [see para 0047-0051]), wherein a low voltage circuit chip including the low voltage circuit is on the low voltage die pad (Kanschat, Fig. 6, transmitter circuit 5, “the transmitter circuit 5 [the low voltage circuit] (that is only schematically shown) is integrated in the first semiconductor substrate 210 and is electrically connected to the primary winding 21 of the first transformer.” [para 0047]), and the second conductor and the fourth conductor are electrically connected. (Kanschat, Figs. 6-7, “The first secondary winding 22 [the second conductor] and the second primary winding 31 [the fourth conductor] are electrically connected” [para 0051]).
Regarding Claims 4-6 and 19, Kanschat in view of Nakashiba and further in view of Ng teaches all of the elements of claims 4-6 and 19 but does not explicitly teach each of the claimed structural arrangements of the conductors relative to each other and to the substrate. However, for the reasons discussed above regarding claim 1, the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art.
It would have been obvious to a person having ordinary skill in the art that the distance parameter between conductors (transformer windings, capacitor plates) is a result-effective variable, i.e., a variable which achieves a recognized result, and that for any desired maximum withstand voltage the required distance between the conductor (transformer winding, capacitor plate) and the substrate, or between individual conductors (transformer windings, capacitor plates) may be determined without undue experimentation. Applicant has provided no evidence indicating that this distance is critical or produces any unexpected results.
Applicant has disclosed embodiments wherein the “conductors” are transformer windings, or alternatively, the “conductors” are capacitor plates.
Kanschat teaches the concept of changing the form, proportions, or degree of positioning of conductors relative to one another. Specifically, as discussed in the Background section of Kanschat, it is well known in the art that “The maximum voltage difference between the two voltage domains the transformer can withstand is dependent on the distance between the transformer windings and the isolation properties of the used isolation material (dielectric layer). The maximum difference voltage increases with increasing distance” (Kanschat, [para 0003]). Similarly, it is well known in the art that modifying the distance between capacitor plates has a predictable effect on the voltage.
"It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.” In re Williams, 36 F.2d 436, 438 (CCPA 1929).
Applicant’s claimed arrangements of the conductors relative to each other and to the substrate in claims 4-6 and 19 are merely variations within a finite number of identified, predictable solutions. The motivation is provided by design need or market pressure to improve marketability by reducing the thickness of dielectric layers in order to improve process accuracy and reliability, as expressly recognized by Kanschat (see [0003]), which also reduces the final dimensions of the insulating chip package while maintaining or increasing the amount of isolation between insulating elements.
Regarding claim 8, Kanschat in view of Nakashiba and further in view of Ng teaches: The insulating chip according to claim 1, wherein the second conductor (Kanschat, secondary winding 22 of the first transformer, Fig.1, Fig. 4) and the fourth conductor (primary winding 31 of the second transformer, Fig.1, Fig. 4) are arranged at positions in line with each other in the thickness direction (vertical direction, as shown in Fig. 4) of the insulating layer (Kanschat, See Fig. 4, dielectric layer 120).
Regarding claim 9, Kanschat in view of Nakashiba and further in view of Ng teaches: The insulating chip according to claim 1, wherein the substrate is a substrate formed from a material containing Si (Kanschat, “Substrate 110 in particular is – but is not restricted to – a semiconductor substrate, such as a monocrystalline silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs) substrate” [para 0030]).
Regarding claim 13, Kanschat in view of Nakashiba and further in view of Ng teaches: The insulating chip according to claim 9, wherein the first conductor (Kanschat, primary winding 21 of the first transformer, Fig. 4) and the third conductor (Kanschat, secondary winding 32 of the second transformer, Fig. 4) are arranged at positions in line with each other in the thickness direction (vertical direction, as shown in Fig. 4) of the insulating layer (Kanschat, See Fig. 4, dielectric layer 120).
Regarding claim 14, Kanschat in view of Nakashiba and further in view of Ng teaches: The insulating chip according to claim 1, wherein the first element includes a first transformer (Kanschat, Fig. 1, first transformer 2) including a first coil (Kanschat, primary winding 21 of the first transformer, Fig.1, Fig. 4) as the first conductor and a second coil (Kanschat, secondary winding 22 of the first transformer, Fig.1, Fig. 4) as the second conductor, and the second element includes a second transformer (Kanschat, second transformer 3, Fig. 1) including a third coil (Kanschat, secondary winding 32 of the second transformer, Fig.1, Fig. 4) as the third conductor and a fourth coil (Kanschat, primary winding 31 of the second transformer, Fig.1, Fig. 4) as the fourth conductor.
Regarding claim 15, Kanschat in view of Nakashiba and further in view of Ng teaches: The insulating chip according to claim 1, wherein the first element includes a first capacitor (Kanschat, Fig. 13, first capacitor 102, [para 0066]) including a first electrode plate (Kanschat, first capacitor plate 121 of the first capacitor, Fig.13, Fig. 14) as the first conductor and a second electrode plate (Kanschat, second capacitor plate 122 of the first capacitor, Fig.13, Fig. 14) as the second conductor, and the second element includes a second capacitor (Kanschat, second capacitor 103, Fig. 13, [para 0066]) including a third electrode plate (Kanschat, second capacitor plate 132 of the second capacitor, Fig.13, Fig. 14) as the third conductor and a fourth electrode plate (Kanschat, first capacitor plate 131 of the second capacitor, Fig.13, Fig. 14) as the fourth conductor. (Also see Kanschat Claim 15; Figs. 13-14).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kanschat in view of Nakashiba and further in view of Ng, as applied to claim 1 above, and further in view of Tanaka et al., U.S. Pub. No. US 2018/0130587 A1 (hereinafter Tanaka).
Regarding claim 10, Kanschat in view of Nakashiba and further in view of Ng teaches every element of claim 10 except: wherein the substrate is a substrate formed from a material containing glass.
However, Tanaka, in the same field of endeavor, teaches: wherein the substrate is a substrate formed from a material containing glass (Tanaka, “an insulating substrate made of an arbitrary insulating material may be adopted as the substrate 42. The insulating substrate is a glass substrate, a ceramic substrate, etc., by way of example” [para 0258]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kanschat in view of Nakashiba and further in view of Ng with the teachings of Tanaka to arrive at an insulating chip wherein the substrate is a substrate formed from a material containing glass, in order to provide an electrically insulating substrate which would allow for increased withstand voltage. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability, and the electrically insulating qualities of glass are well known in the art.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kanschat in view of Nakashiba and further in view of Ng, as applied to claim 1 above, and further in view of Peng et al., U.S. Pub. No. 2018/0204665 A1 (hereinafter Peng).
Regarding claim 11, Kanschat in view of Nakashiba and further in view of Ng teaches every element of claim 11 except: wherein the substrate is a substrate including a first semiconductor layer, a second semiconductor layer, and a semiconductor oxide layer arranged between the first semiconductor layer and the second semiconductor layer.
However, Peng, in the same field of endeavor, teaches: wherein the substrate is a substrate including a first semiconductor layer, a second semiconductor layer, and a semiconductor oxide layer arranged between the first semiconductor layer and the second semiconductor layer (Peng, “The silicon substrate may be a bulk silicon wafer or may be a thin layer of silicon (on an insulating layer commonly known as silicon-on-insulator or SOI) that is, in turn, supported by a carrier wafer” [para 0023]).
It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability, and the Silicon On Insulator substrate was well known in the art before the effective filing date of the claimed invention (See Applicant’s website, “This technology is widely adopted in power devices and MEMS. In MEMS the oxide layer can be used as a stopper layer for silicon etching, making it possible to form complex 3-dimensional structures”, 28 Sept. 2020, available at: https://web.archive.org/web/20200928020117/https://www.rohm.com/electronics-basics/piezo/ mems). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kanschat in view of Nakashiba and further in view of Ng with the teachings of Peng to arrive at an insulating chip wherein the substrate is a substrate including a first semiconductor layer, a second semiconductor layer, and a semiconductor oxide layer arranged between the first semiconductor layer and the second semiconductor layer with a high likelihood of success and without undue experimentation.
Regarding claim 12, Kanschat in view of Nakashiba and further in view of Ng and further in view of Peng teaches: The insulating chip according to claim 11, wherein a dividing band (Kanschat, Fig. 4, trench 123 [para 0039]) that contains an insulating material (Kanschat, “The filling material is, e.g., a glass.” [para 0039]) and that goes through the second semiconductor layer to reach the semiconductor oxide layer (Peng, teaches silicon-on-insulator [para 0023]) is formed on the second semiconductor layer (Kanschat, Fig. 4, “trench 123 extends through the dielectric layer 120 down to the substrate 110,” [para 0039]), and the dividing band is arranged between the first conductor and the third conductor (Kanschat, Fig. 4, “This trench is arranged between the two transformers 2,3” [para 0039]) as viewed from the thickness direction (vertical direction, as shown in Kanschat, Fig. 4) of the insulating layer and is provided to divide the second semiconductor layer into a first divided semiconductor layer (Kanschat, Fig. 4, region on left side of trench 123) facing the first conductor and a second divided semiconductor layer (Kanschat, Fig. 4, region on right side of trench 123) facing the third conductor (Kanschat, Fig. 4, “trench 123 extends through the dielectric layer 120 down to the substrate 110. This trench is arranged between the two transformers 2,3 in the dielectric layer 120, and is optionally filled with an insulation material.” [para 0039]).
It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability, and as discussed earlier regarding claim 11, the Silicon On Insulator substrate was well known in the art before the effective filing date of the claimed invention. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kanschat in view of Nakashiba and further in view of Ng and further in view of Peng to arrive at an insulating chip wherein the substrate is a substrate including a first semiconductor layer, a second semiconductor layer, and a semiconductor oxide layer arranged between the first semiconductor layer and the second semiconductor layer; and wherein a dividing band that contains an insulating material and that goes through the second semiconductor layer to reach the semiconductor oxide layer is formed on the second semiconductor layer. The motivation to do so would be to improve marketability by reducing the size of the insulating chip package, while maintaining or increasing the amount of isolation between insulating elements.
Claims 16 – 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kanschat in view of Nakashiba and further in view of Ng and further in view of Osada et al., U.S. Pub. No. 2015/0137314 A1 (hereinafter Osada):
Regarding claim 16, Kanschat in view of Nakashiba and further in view of Ng teaches every element of claim 16 but does not explicitly teach: wherein the low voltage circuit is connected to a first reference potential and the high voltage circuit is connected to a second reference potential, the first reference potential being independent of the second reference potential, and a voltage of the low voltage circuit is based on the first reference potential and a voltage of the high voltage circuit is based on the second reference potential.
However, Osada, in the same field of endeavor, teaches: wherein the low voltage circuit is connected to a first reference potential (Osada, FIG. 2, controller chip 5 [the low voltage circuit] is connected to 5 volt reference potential, [0078]) and the high voltage circuit is connected to a second reference potential (Osada, FIG. 2, driver chip 7 [the high voltage circuit] is connected to 1200 volt reference potential, [0079-0080]), the first reference potential being independent of the second reference potential, and a voltage of the low voltage circuit is based on the first reference potential and a voltage of the high voltage circuit is based on the second reference potential (Osada, FIG. 2 shows low voltage circuit based on 5 volt reference potential, high voltage circuit based on 1200 volt reference potential). Additionally, Nakashiba teaches “the reference voltage of the transmission-side circuit [the low voltage circuit] and the reference voltage of the reception-side circuit [the high voltage circuit] differ from each other,” [0008].
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kanschat in view of Nakashiba and further in view of Ng with the teachings of Osada, arriving at Applicant’s claimed invention wherein the low voltage circuit is connected to a first reference potential and the high voltage circuit is connected to a second reference potential, the first reference potential being independent of the second reference potential, and a voltage of the low voltage circuit is based on the first reference potential and a voltage of the high voltage circuit is based on the second reference potential with predictable results and without undue experimentation. The motivation for doing so would be to provide suitable reference potentials for the low voltage circuit and for the high voltage circuit as is well known in the art, as expressly recognized by Kanschat, Nakashiba, Ng, and Osada.
Regarding claim 17, Kanschat in view of Nakashiba and further in view of Ng and further in view of Osada teaches: The insulating chip according to claim 1, wherein the insulating layer (Kanschat, Fig. 4, dielectric layer 120, [para 0030]; Nakashiba, FIGs. 1, 4, and 9, multilayer interconnect 400, [0043]) is directed to an insulating layer laminated body including a plurality of laminated insulating layers on the substrate (Nakashiba, multilayer interconnect 400, “the multilayer interconnect 400 has a structure that is formed by stacking an insulating layer 410, an interconnect layer 412, an insulating layer 420, an interconnect layer 422, an insulating layer 430, an interconnect layer 432, an insulating layer 440, and an interconnect layer 442 in this order,” [0043]; Osada, FIG. 6, “The insulating layer laminated structure 27 is composed of a plurality of (twelve in FIG. 6) insulating layers which are laminated successively from the surface of the semiconductor substrate 26,” [0084]), the first conductor is embedded into a first insulating layer of the insulating layer laminated body, the second conductor and the fourth conductor are embedded into a second insulating layer of the insulating layer laminated body, and the third conductor is embedded into a third insulating layer of the insulating layer laminated body (Nakashiba, see FIGs. 1, 4, and 9, and associated text; Osada, FIG. 6, “lower coil 20 and the upper coil 21 are formed in different insulating layers 28 in the insulating layer laminated structure 27 and face each other with one or more insulating layers 28 sandwiched therebetween,” [0085]).
Regarding claim 18, Kanschat in view of Nakashiba and further in view of Ng and further in view of Osada teaches: The insulating chip according to claim 17, wherein the second insulating layer (Nakashiba, see FIGs. 1, 4, and 9, the second insulating layer is analogous to the layer containing third inductor 304 [the second conductor] and fourth inductor 324 [the fourth conductor]; Osada, FIG. 6, “upper coil 21 is formed in an insulating layer 28, which is the eleventh layer,” [0085]) is arranged higher than the first insulating layer and the third insulating layer in a thickness direction of the insulating layer laminated body (Nakashiba, see FIGs. 1, 4, and 9, the first insulating layer is shown as the layer containing first inductor 302 [the first conductor], [0044]; the third insulating layer is shown as the layer containing second inductor 322 [the third conductor]), and the third insulating layer is arranged higher than the first insulating layer in the thickness direction of the insulating layer laminated body (Nakashiba, see FIGs. 1, 4, and 9).
Conclusion
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/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899