DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/14/25 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 2/06/26. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagumo (US 2017/0309638, hereinafter referred to as “Nagumo”).
Nagumo discloses the semiconductor device as claimed. See figures 4A-4M and corresponding text, where Nagumo teaches, in claim 1, a method for semiconductor device fabrication, the method comprising:
forming a vertical structure in a stack of layers (110) with an end in a first layer (30) by a first processing that is performed on a first side of a first die, the stack of layers and the first layer being on the first side of the first die: and
replacing the first layer with a second layer (80) by a second processing that is performed on a second side of the first die that is opposite to the first side, a material of the first layer having a better etch selectivity to the stack of layers than a material of the second layer (figures 4A-4M; [0036-0049]).
Nagumo teaches, in claim 2, wherein the material of the first layer includes tungsten and the material of the second layer includes polysilicon (figures 4A-4M; [0036-0049]).
Nagumo teaches, in claim 3, wherein the vertical structure corresponds to a channel structure including a channel layer (figures 4A-4M; [0036-0049]).
Nagumo teaches, in claim 4, wherein the first layer is included in an initial first stack of layers in a core region of the first die, the stack of layers corresponds to an initial second stack of layers, and the method further comprises:
forming the initial second stack of layers that comprises insulating layers and sacrificial gate layers stacked alternatingly over the initial first stack of layers (figures 4A-4M; [0036-0049]).
Nagumo teaches, in claim 5, wherein forming the vertical structure comprises: forming a channel hole in the stack of layers with an end in the first layer; and
forming the channel structure in the channel hole (figures 4A-4M; [0036-0049]).
Nagumo teaches, in claim 6, wherein the channel structure includes a blocking insulating layer, a charge storage layer and a tunneling insulating layer (figures 4A-4M; [0036-0049]).
Nagumo teaches, in claim 7, wherein replacing the first layer with the second layer further comprises:
removing the first layer by the second processing that is performed on the second side of the first die: and
removing the blocking insulating layer, the charge storage layer, and the tunneling insulating layer from an end of the channel structure by the second processing that is performed on the second side of the first die (figures 4A-4M; [0036-0049]).
Nagumo teaches, in claim 8, wherein replacing the first layer with the second layer further comprises: forming the second layer in contact with the channel layer at an end of the channel structure (figures 4A-4M; [0036-0049]).
Nagumo teaches, in claim 9, wherein the second layer corresponds to a semiconductor layer (figures 4A-4M; [0036-0049]).
Nagumo teaches, in claim 10, wherein replacing the first layer with the second layer further comprises:
forming a liner portion of the second layer the liner portion contacting the channel layer at an end of the channel structure;
performing ion implantation to dope the liner portion; and
forming a bulk portion of the second layer (figures 4A-4M; [0036-0049]).
Nagumo teaches, in claim 11, further comprising:
forming a pad structure on the second side of the first die, the pad structure being conductively connected with the second layer (figures 4A-4M; [0036-0049]).
Nagumo teaches, in claim 12, wherein the vertical structure corresponds to a dummy channel structure (figures 4A-4M; [0036-0049]).
Nagumo teaches, in claim 13, wherein the first layer is included in an initial first stack of layers in a staircase region of the first die, the stack of layers corresponds to an initial second stack of layers, and the method further comprises:
forming the initial second stack of layers that comprises insulating layers and sacrificial gate layers stacked alternatingly over the initial first stack of layers;
forming stair steps based on the initial second stack of layers in the staircase region; and
planarizing the staircase region using an insulating material (figures 4A-4M; [0036-0049]).
Nagumo teaches, in claim 14, wherein forming the vertical structure comprises:
forming a dummy channel hole in the stack of layers, an end of the dummy channel hole being in the first layer; and
forming the dummy channel structure in the dummy channel hole (figures 4A-4M; [0036-0049]).
Nagumo teaches, in claim 15, wherein the vertical structure corresponds to a gate line slit structure (figures 4A-4M; [0036-0049]).
Nagumo teaches, in claim 16, wherein the first layer is included in an initial first stack of layers in a gate line slit region of the first die, the stack of layers corresponds to an initial second stack of layers, and the method further comprises:
forming the initial second stack of layers that comprises insulating layers and sacrificial gate layers stacked alternatingly over the initial first stack of layers (figures 4A-4M; [0036-0049]).
Nagumo teaches, in claim 17, wherein forming the vertical structure comprises: forming channel structures in the initial second stack of layers;
forming a trench in the initial second stack of layers with an end in the first layer;
replacing, via the trench, the sacrificial gate layers with gate layers; and
forming a gate line slit structure in the trench (figures 4A-4M; [0036-0049]).
Nagumo teaches, in claim 18,further comprising:
forming a punch through contact structure in a punch through region by the first processing that is performed on the first side of the first die (figures 4A-4M; [0036-0049]).
Nagumo teaches, in claim 19, further comprising: forming bonding structures on the first side of the first die; and
bonding the first side with a second die before the second processing that is performed on the second side of the first die (figures 4A-4M; [0036-0049]).
Nagumo teaches, in claim 20, further comprising:
forming a through silicon contact by the second processing that is performed on the second side of the first die, the through silicon contact connecting a punch through contact structure with a pad structure on the second side of the first die (figures 4A-4M; [0036-0049]).
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 January 7, 2026