Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/02/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (Pub. No.: US 2021/0384074) in view of Parikh (Patent No.: US 10629484) filed in the IDS on 01/04/2022.
Re claim 1, Chen, FIG. 19B teaches a semiconductor device, comprising:
a first conductive lower wiring (left 214c, ¶ [0030]) disposed an insulating layer (212) at a first metal level and that extends in a first horizontal direction (along the bottom horizontal width of left 214c) parallel to an upper surface of the insulating layer (along the bottom horizontal width of 212);
an etch stop layer (226) disposed on (indirectly) the first conductive lower wiring (left 214c) and in contact with the upper surface of the insulating layer (212);
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a first upper wiring structure connected to the first conductive lower wiring and that includes a first conductive upper wiring ([FCUW], FIG. 19B [as shown above]) and a first conductive upper via [FCUV], wherein the first conductive upper wiring (left 234) is disposed at a second metal level higher than the first metal level and extends in a second direction different from the first direction; and
a conductive insertion pattern (left 214p, [0030]) disposed between the first conductive lower wiring (left 214c) and the first upper wiring structure ([FCUW]+FCUV]) and connected to the first conductive upper via [FCUV],
wherein the first conductive upper via [FCUV] is disposed between the first conductive upper wiring [FCUW] and the conductive insertion pattern (left 214p);
wherein the first conductive upper wiring (left [234+238]) and the conductive insertion pattern (left 214p) are spaced vertically apart by a thickness of the first conductive upper via ([vertical thickness of [FCUV]),
wherein the conductive insertion pattern (left 214p) includes an upper surface and a bottom surface opposed in a vertical direction perpendicular to the first horizontal direction (directly along the bottom surface of 212) and the second horizontal direction (indirectly along top surface of 212),
wherein the bottom surface of the conductive insertion pattern (left 214p) is in contact with an upper surface of the first conductive lower wiring (left 214c),
wherein the etch stop layer (226) includes an upper surface and a bottom surface opposed in the vertical direction,
wherein the bottom surface of the etch stop layer (226) is in direct contact with the upper surface of the insulating layer (212),
wherein an upper surface of the conductive insertion pattern (left 214p) is in direct contact with a bottom surface of the first conductive upper via [FCUV],
wherein the first conductive upper wiring (MIDDLE [234+238}, FIG. 19B [as shown above]) does not contact the upper surface of the conductive insertion pattern (left 214p),
wherein the upper surface of the conductive insertion pattern (left 214p) has a first width in the first horizontal direction,
wherein the bottom surface of the first conductive upper via [FCUV] has a second width (left 238) in the first horizontal direction that is less than the first width (because of 234),
wherein a sidewall of the conductive insertion pattern (214p) connecting the upper surface (240) of the conductive insertion pattern and the bottom surface of the conductive insertion pattern is in contact (indirectly) with the etch stop layer (226), and
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wherein the conductive insertion pattern has a single layer structure [CInP], FIG. 19B [as shown above].
Chen fails to teach wherein a height from the upper surface of the first conductive lower wiring to the upper surface of the conductive insertion pattern is greater than a height from the upper surface of the first conductive lower wiring to the upper surface of the etch stop layer; and wherein the bottom surface of the conductive insertion pattern and the bottom surface of the etch stop layer are coplanar with each other.
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Parikh teaches wherein a height from the upper surface of the first conductive lower wiring (left/middle 106) to the upper surface of the conductive insertion pattern (120+125) is greater than a height from the upper surface of the first conductive lower wiring (left/middle 106) to the upper surface of the etch stop layer (112/114); and wherein the bottom surface of the conductive insertion pattern (120, FIG. 11A [as shown above]) and the bottom surface of the etch stop layer (112/114) are coplanar [CoP] with each other.
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of decreasing via resistance and reducing the potential to short to the wrong metal line as taught by Parikh, Abstract.
Re claim 2, in the combination, Chen, FIG. 19B teaches the semiconductor device of claim 1, wherein the upper surface of the conductive insertion pattern has a third width in the second horizontal direction (214p), and
the bottom surface of the first conductive upper via has a fourth width (238) in the second horizontal direction that is less than the third width.
Re claim 3, in the combination, Chen, FIG. 19B teaches the semiconductor device of claim 1, wherein the upper surface of the conductive insertion pattern (214p) and the bottom surface of the first conductive upper via (238) each have a third width in the second horizontal direction.
Re claim 4, in the combination, Chen, FIG. 19B teaches the semiconductor device of claim 1, wherein the conductive insertion pattern (left 214p) is in contact with the first conductive lower wiring (left 214c).
Re claim 5, in the combination, Parikh, FIG. 11A teaches the semiconductor device of claim 1, wherein a thickness of the conductive insertion pattern (bottom-most of 120) is less than a thickness of the first conductive lower wiring (106) and a thickness of the first conductive upper wiring (upper 130+128).
Re claim 6, in the combination, Chen, FIG. 19B teaches the semiconductor device of claim 1, further comprising
wherein a thickness of the conductive insertion pattern (vertical thickness of (214p)) is greater than a thickness of the etch stop layer (vertical thickness of 226).
Re claim 7, in the combination, Chen, FIG. 19B teaches the semiconductor device of claim 1, further comprising:
a second conductive lower wiring (right 214c) disposed at the first metal level and that extends in the first horizontal direction; and
a second upper wiring structure (right [238+234+214p]) connected to the second conductive lower wiring and that includes a second conductive upper wiring (right 234) and a second conductive upper via (right [238+214]),
wherein the second conductive upper wiring (right 234) extends in the second direction at the second metal level, and
the second conductive upper via (right [238+214p]) is directly connected to the second conductive lower wiring (right 214c).
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parikh in view of Chen.
Re claim 1, Parikh, FIG. 11A teaches a semiconductor device, comprising:
a first conductive lower wiring (far left 106, col. 7, lines 25-32) disposed in an insulating layer (104) at a first metal level and that extends in a first horizontal direction (along the top horizontal width of 106, FIG. 11A) parallel to an upper surface of the insulating layer (along the top horizontal width of 104);
an etch stop layer (112/114) disposed on the first conductive lower wiring (left/middle 106) and in contact with the upper surface of the insulating layer (104);
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a first upper wiring structure connected to the first conductive lower wiring and that includes a first conductive upper wiring ([FCUW], FIG. 11B [as shown below]) and a first conductive upper via [FCV], wherein the first conductive upper wiring is disposed at a second metal level higher than the first metal level and extends in a second direction (vertical) different from the first direction; and
a conductive insertion pattern (120) disposed between the first conductive lower wiring (106) and the first upper wiring structure [FCUW] and connected to the first conductive upper via [FCV],
wherein the first conductive upper via [FCV] is disposed between the first conductive upper wiring [FCUW] and the conductive insertion pattern (left 120),
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wherein the first conductive upper wiring [FCUW] and the conductive insertion pattern (120) are spaced vertically apart by a thickness of the first conductive upper via ([TofFCUV], FIG. 11B [as shown above]),
wherein the conductive insertion pattern (120+125) includes an upper surface and a bottom surface opposed in a vertical direction perpendicular to the first horizontal direction (directly along the top surface of 104) and the second first horizontal direction (indirectly along bottom surface of 104),
wherein the bottom surface of the conductive insertion pattern (120) is in contact with an upper surface of the first conductive lower wiring (left/middle 106),
wherein the etch stop layer (112/114) includes an upper surface and a bottom surface opposed in the vertical direction,
wherein the bottom surface of the etch stop layer (112/114) is in direct contact with the upper surface of the insulating layer (104),
wherein the bottom surface of the conductive insertion pattern (120/125, FIG. 11A [as shown above]) and the bottom surface of the etch stop layer (112/114) are coplanar [CoP] with each other,
wherein a height from the upper surface of the first conductive lower wiring (left/middle 106) to the upper surface of the conductive insertion pattern (120) is greater than a height from the upper surface of the first conductive lower wiring (left/middle 106) to the upper surface of the etch stop layer (112/114),
wherein the upper surface of the conductive insertion pattern (left 120+128) is in direct contact with a bottom surface of the first conductive upper via [FCV],
wherein the upper surface of the conductive insertion pattern (upper width of 120+125) has a first width in the first horizontal direction,
wherein the bottom surface of the first conductive upper via (130) has a second width (lower width) in the first horizontal direction that is less than the first width (width of 120+125), and
wherein a sidewall of the conductive insertion pattern (120) connecting the upper surface of the conductive insertion pattern and the bottom surface of the conductive insertion pattern is in contact (directly) with the etch stop layer (112/114), and wherein the conductive insertion pattern has a single layer structure (120).
Parikh fails to teach wherein the first conductive upper wiring does not contact the upper surface of the conductive insertion pattern.
Chen teaches wherein the first conductive upper wiring (MIDDLE 234, FIG. 19B [as shown above]) does not contact the upper surface of the conductive insertion pattern (left 214p),
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of decreasing the contact resistance as taught by Chen, [0002].
Re claim 2, in the combination, Chen, FIG. 19B teaches the semiconductor device of claim 1, wherein the upper surface of the conductive insertion pattern has a third width in the second horizontal direction (214p), and
the bottom surface of the first conductive upper via has a fourth width (238) in the second horizontal direction that is less than the third width.
Re claim 3, in the combination, Chen, FIG. 19B teaches the semiconductor device of claim 1, wherein the upper surface of the conductive insertion pattern (214p) and the bottom surface of the first conductive upper via (238) each have a third width in the second horizontal direction.
Re claim 4, in the combination, Parikh, FIG. 11A teaches the semiconductor device of claim 1, wherein the conductive insertion pattern (120) is in contact with the first conductive lower wiring (106).
Re claim 5, in the combination, Parikh, FIG. 11A teaches the semiconductor device of claim 1, wherein a thickness of the conductive insertion pattern (bottom-most of 120) is less than a thickness of the first conductive lower wiring (106) and a thickness of the first conductive upper wiring (upper 130+128).
Re claim 6, Parikh, FIG. 11A teaches the semiconductor device of claim 1, further comprising
wherein a thickness of the conductive insertion pattern (vertical thickness 120) is greater than a thickness of the etch stop layer (vertical thickness of 114).
Re claim 7, Parikh, FIG. 11A teaches the semiconductor device of claim 1, further comprising:
a second conductive lower wiring (far right 106) disposed at the first metal level and that extends in the first horizontal direction; and
a second upper wiring structure (132/128/134) connected to the second conductive lower wiring and that includes a second conductive upper wiring (right 128) and a second conductive upper via (132/134),
wherein the second conductive upper wiring (128) extends in the second horizontal direction at the second metal level, and
the second conductive upper via (132/134) is directly connected to the second conductive lower wiring (106).
Response to Arguments
Applicant's arguments filed 04/02/2026 have been fully considered but they are not persuasive because
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Parikh teaches wherein the bottom surface of the conductive insertion pattern (120, FIG. 11A [as shown above]) and the bottom surface of the etch stop layer (112/114) are coplanar [CoP] with each other, and wherein the conductive insertion pattern has a single layer structure (120, note that the conductive insertion pattern is now the 120 layer only).
Chen, FIG. 19B still reads on:
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wherein the conductive insertion pattern has a single layer structure [CInP], FIG. 19B [as shown above].
For the above reasons, it is believed that the rejections should be sustained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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