DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 35 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/23/2026 has been entered.
Remarks
The 03/23/2026 amendments of claims 1, 10 and 16 have been noted and entered.
The 03/23/2026 cancellation of claims 5 and 18 has been noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks pages 10-13, filed 03/23/2026, with respect to the objection to claim 10 for minor informalities have been fully considered and are not persuasive in light of the newly added amendments. Examining amended claim 10 reveals that in line 7 of the claim the following statement appears: “… to a temporary tape to place placing the semiconductor chip side by side with the connection substrate,…” (emphasis added). Thus, the objections of record are maintained.
Applicant’s arguments, see Remarks pages 10-13, filed 03/23/2026, with respect to the rejection(s) of claim(s) 1-13, 15-20 and 23 under 35 U.S.C 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Chen et al, US 20200343183 A1 (Chen ‘183).
New Grounds of Rejection
New grounds of rejection, prior art reference Chen et al, US 20200343183 A1 (Chen ‘183) appears below.
Claim Objections
Claim 10 is objected to for the following informalities:
Regarding claim 10: claim 10 contains the following limitations in line 7 of the claim: “… attaching the substantially flat top surface of the semiconductor chip and a top surface of a connection substrate to a temporary tape to place placing the semiconductor chip side by…” (emphasis added). The phrasing of the limitation is incorrect from a grammatical point of view. The limitation is suggested to be changed to either: 1. “… attaching the substantially flat top surface of the semiconductor chip and a top surface of a connection substrate to a temporary tape to place the semiconductor chip side by…” or 2. “… attaching the substantially flat top surface of the semiconductor chip and a top surface of a connection substrate to a temporary tape placing the semiconductor chip side by…”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-3, 6-9, 16, 20 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al, US 20180102322 A1 (Kang) in view of Lim, US 20210035961 A1 (Lim) in further view of Chen et al, US 20200343183 A1 (Chen ‘183).
Regarding claim 1; Kang teaches a method of fabricating a semiconductor package, the method comprising:
preparing a semiconductor chip (Kang: Annotated Fig (12B) shared in this OA: 120) having a bottom surface provided with a pillar pattern and a top surface provided with no pillar pattern;
placing the semiconductor chip (120) side by side with a connection substrate (110) provided with a conductive pad (112b) on a bottom surface of the connection substrate (110);
forming a molding layer (130) on the bottom surface of the connection substrate (110) and on the bottom surface of the semiconductor chip (120) to cover the pillar pattern and the conductive pad (112b);
forming a first redistribution substrate (First Redistribution Substrate) on a top surface of the connection substrate (110), the top surface of the semiconductor chip (120), and a top surface of the molding layer (130), the first redistribution substrate (First Redistribution Substrate) being directly in physical contact with the top surface of the semiconductor chip (120); and
performing a grinding process on a bottom surface of the molding layer to expose the pillar pattern and the conductive pad,
wherein an outer sidewall of the connection substrate (110) is vertically aligned with an outer sidewall of the first redistribution substrate (First Redistribution Substrate),
the placing of the semiconductor chip (120) side by side with the connection substrate (110) comprises attaching the top surface of the semiconductor chip (120) and the top surface of the connection substrate (110) to a temporary tape (Annotated Fig (12A) shared in this OA: 200), and the forming of the first redistribution substrate (Annotated Fig (12B) shared in this OA: First Redistribution Substrate) directly in physical contact with the top surface of the semiconductor chip (120) is done subsequently to removing the temporary tape (Annotated Fig (12A) shared in this OA: 200) from the top surface of the semiconductor chip (120) and the top surface of the connection substrate (110),
and the forming of the first redistribution substrate (Annotated Fig (12B) shared in this OA: First Redistribution Substrate) includes: forming a first dielectric layer (141) covering the top surface of the connection substrate (110), the top surface of the semiconductor chip (120), and the top surface of the molding layer (130);
forming a first seed pattern in the first dielectric layer to contact a connection pad of the connection substrate; and
forming a first redistribution pattern on the first seed pattern, wherein the connection pad is on the top surface of the connection substrate.
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Kang does not teach the semiconductor chip having a bottom surface provided with a pillar pattern and a top surface provided with no pillar pattern, forming a molding layer on the bottom surface of the connection substrate and on the bottom surface of the semiconductor chip to cover the pillar pattern, and performing a grinding process on a bottom surface of the molding layer to expose the pillar pattern and the conductive pad.
However, Lim teaches the semiconductor chip (Lim: Annotated Fig (5) shared in this OA: 120) having a bottom surface provided with a pillar pattern (122) and a top surface provided with no pillar pattern, forming a molding layer (130) on the bottom surface of the connection substrate (110) and on the bottom surface of the semiconductor chip (120) to cover the pillar pattern (122), and performing a grinding process (paragraph [0049] and claim 12 of Lim) on a bottom surface of the molding layer (130) to expose the pillar pattern (122) and the conductive pad (112, 113).
Kang and Lim are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kang by introducing the pillar pattern connection on the bottom of the chip as disclosed in Lim to make establishing connections with the chip easier leading to a more efficient production process of the device.
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Kang in view of Lim does not teach forming a first seed pattern in the first dielectric layer to contact a connection pad of the connection substrate; and forming a first redistribution pattern on the first seed pattern, wherein the connection pad is on the top surface of the connection substrate.
Chen ‘183 teaches forming a first seed pattern (Chen ‘183: Annotated Fig (10) shared in this OA: 134s) in the first dielectric layer (132a) to contact a connection pad (124) of the connection substrate (substrate containing 124, 122); and forming a first redistribution pattern (134) on the first seed pattern (134s), wherein the connection pad (124) is on the top surface of the connection substrate (substrate containing 124, 122).
Kang in view of Lim and Chen ‘183 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kang in view of Lim by using the seed layer disclosed in Chen ‘183 to improve the mechanical bond strength and the conductivity of the electrical connections in the device leading to a more reliable device.
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Regarding claim 2; Kang in view of Lim in view of Chen ‘183 teaches all the limitations of the method of claim 1.
Further, Kang teaches wherein the forming of the first redistribution substrate (Kang: Annotated Fig (12B) shared in this OA: First Redistribution Substrate) is performed after the performing of the grinding process ([0090]: “Referring to FIG. 12B, then, the insulating layer 141 may be formed. Then, a grinding process may be performed on the interconnection members 125 as well as the insulating layer 141 to form a flat surface.”).
Regarding claim 3; Kang in view of Lim in further view of Chen ‘183 teaches all the limitations of the method of claim 1.
However, Kang does not teach further comprising forming a second redistribution substrate on a bottom surface of the exposed pillar pattern and on a bottom surface of the exposed conductive pad.
Lim teaches further comprising forming a second redistribution substrate (Lim: Annotated Fig (5) shared in this OA: 101) on a bottom surface of the exposed pillar pattern (122) and on a bottom surface of the exposed conductive pad (Conductive Pad).
Kang and Lim are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kang by using the second redistribution substrate as disclosed in Lim to make establishing electrical connections with the device components easier leading to a more efficient device production process.
Regarding claim 6; Kang in view of Lim in further view of Chen ‘183 teaches all the limitations of the method of claim 1.
Further, Kang teaches further comprising: allowing a temporary tape (Kang: Annotated Fig (12A) shared in this OA: 200) to be directly attached to the semiconductor chip (Annotated Fig (12B) shared in this OA: 120) and the connection substrate (110); and after the forming of the molding layer (130), removing the temporary tape Annotated Fig (12A) shared in this OA: 200) to expose the top surface of the connection substrate (110) and the top surface of the semiconductor chip (120).
Regarding claim 7; Kang in view of Lim in further view of Chen ‘183 teaches all the limitations of the method of claim 1.
Further, Kang teaches wherein the first redistribution substrate (Kang: Annotated Fig (12B) shared in this OA: First Redistribution Substrate) is directly in physical contact with the top surface of the connection substrate (110) and with the top surface of the molding layer (130).
Regarding claim 8; Kang in view of Lim in further view of Chen ‘183 teaches all the limitations of the method of claim 1.
Further, Kang teaches wherein the molding layer (Kang: Annotated Fig (12B) shared in this OA: 130) extends between the connection substrate (110) and the semiconductor chip (120), and the top surface of the molding layer (130) is coplanar with the top surface of the connection substrate (110) and with the top surface of the semiconductor chip (120).
Regarding claim 9; Kang in view of Lim in further view of Chen ‘183 teaches all the limitations of the method of claim 1.
Further, Kang teaches wherein the connection substrate (Kang: Annotated Fig (12B) shared in this OA: 110) has a hole (hole filled with the chip 120), the placing of the semiconductor chip (120) side by side with the connection substrate (110) includes providing the semiconductor chip (120) in the hole of the connection substrate (110), and an angle between the top surface of the connection substrate (110) and a sidewall of the hole is in a range from about 85 degrees to about 95 degrees (by examining the angle between the top surface of the connection substrate 110 and a sidewall of the hole that contains the chip 120 in Fig (12B) it appears that the angle is a right angle and thus is in the recited range).
Regarding claim 16; Kang teaches a method of fabricating a semiconductor package, the method comprising:
preparing a semiconductor chip (Kang: Annotated Fig (12B) shared in this OA: 120) a bottom surface and a top surface (see top and bottom surfaces of 120); and
the bottom surface provided with a bump including a pillar pattern, and the top surface provided with no pillar pattern;
preparing a connection substrate (110) provided with a conductive pad (112b) on a bottom surface of the connection substrate (110), the connection substrate (110) having a hole (the hole in which the chip 120 is placed) that penetrates the connection substrate (110);
placing the semiconductor chip (120) and the connection substrate (110) on a bottom surface of a temporary tape (Annotated Fig (12A): 200),
the semiconductor chip (120) being in the hole of the connection substrate (110) and being in physical contact with the bottom surface of the temporary tape (200);
forming a molding layer (130) on the bottom surface of the connection substrate (110) and on the bottom surface of the semiconductor chip (120), the molding layer (130) extending between the connection substrate (110) and the semiconductor chip (120) and physically contacting the temporary tape (200);
removing the temporary tape (200) to expose a top surface of the connection substrate (110), the top surface of the semiconductor chip (120), and a top surface of the molding layer (130);
forming a first redistribution substrate (Kang: Annotated Fig (12B) shared in this OA: First Redistribution Substrate) on the top surface of the connection substrate (110), the top surface of the semiconductor chip (120), and the top surface of the molding layer (130) subsequent to removing of the temporary tape (Annotated Fig (12A) shared in this OA: 200),
the first redistribution substrate (Annotated Fig (12B): First Redistribution Substrate) being directly in physical contact with the top surface of the semiconductor chip (120);
performing a grinding process on a bottom surface of the molding layer to expose the pillar pattern and the conductive pad;
forming a second redistribution substrate on the exposed pillar pattern and the exposed conductive pad; and
forming a solder ball on a bottom surface of the second redistribution substrate, and
and the forming of the first redistribution substrate (Annotated Fig (12B) shared in this OA: First Redistribution Substrate) includes: forming a first dielectric layer (141) covering the top surface of the connection substrate (110), the top surface of the semiconductor chip (120), and the top surface of the molding layer (130);
forming a first seed pattern in the first dielectric layer to contact a connection pad of the connection substrate; and forming a first redistribution pattern on the first seed pattern, wherein the connection pad is on the top surface of the connection substrate.
Kang does not teach the bottom surface of the semiconductor chip provided with a bump including a pillar pattern; forming a molding layer on the bottom surface of the connection substrate and on the bottom surface of the semiconductor chip to cover a bottom surface of the bump and a bottom surface of the conductive pad, and performing a grinding process on a bottom surface of the molding layer to expose the pillar pattern and the conductive pad; and forming a solder ball on a bottom surface of the second redistribution substrate.
However, Lim teaches the bottom surface of the semiconductor chip (Lim: Annotated Fig (5) shared in this OA: 120) provided with a bump (Bump) including a pillar pattern (122), forming a molding layer (130) on the bottom surface of the connection substrate (110) and on the bottom surface of the semiconductor chip (120) to cover a bottom surface of the bump (Bump) and a bottom surface of the conductive pad (Conductive Pad), and performing a grinding process (paragraph [0049] and claim 12 of Lim) on a bottom surface of the molding layer (130) to expose the pillar pattern (122) and the conductive pad (112, 113); and forming a solder ball (Solder Ball) on a bottom surface of the second redistribution substrate (101).
Kang and Lim are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kang by introducing the pillar pattern connection on the bottom of the chip as disclosed in Lim to make establishing connections with the chip easier leading to a more efficient production process of the device.
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Kang in view of Lim does not teach forming a first seed pattern in the first dielectric layer to contact a connection pad of the connection substrate; and forming a first redistribution pattern on the first seed pattern, wherein the connection pad is on the top surface of the connection substrate.
Chen ‘183 teaches forming a first seed pattern (Chen ‘183: Annotated Fig (10) shared in this OA: 134s) in the first dielectric layer (132a) to contact a connection pad (124) of the connection substrate (substrate containing 124, 122); and forming a first redistribution pattern (134) on the first seed pattern (134s), wherein the connection pad (124) is on the top surface of the connection substrate (substrate containing 124, 122).
Kang in view of Lim and Chen ‘183 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kang in view of Lim by using the seed layer disclosed in Chen ‘183 to improve the mechanical bond strength and the conductivity of the electrical connections in the device leading to a more reliable device.
Regarding claim 20; Kang in view of Lim in further view of Chen ‘183 teaches all the limitations of the method of claim 16.
Further, Kang teaches wherein the hole (Kang: Annotated Fig (12B) shared in this OA: the hole in which the chip (120) is placed) of the connection substrate (110) exposes an inner sidewall of the connection substrate (110), and an angle between the inner sidewall and the top surface of the connection substrate is in a range from about 85 degrees to about 95 degrees (by examining the angle between the top surface of the connection substrate 110 and a sidewall of the hole that contains the chip 120 in Fig (12B) it appears that the angle is a right angle and thus is in the recited range).
Regarding claim 23; Kang in view of Lim in further view of Chen ‘183 teaches all the limitations of the method of claim 1.
However, Kang does not teach wherein the preparing of the semiconductor chip prepares the semiconductor provided with a bump including the pillar pattern on the bottom surface of the semiconductor chip; the forming of the molding layer forms the molding layer on the bottom surface of the connection substrate and on the bottom surface of the semiconductor chip to cover the bump including the pillar pattern and the conductive pad; and the performing of the grinding process performs the grinding process on the bottom surface of the molding layer to expose the bump including the pillar pattern and the conductive pad.
Lim teaches wherein the preparing of the semiconductor chip (Lim: Annotated Fig (5) shared in this OA: 120) prepares the semiconductor provided with a bump (Bump) including the pillar pattern on the bottom surface of the semiconductor chip (120); the forming of the molding layer (130) forms the molding layer on the bottom surface of the connection substrate (110) and on the bottom surface of the semiconductor chip (120) to cover the bump (Bump) including the pillar pattern and the conductive pad (Conductive Pad); and the performing of the grinding process performs the grinding process on the bottom surface of the molding layer (130) to expose the bump (Bump) including the pillar pattern and the conductive pad (Conductive Pad).
Kang and Lim are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kang by introducing the second redistribution layer disclosed in Lim to make establishing electrical connections with the device easier leading to a more efficient device construction process).
Claims 4 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al, US 20180102322 A1 (Kang) in view of Lim, US 20210035961 A1 (Lim) in further view of Chen et al, US 20200343183 A1 (Chen ‘183) in further view of Chen et al, US 20180151500 A1 (Chen ‘500)
Regarding claim 4; Kang in view of Lim in further view of Chen ‘183 teaches all the limitations of claim 3.
However, Kang in view of Lim in further view of Chen ‘183 does not teach wherein the second redistribution substrate includes: a plurality of second seed patterns directly coupled to the pillar pattern and the conductive pad; and a plurality of second redistribution patterns formed on bottom surfaces of the plurality of second seed patterns.
Chen ‘500 teaches that the method includes: a plurality of second seed patterns (Chen ‘500: Annotated Fig (1L): 260) directly coupled to the pillar pattern (120) and the conductive pad (180); and a plurality of second redistribution patterns (Second Redistribution Patterns) formed on bottom surfaces of the plurality of second seed patterns (260).
Kang in view of Lim in further view of Chen ‘183 and Chen ‘500 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kang in view of Lim in further view of Chen ‘183 by introducing the seeding of connection pads from Chen ‘500 to strengthen the mechanical properties of the electric connection pads.
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Regarding claim 19; Kang in view of Lim in further view of Chen ‘183 teach all the limitations of the method of claim 16.
However, Kang does not teach wherein the forming of the second redistribution substrate includes: forming a second dielectric layer that covers a grinded bottom surface of the molding layer; forming a plurality of second seed patterns in physical contact with a bottom surface of the exposed pillar pattern and with the bottom surface of the exposed conductive pad; and forming a plurality of second redistribution patterns on bottom surfaces of the plurality of second seed patterns.
Lim teaches wherein the forming of the second redistribution substrate (Lim: Annotated Fig (5) shared in this OA: 101) includes: forming a second dielectric layer (141) that covers a grinded bottom surface of the molding layer (130).
Kang and Lim are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kang by constructing the second redistribution layer as disclosed in Lim to make establishing electrical connections with the device easier leading to a more efficient device construction process.
However, Kang in view of Lim in further view of Chen ‘183 does not teach forming a plurality of second seed patterns in physical contact with a bottom surface of the exposed pillar pattern and with the bottom surface of the exposed conductive pad; and forming a plurality of second redistribution patterns on bottom surfaces of the plurality of second seed patterns.
Chen ‘500 teaches forming a plurality of second seed patterns (Chen ‘500: Annotated Fig (1L) shared in this OA: 260) in physical contact with a bottom surface of the exposed pillar pattern (120) and with the bottom surface of the exposed conductive pad (180); and forming a plurality of second redistribution patterns (Second Redistribution Patterns) on bottom surfaces of the plurality of second seed patterns (260).
Kang in view Lim in further view of Chen ‘183 and Chen ‘500 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kang in view of Lim in further view of Chen ‘183 introducing the seeding of connection pads from Chen ‘500 to increase the mechanical strength and electrical conduction properties of the electric connection pads.
Claims 10-12, 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al, US 20180102322 A1 (Kang) in view of Lim, US 20210035961 A1 (Lim) in further view of Chen et al, US 20200343183 A1 (Chen ‘183) in further view of Yap, US 20170077072 A1 (Yap).
Regarding claim 10; Kang teaches a method of fabricating a semiconductor package, the method comprising:
preparing a semiconductor chip (Kang: Annotated Fig (12B) shared in this OA: 120) having a bottom surface and a substantially flat top surface (see top and bottom surfaces of 120),
the bottom surface provided with a bump including a pillar pattern, and the substantially flat top surface provided with no pillar pattern;
attaching the substantially flat top surface of the semiconductor chip (120) and a top surface of a connection substrate (110) to a temporary tape (200) placing the semiconductor chip (120) side by side with a connection substrate (110) wherein the connection substrate is provided with a conductive pad (112b) on a bottom surface of the connection substrate (110);
forming a molding layer (130) on the bottom surface of the connection substrate (110) and on the bottom surface of the semiconductor chip (120) to cover the bump and the conductive pad (112b);
removing the temporary tape (Kang: Annotated Fig (12A) shared in this OA: 200) from the substantially flat top surface of the semiconductor chip (120) and the top surface of the connection substrate (110);
forming, subsequent to removing the temporary tape (200), a first redistribution substrate (First Redistribution Substrate) in direct physical contact with the top surface of the connection substrate (110), the substantially flat top surface of the semiconductor chip (120), and a top surface of the molding layer (130), and
performing a grinding process on a bottom surface of the molding layer to expose the pillar pattern and the conductive pad,
wherein the connection substrate (110) includes a plurality of connection pads (112a) on the top surface of the connection substrate (110),
wherein the placing of the semiconductor chip (120) is placed side by side with the connection substrate (110) by attaching the top surface of the semiconductor chip (120) and the top surface of the connection substrate (110) to a temporary tape (200), and
wherein the forming of the first redistribution substrate (Annotated Fig (12B) shared in this OA: First Redistribution Substrate) includes: forming a first dielectric layer (141) covering the top surface of the connection substrate (110), the top surface of the semiconductor chip (120), and the top surface of the molding layer (130);
forming a first seed pattern in the first dielectric layer to contact a connection pad of the connection substrate;
forming a first seed pattern directly coupled to each of the plurality of connection pads; and
forming a first redistribution pattern on the first seed pattern.
Kang in view of Lim does not teach forming a first seed pattern in the first dielectric layer to contact a connection pad of the connection substrate; forming a first seed pattern directly coupled to each of the plurality of connection pads; and forming a first redistribution pattern on the first seed pattern.
Chen ‘183 teaches forming a first seed pattern (Chen ‘183: Annotated Fig (10) shared in this OA: 134s) in the first dielectric layer (132a) to contact a connection pad (124) of the connection substrate (substrate containing 124, 122); forming a first seed pattern (134s) directly coupled to each of the plurality of connection pads (124); and forming a first redistribution pattern (134) on the first seed pattern (134s).
Kang in view of Lim and Chen ‘183 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kang in view of Lim by using the seed layer disclosed in Chen ‘183 to improve the mechanical bond strength and the conductivity of the electrical connections in the device leading to a more reliable device.
However, Kang in view of Lim in further view of Chen ‘183 does not teach to cover the bump and the conductive pad with the molding material.
Yap teaches to cover the bump (Yap: Fig (4): 60) and the conductive pad (68). Kang in view of Lim in further view of Chen ‘183 and Yap are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kang in view of Lim in further view Chen ‘183 by including the covering of the bump as disclosed in Yap to strengthen the structure of the connection layers leading to a more reliable device.
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Regarding claim 11; Kang in view of Lim in further view of Chen ‘183 in further view of Yap teaches all the limitations of the method of claim 10.
However, Kang does not teach wherein the bump further includes a solder pattern on a bottom surface of the pillar pattern.
Lim teaches wherein the bump (Lim: Annotated Fig (5) shared in this OA: Bump) further includes a solder pattern (Solder Ball) on a bottom surface of the pillar pattern (122).
Kang and Lim are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kang by introducing the solder pattern at the bottom surface of the pillar pattern as disclosed in Lim to improve the strength of the electrical connection in the device leading to a more reliable device.
However, Kang in view of Lim in further view of Chen ‘183 does not teach the performing of the grinding process includes removing the solder pattern.
Yap teaches the performing of the grinding process (Yap: [0026]) includes removing the solder pattern (60).
Kang in view of Lim in further view of Chen ‘183 and Yap are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kang in view of Lim in further view of Chen ‘183 by performing the grinding process such that it removes the solder pattern as disclosed in Yap to generate a fresh surface of solder to improve the bonding process and the electrical connections in the device leading to a more reliable device.
Regarding claim 12; Kang in view of Lim in further view of Chen ‘183 in further view of Yap teaches all the limitations of the method of claim 10.
Further, Kang teaches wherein a width of the connection substrate (Kang: Annotated Fig (12B) shared in this OA: 110) is substantially the same as a width of the first redistribution substrate (First Redistribution Substrate).
Regarding claim 15; Kang in view of Lim in further view of Chen ‘183 in further view of Yap teaches all the limitations of the method of claim 10.
Further, Kang teaches wherein the forming of the molding layer (Kang: Annotated Fig (12B): 130) further includes allowing the molding layer (130) to extend between the connection substrate (110) and the semiconductor chip (120) and to contact the temporary tape (Annotated Fig (12A): 200).
Regarding claim 17; Kang in view of Lim in further view of Chen ‘183 teaches all the limitations of the method of claim 16.
However, Kang does not teach wherein the bump further includes a solder pattern on a bottom surface of the pillar pattern, and the performing of the grinding process includes removing the solder pattern.
Lim teaches wherein the bump further includes a solder pattern (Lim: Annotated Fig (5) shared in this OA: Solder Ball) on a bottom surface of the pillar pattern (122).
However, while Kang teaches a grinding process they fail to teach the performing of the grinding process includes removing the solder pattern.
Yap teaches the performing of the grinding process (Yap: [0026]) includes removing the solder pattern (60).
Kang in view of Lim in further view of Chen ‘183 and Yap are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kang in view of Lim in further view of Chen ‘183 by using the grinding process which includes the removal of the solder pattern as disclosed in Yap to enhance the ability of the chip to bond with other layers by generating a fresh solder bonding surface.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kang et al, US 20180102322 A1 (Kang) in view of Lim, US 20210035961 A1 (Lim) in further view of Yap, US 20170077072 A1 (Yap) in further view of Wu, US 20210098421 A1 (Wu).
Regarding claim 13; Kang in view of Lim in further view of Chen ‘183 in further view of Yap teaches all the limitations of the method of claim 10.
However, Kang in view of Lim in further view of Chen ‘183 in further view of Yap does not teach further comprising forming a second redistribution substrate, wherein the forming of the second redistribution substrate includes: forming a plurality of second seed patterns in direct contact with the exposed pillar pattern and the exposed conductive pad; and forming a plurality of second redistribution patterns on bottom surfaces of the plurality of second seed patterns.
Wu teaches further comprising forming a second redistribution substrate (Wu: Fig (1): 110), wherein the forming of the second redistribution substrate (110) includes: forming a plurality of second seed patterns (112b, [0022]) in direct contact with the exposed pillar pattern (120) and the exposed conductive pad (112); and forming a plurality of second redistribution patterns (110) on bottom surfaces of the plurality of second seed patterns ([0022]).
Kang in view of Lim in further view of Chen ‘183 in further view of Yap and Wu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kang in view of Lim in further view of Chen ‘183 in further view of Yap by introducing the seeding of connection pads from Wu to strengthen the mechanical properties of the electric connection pads and improve their conductivity leading to a more reliable device.
Conclusion
Prior art made of record but not relied upon is considered pertinent to applicant’s disclosure:
Lee et al, US 20210090973 A1 (Lee); discloses seed layers in direct contact with connection pads and interconnection structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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