DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0384313 A1 to Cheng (hereinafter “Cheng ‘313” – previously cited reference).
Regarding claim 1, Cheng ‘313 discloses a semiconductor device comprising:
a first nanosheet device located on a substrate, wherein the first nanosheet device includes a first plurality of nanosheets (semiconductor device having first nanostructure 22 on substrate 110 and with a plurality of nanosheets 22a-22c; Fig. 3A; paragraphs [0037], [0055]), wherein each of the first plurality of nanosheets are surrounded by a first dipole, wherein the first dipole has a first concentration of a first dipole material (dipole material of high-k gate dielectric layers 210, 222 having doping concentration level of La2O3 and surrounding first nanostructure 22; Fig. 22; paragraphs [0022], [0084]), wherein the first dipole includes a first layer and a second layer, wherein the first nanosheet device further includes a first gate, wherein the first gate is in contact with the second layer (layers 210, 222 in contact with gate structure 200A; Fig. 17A); and
a second nanosheet device located on the substrate, wherein the second nanosheet device includes a second plurality of nanosheets (second nanostructure 22 on substrate 110 and with a plurality of nanosheets 22a-22c; Fig. 3A; paragraphs [0037], [0055]), wherein each of the second plurality of nanosheets are surrounded by a second dipole, wherein the second dipole has a second concentration of a second dipole material, wherein the first concentration and the second concentration are different (dipole material of high-k gate dielectric layers 221, 230, 240 in part having doping concentration level lower than layer 222 and surrounding second nanostructure 22; Fig. 22; paragraphs [0022], [0072], [0084]), wherein the second dipole includes a third layer and a fourth layer, wherein the second nanosheet device further includes a second gate, wherein the second gate is in contact with the fourth layer (layers 221, 230, 240 in contact with gate structure 200B; Fig. 17B).
Regarding claim 2, Cheng ‘313 discloses the semiconductor device of claim 1, wherein the first layer is a first interfacial layer surrounding each of the first plurality of nanosheets (first interfacial layer 210 surrounding first nanostructure 22; Fig. 22; paragraphs [0022], [0059], [0063]); and wherein the second layer is a first dielectric layer surrounding the first interfacial layer on each of the first plurality of nanosheets, wherein the first dipole material is located within the first interfacial layer and the first dielectric layer (dielectric layer 222 surrounding layer 210 on each of nanosheets 22a-22c with dipole material disposed within layers 210, 222; Fig. 22; paragraphs [0022]-[0023], [0059], [0066]).
Regarding claim 3, Cheng ‘313 discloses the semiconductor device of claim 2, wherein the third layer is a second interfacial layer surrounding each of the second plurality of nanosheets (second interfacial layer 240 surrounding second nanostructure 22; Fig. 22; paragraphs [0022], [0059], [0063]); wherein the fourth layer is a second dielectric layer surrounding the second interfacial layer on each of the second plurality of nanosheets, wherein the second dipole material is located within the second interfacial layer and the second dielectric layer (dielectric layer 230 surrounding layer 210 on each of nanosheets 22a-22c with dipole material disposed within layers 230, 240; Fig. 22; paragraphs [0022]-[0023], [0059], [0066]).
Regarding claim 4, Cheng ‘313 discloses the semiconductor device of claim 3, wherein an amount of the first dipole material located within the first interfacial layer and the first dielectric layer is different than an amount of second dipole material located within the second interfacial layer and the second dielectric layer (dipole material of layer 222 having doping concentration level lower than dipole material of layer 221; Fig. 22; paragraphs [0022], [0072], [0084]).
Regarding claim 5, Cheng ‘313 discloses the semiconductor device of claim 4, wherein the first dipole material and the second dipole material are comprised of different dipole materials (dipole material La2O3 of layer 222 may be different than that of dipole material of layer 221; paragraphs [0024], [0072]).
Regarding claim 6, Cheng ‘313 discloses the semiconductor device of claim 4, wherein the first dipole material and the second dipole material are comprised of the same dipole materials (dipole material La2O3 of layer 222 may be same as that of dipole material of layer 221; paragraphs [0024], [0072]).
Regarding claim 7, Cheng ‘313 discloses the semiconductor device of claim 4, wherein the first dipole material and the second dipole material are comprised of different amounts of the same dipole material (dipole material of layer 222 may have same doping material at concentration level lower than dipole material of layer 221; Fig. 22; paragraphs [0022], [0024], [0072], [0084]).
Regarding claim 8, Cheng ‘313 discloses the semiconductor device of claim 1, wherein the first dipole material is comprised of a dipole material selected from a group consisting of La2O3, Y2O3, Al2O3, or a combination thereof (dipole material of layer 222 may be La2O3; paragraphs [0024], [0072]).
Regarding claim 9, Cheng ‘313 discloses the semiconductor device of claim 1, wherein the second dipole material is comprised of a dipole material selected from a group consisting of La2O3, Y2O3, Al2O3, or a combination thereof (dipole material of layer 222 may be La2O3; paragraphs [0024], [0072]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-16 are rejected under 35 U.S.C. 103 as being obvious over US 2021/0391225 A1 to Cheng et al. (hereinafter “Cheng ‘225” – previously cited reference) in view of Cheng ‘313.
Regarding claim 10, Cheng ‘225 discloses a semiconductor device comprising:
a first nanosheet device located on a substrate, wherein the first nanosheet device includes a first plurality of nanosheets (semiconductor device 100 having NFET 102N1 on substrate 106 and comprising a plurality of nano-scale layers of gate structure 112N1; Figs. 1A-1B; paragraphs [0028], [0036]), wherein each of the first plurality of nanosheets are surrounded by a first dipole, wherein the first dipole has a first concentration of a first dipole material (layers of gate structure 112N1 surrounded by dipole 129N1 with first dopant material and concentration level; Figs. 1A-1B; paragraphs [0038]-[0039]), wherein the first dipole is located around three sides of the each of the first plurality of nanosheets, wherein the first dipole includes a first layer and a second layer (dipole 129N1 disposed around three sides of other layers of gate structure 112N1 and includes two opposing side layers; Fig. 1B), wherein the first nanosheet device further includes a first gate, wherein the first gate is in contact with the second layer (gate structure 112N1 in contact with two opposing side layers; Fig. 1B);
a second nanosheet device located on the substrate, wherein the second nanosheet device includes a second plurality of nanosheets (NFET 102N2 on substrate 106 and comprising a plurality of nano-scale layers of gate structure 112N2; Figs. 1A-1B; paragraphs [0028], [0036]), wherein each of the second plurality of nanosheets are surround by a second dipole, wherein the second dipole has a second concentration of a second dipole material, wherein the first concentration and the second concentration are different (layers of gate structure 112N2 surrounded by dipole 129N2 with second dopant material and concentration level different from that of first dopant; Figs. 1A-1B; paragraphs [0038]-[0039]), wherein the second dipole is located around three sides of the each of the second plurality of nanosheets, wherein the second dipole includes a third layer and a fourth layer (dipole 129N2 disposed around three sides of other layers of gate structure 112N2 and includes two opposing side layers; Fig. 1B), wherein the second nanosheet device further includes a second gate, wherein the second gate is in contact with the fourth layer (gate structure 112N2 in contact with two opposing side layers; Fig. 1B);
a third nanosheet device located on the substrate, wherein the third nanosheet device includes a third plurality of nanosheets (NFET 102N3 on substrate 106 and comprising a plurality of nano-scale layers of gate structure 112N3; Figs. 1A-1B; paragraphs [0028], [0036]), wherein each of the second plurality of nanosheets are surrounded by a third dipole, wherein the third dipole has a third concentration of a third dipole material, wherein the third concentration is different than the first concentration and the second concentration (layers of gate structure 112N2 surrounded by La2O3 oxide 127 of adjacent La2O3 dipole 129N3 with third concentration level different from that of first dopant; Figs. 1A-1B; paragraphs [0038]-[0039], [0043]), wherein the third dipole is located around three sides of the each of the third plurality of nanosheets, wherein the third dipole includes a firth layer and a sixth layer (dipole 129N3 disposed around three sides of other layers of gate structure 112N3 and includes two opposing side layers; Fig. 1B), wherein the third nanosheet device further includes a third gate, wherein the third gate is in contact with the sixth layer (gate structure 112N3 in contact with two opposing side layers; Fig. 1B); and
a fourth nanosheet device located on the substrate, wherein the fourth nanosheet device includes a fourth plurality of nanosheets, wherein a dipole does not surround each of the fourth plurality of nanosheets (NFET 102N4 on substrate 106 and comprising a plurality of nano-scale layers of gate structure 112N3, where NFET 102N4 does not comprise a dipole; Figs. 1A-1B; paragraphs [0028], [0036], [0043]).
Cheng ‘225 fails to disclose wherein the first dipole is located around four sides of the each of the first plurality of nanosheets; wherein the second dipole is located around four sides of the each of the second plurality of nanosheets; and wherein the third dipole is located around four sides of the each of the third plurality of nanosheets.
However, Cheng ‘313 discloses wherein the first dipole is located around four sides of the each of the first plurality of nanosheets (dipole material of high-k gate dielectric layers 222, 240 surrounding four sides of one of plurality of nanostructures 22; Fig. 22; paragraphs [0022], [0050], [0084]), wherein the first dipole includes a first layer and a second layer, wherein the first nanosheet device further includes a first gate, wherein the first gate is in contact with the second layer (layers 222, 240 in contact with gate structure 200A; Fig. 17A); wherein the second dipole is located around four sides of the each of the second plurality of nanosheets (dipole material of high-k gate dielectric layers 221, 240 surrounding four sides of one of plurality of nanostructures 22; Fig. 22; paragraphs [0022], [0050], [0084]), wherein the second dipole includes a third layer and a fourth layer, wherein the second nanosheet device further includes a second gate, wherein the second gate is in contact with the fourth layer (layers 221, 240 in contact with gate structure 200B; Fig. 17A); wherein the third dipole is located around four sides of the each of the third plurality of nanosheets (dipole material of high-k gate dielectric layers 220, 240 surrounding four sides of one of plurality of nanostructures 22; Fig. 22; paragraphs [0022], [0050], [0084]), wherein the third dipole includes a firth layer and a sixth layer, wherein the third nanosheet device further includes a third gate, wherein the third gate is in contact with the sixth layer (layers 220, 240 in contact with gate structure 200C; Fig. 17A);
Cheng ‘225 and Cheng ‘313 are both considered to be analogous to the claimed invention because they are in the same field of gate-all-around devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheng ‘225to incorporate the teaching of Cheng ‘313 in order to potentially provide enhanced gate control and electrostatic tuning, improved threshold voltage modulation, and reduced leakage current.
Regarding claim 11, Cheng ‘225 in view of Cheng ‘313 discloses the semiconductor device of claim 10. Cheng ‘225 further discloses a first interfacial layer surrounding each of the first plurality of nanosheets; a first dielectric layer surrounding the first interfacial layer on each of the first plurality of nanosheets, wherein the first dipole material is located within the first interfacial layer and the first dielectric layer (La2O3-doped oxide layer 127 surrounding layers 112N1 and La2O3-doped HK dielectric layer 128N1 surrounding layer 127; paragraphs [0038]-[0040], [0068]).
Cheng ‘225 fails to disclose wherein the first layer is a first interfacial layer surrounding each of the first plurality of nanosheets; and wherein the second layer is a first dielectric layer surrounding the first interfacial layer on each of the first plurality of nanosheets, wherein the first dipole material is located within the first interfacial layer and the first dielectric layer.
However, Cheng ‘313 discloses wherein the first layer is a first interfacial layer surrounding each of the first plurality of nanosheets (first interfacial layer 210 surrounding first nanostructure 22; Fig. 22; paragraphs [0022], [0050], [0059], [0063]); and wherein the second layer is a first dielectric layer surrounding the first interfacial layer on each of the first plurality of nanosheets, wherein the first dipole material is located within the first interfacial layer and the first dielectric layer (dielectric layer 222 surrounding layer 210 on each of nanosheets 22a-22c with dipole material disposed within layers 210, 222; Fig. 22; paragraphs [0022]-[0023], [0050], [0059], [0066]).
Cheng ‘225 and Cheng ‘313 are both considered to be analogous to the claimed invention because they are in the same field of gate-all-around devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheng ‘225 to incorporate the teaching of Cheng ‘313 in order to potentially provide improved interface quality and reduced trap density, enhanced channel mobility, and suppression of short-channel effects.
Regarding claim 12, Cheng ‘225 in view of Cheng ‘313 discloses the semiconductor device of claim 11. Cheng ‘225 further discloses a second interfacial layer surrounding each of the second plurality of nanosheets; a second dielectric layer surrounding the second interfacial layer on each of the second plurality of nanosheets, wherein the second dipole material is located within the second interfacial layer and the second dielectric layer (La2O3-doped oxide layer 127 surrounding layers 112N2 and La2O3-doped HK dielectric layer 128N2 surrounding layer 127; paragraphs [0038]-[0040], [0068]).
Cheng ‘225 fails to disclose wherein the third layer is a second interfacial layer surrounding each of the second plurality of nanosheets; wherein the fourth layer is a second dielectric layer surrounding the second interfacial layer on each of the second plurality of nanosheets, wherein the second dipole material is located within the second interfacial layer and the second dielectric layer.
However, Cheng ‘313 discloses wherein the third layer is a second interfacial layer surrounding each of the second plurality of nanosheets (second interfacial layer 210 surrounding second nanostructure 22; Fig. 22; paragraphs [0022], [0050], [0059], [0063]); wherein the fourth layer is a second dielectric layer surrounding the second interfacial layer on each of the second plurality of nanosheets, wherein the second dipole material is located within the second interfacial layer and the second dielectric layer (dielectric layer 221 surrounding layer 210 on each of nanosheets 22a-22c with dipole material disposed within layers 210, 221; Fig. 22; paragraphs [0022]-[0023], [0050], [0059], [0066]).
Cheng ‘225 and Cheng ‘313 are both considered to be analogous to the claimed invention because they are in the same field of gate-all-around devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheng ‘225 to incorporate the teaching of Cheng ‘313 in order to potentially provide improved interface quality and reduced trap density, enhanced channel mobility, and suppression of short-channel effects.
Regarding claim 13, Cheng ‘225 in view of Cheng ‘313 discloses the semiconductor device of claim 12. Cheng ‘225 further discloses a third interfacial layer surrounding each of the third plurality of nanosheets; a third dielectric layer surrounding the third interfacial layer on each of the third plurality of nanosheets, wherein the third dipole material is located within the third interfacial layer and the third dielectric layer (La2O3-doped oxide layer 127 surrounding layers 112N3 and La2O3-doped HK dielectric layer 128N3 surrounding layer 127; paragraphs [0038]-[0040], [0068]).
Cheng ‘225 fails to disclose wherein the fifth layer is a third interfacial layer surrounding each of the third plurality of nanosheets; wherein the sixth layer is a third dielectric layer surrounding the third interfacial layer on each of the third plurality of nanosheets, wherein the third dipole material is located within the third interfacial layer and the third dielectric layer.
However, Cheng ‘313 discloses wherein the fifth layer is a third interfacial layer surrounding each of the third plurality of nanosheets (third interfacial layer 210 surrounding third nanostructure 22; Fig. 22; paragraphs [0022], [0050], [0059], [0063]); wherein the sixth layer is a third dielectric layer surrounding the third interfacial layer on each of the third plurality of nanosheets, wherein the third dipole material is located within the third interfacial layer and the third dielectric layer (dielectric layer 220 surrounding layer 210 on each of nanosheets 22a-22c with dipole material disposed within layers 210, 220; Fig. 22; paragraphs [0022]-[0023], [0050], [0059], [0066]).
Cheng ‘225 and Cheng ‘313 are both considered to be analogous to the claimed invention because they are in the same field of gate-all-around devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheng ‘225 to incorporate the teaching of Cheng ‘313 in order to potentially provide improved interface quality and reduced trap density, enhanced channel mobility, and suppression of short-channel effects.
Regarding claim 14, Cheng ‘225 in view of Cheng ‘313 discloses the semiconductor device of claim 13. Cheng ‘225 further discloses wherein an amount of the first dipole material located within the first interfacial layer and the first dielectric layer is different than an amount of second dipole material located within the second interfacial layer and the second dielectric layer (dipole 129N2 with second dopant material and concentration level different from that of first dopant of dipole 129N1; Figs. 1A-1B; paragraphs [0038]-[0039]).
Regarding claim 15, Cheng ‘225 in view of Cheng ‘313 discloses the semiconductor device of claim 14. Cheng ‘225 further discloses wherein an amount of the first dipole material located within the first interfacial layer and the first dielectric layer is different than an amount of third material located within the third interfacial layer and the third dielectric layer (dipole 129N1 with first dopant material and concentration level different from that of third dopant of dipole 129N3; Figs. 1A-1B; paragraphs [0038]-[0039], [0041], [0043], [0046]).
Regarding claim 16, Cheng ‘225 in view of Cheng ‘313 discloses the semiconductor device of claim 15. Cheng ‘225 further discloses wherein an amount of the third dipole material located within the third interfacial layer and the third dielectric layer is different than an amount of second dipole material located within the second interfacial layer and the second dielectric layer (dipole 129N3 with third dopant material and concentration level different from that of second dopant of dipole 129N2; Figs. 1A-1B; paragraphs [0038]-[0039], [0041], [0043], [0046]).
Response to Arguments
Applicant's arguments filed August 13, 2025 have been fully considered. Applicant in part submitted amendments to independent claims with corresponding arguments that these amended claims are allowable over the references cited and that Cheng ‘313 does not disclose certain elements of original claim 1.
Specifically, Applicant asserts that Cheng ‘313 does not disclose concentrations differing from device to device, but only that the concentration of the dopant differs within layers around a nanosheet. However, as discussed during the Applicant-Initiated Interview of August 7, 2025, Cheng ’313 discloses different dopant concentrations for each of the dielectric layers in each of the respective gate structures 200A-200F which, beyond the paragraphs cited in the Office Action, is further supported by paragraph [0075] of Cheng ‘313 which states that “varying levels of dopant concentration to the first gate dielectric layers 222, 221, 220, which corresponds to varying threshold voltages of the gate structures 200A-200F.” This supports an interpretation that dopant concentration differs between devices. Therefore, this argument is not persuasive.
Finally, Examiner agrees that amended claims 1 and 10 overcome the previous 35 USC 102 rejections using Cheng ‘225 and Cheng ‘313. However, after additional search, new grounds of rejection under 35 USC 102 and 35 USC 103 have been presented related to an alternative interpretation of Cheng ‘225 and necessitated by Applicant’s amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818