DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 6-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Darwish et al. (US 20110254088 A1, hereinafter Darwish‘088).
Regarding independent claim 1, Darwish‘088 teaches, “A semiconductor device (fig. 3A-3C; ¶¶ [0053]-[0083]), comprising:
a first electrode (102, fig. 3A, reference sign 102 shown in fig. 1A);
a second electrode (103, reference sign 103 shown in fig. 1A);
a first semiconductor region (110) of a first conductivity type (N-) that is Located between the first electrode (102) and the second electrode (103) in a first direction from the first electrode toward the second electrode (vertical direction) and has a first portion (portion of element 110 adjacent to element 100) and a plurality of second portions (portion of element 110 above the first portion),
the first portion being electrically connected to the first electrode (102) and extending in a second direction (horizontal direction) intersecting the first direction,
the second portion extending from the first portion toward the second electrode (103) in the first direction;
a second semiconductor region (120, reference sign 120 shown in fig. 1A) of a second conductivity type (P) that is located between the second portion and the second electrode (103) in the first direction;
a third semiconductor region (140, reference sign 140 shown in fig. 1A) of the first conductivity type (N+) that is located between the second semiconductor region (120) and the second electrode (103) in the first direction and electrically connected to the second electrode (103);
a fourth semiconductor region (370, fig. 3A) of the second conductivity type (P) that is located between the second portion and the second electrode (103) in the first direction;
a third electrode (130) that is located between the first portion and the second electrode (103) in the first direction, is at least partially located parallel to the second portion in the second direction, and electrically connected to the second electrode (¶ 0056) and the fourth semiconductor region (370, ¶ 0067);
a first insulating region (marked as 132 in fig. 1A) that is located between the third electrode (130) and both the first portion and the second portion (110);
a gate electrode (150) that is located between the fourth semiconductor region (370) and the second electrode (103) in the first direction and located between the third electrode (130) and both the second semiconductor region (120) and the third semiconductor region (140) in the second direction; and
a second insulating region (gate insulating film) that electrically separates the gate electrode (150) from the first semiconductor region (110), the second semiconductor region (120), the third semiconductor region (140), the fourth semiconductor region (370, fig. 3A), and the second electrode (103),
wherein the fourth semiconductor region (370, fig. 3A) and the third electrode (130) are in contact with each other in the second direction (horizontal direction)”.
The limitation ‘in contact’ in the last line is broad and can be explained using broadest reasonable interpretation. During examination, the claims must be interpreted as broadly as their terms reasonably allow. In re American Academy of Science Tech Center, F.3d, 2004 WL 1067528 (Fed. Cir. May 13, 2004). In the instant case, ‘in contact’ can be explained as ‘in electrical/indirect contact’ or ‘in direct contact’. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements. As an example, referring to applicant’s fig. 1, the fourth semiconductor region (14) is in direct contact with third electrode (3). The term "indirect contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected with one or more intermediary conducting, insulating or semiconductor layers at the interface of the two elements. As an example, referring to applicant’s fig. 1, element 112 is in indirect contact with element 3 (via element 35).
Regarding claim 3, Darwish‘088 further teaches, “The semiconductor device according to claim 1, wherein the fourth semiconductor region (370) and the first insulating region (insulating region surrounding element 130) are adjacent to each other in the second direction”.
Regarding claim 6, Darwish‘088 further teaches, “The semiconductor device according to claim 1, wherein the second electrode (103) includes a contact portion (marked as ‘Recessed Contact 160’ in fig. 1A ) extending toward the first electrode (102) in the first direction, and the semiconductor device includes a fifth semiconductor region (marked as 122 in fig. 1A) located between the second semiconductor region (120) and the second electrode (103) in the first direction and between the contact portion (160) and both the second semiconductor region (120) and the third semiconductor region (140), and the fifth semiconductor region (122) has a second conductivity type (P+) impurity concentration higher than a second conductivity type impurity concentration (P) included in the second semiconductor region (120)”.
Regarding claim 7, Darwish‘088 further teaches, “The semiconductor device according to claim 6, wherein the fifth semiconductor region (122) is located between the third semiconductor region (140) and the contact portion (160) in the second direction”.
Regarding claim 8, Darwish‘088 further teaches, “The semiconductor device according to claim 6, wherein the fifth semiconductor region (122) is located between the third semiconductor region (140) and the contact portion (160) in a third direction (another horizontal direction) intersecting the first direction and the second direction”.
Claims 1 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Darwish‘088.
Regarding independent claim 1, Darwish‘088 teaches, “A semiconductor device (fig. 1A-1I; ¶¶ [0053]-[0133]), comprising:
a first electrode (102, fig. 1A);
a second electrode (103);
a first semiconductor region (110) of a first conductivity type (N) that is Located between the first electrode (102) and the second electrode (103) in a first direction (vertical direction) from the first electrode (102) toward the second electrode (103) and has a first portion and a plurality of second portions,
the first portion being electrically connected to the first electrode (102) and extending in a second direction (horizontal direction) intersecting the first direction,
the second portion extending from the first portion toward the second electrode (103) in the first direction;
a second semiconductor region (120) of a second conductivity type (P) that is located between the second portion and the second electrode (103) in the first direction;
a third semiconductor region (140) of the first conductivity type (n+) that is located between the second semiconductor region (120) and the second electrode (103) in the first direction and electrically connected to the second electrode (103);
a fourth semiconductor region (122’, fig. 1B) of the second conductivity type (P+) that is located between the second portion and the second electrode (103) in the first direction;
a third electrode (130) that is located between the first portion and the second electrode (103) in the first direction, is at least partially located parallel to the second portion in the second direction, and electrically connected to the second electrode (103) and the fourth semiconductor region (122’);
a first insulating region (132, fig. 1A) that is located between the third electrode (130) and both the first portion and the second portion (110);
a gate electrode (150) that is located between the fourth semiconductor region (122’) and the second electrode (103) in the first direction and located between the third electrode (130) and both the second semiconductor region (120) and the third semiconductor region (140) in the second direction; and
a second insulating region (152) that electrically separates the gate electrode (150) from the first semiconductor region (110), the second semiconductor region (120), the third semiconductor region (140), the fourth semiconductor region (122’), and the second electrode (103),
wherein the fourth semiconductor region (122’, fig. 1B) and the third electrode (130’) are in contact with each other in the second direction (horizontal direction)”.
The limitation ‘in contact’ in the last line is broad and can be explained using broadest reasonable interpretation. During examination, the claims must be interpreted as broadly as their terms reasonably allow. In re American Academy of Science Tech Center, F.3d, 2004 WL 1067528 (Fed. Cir. May 13, 2004). In the instant case, ‘in contact’ can be explained as ‘in electrical/indirect contact’ or ‘in direct contact’. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements. As an example, referring to applicant’s fig. 1, the fourth semiconductor region (14) is in direct contact with third electrode (3). The term "indirect contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected with one or more intermediary conducting, insulating or semiconductor layers at the interface of the two elements. As an example, referring to applicant’s fig. 1, element 112 is in indirect contact with element 3 (via element 35).
Regarding claim 5, Darwish‘088 further teaches, “The semiconductor device according to claim 1, wherein a concentration of a second conductivity type impurity contained in the fourth semiconductor region (122’) is higher than a concentration of a second conductivity type impurity contained in the second semiconductor region (120)”.
Response to Arguments
Applicant’s arguments with respect to the newly amended claims have been considered but are moot as these are explained in the above rejection.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817