DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/11/2026 has been entered.
Response to Amendment
Applicant’s amendment dated 02/11/2026, in which claims 1, 8, 21 were amended, claims 10 and 23 were withdrawn, claims 4-5, 15-20 were cancelled, has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3, 6-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, claim 1 recites the limitation “performing a bottom-up deposition process to deposit a first material, wherein the performing the bottom-up deposition process initializes a growth of a conductive via material on the gate contact layer.” It is unclear which material is “a first material” and which material is “a conductive via material”.
The meaning of every term used in a claim should be apparent from the prior art or from the specification and drawings at the time the application is filed. Claim language may not be "ambiguous, vague, incoherent, opaque, or otherwise unclear in describing and defining the claimed invention." In re Packard, 751 F.3d 1307, 1311, 110 USPQ2d 1785, 1787 (Fed. Cir. 2014)…Until the meaning of a term or phrase used in a claim is clear, a rejection under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph is appropriate. See MPEP 2173.05 (a) and MPEP 608.01 (o).
For the purpose of this Action, the limitation “a conductive via material” will be interpreted and examined as -- the first material--.
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US Pub. 20200365698) in view of Huang et al. (US Pub. 20200243385), Chandrashekar et al. (US Pub. 20130302980), Khaderbad et al. (US Pub. 20210083119) and Chiang et al. (US Pub. 20060102197).
Regarding claims 1 and 3, Tsai et al. discloses in Fig. 2-3, Fig. 10-11 a method of manufacturing a semiconductor device, the method comprising:
forming a gate contact layer [301] over a gate electrode [a first conductive layer, a first metal material, a work function layer, and a first barrier layer a fill material of gate stack 603], the gate electrode [a first conductive layer, a first metal material, a work function layer, and a first barrier layer a fill material of gate stack 603] over a channel region of a semiconductor material [107], wherein the gate contact layer [301] comprises tungsten and has a planar surface facing a substrate, the planar surface extending from a first side of the gate contact layer [301] to a second side of the gate contact layer opposite the first side, the first side and the second side being outermost sides of the gate contact layer [301][Figs. 2-3, paragraph [0037]-[0048]];
forming an etch stop layer [1101] over the gate contact layer [301][Fig.11, paragraph [0069]];
forming a dielectric layer [1103] over the etch stop layer [1101], the dielectric layer [1103] having a second planar surface facing the substrate, the second planar surface extending from a first side of the dielectric layer [1103] to a second side of the dielectric layer opposite the first side of the dielectric layer [1103], the first side of the dielectric layer and the second side of the dielectric layer [1103] being outermost sides of the dielectric layer [1103][Fig. 11, paragraph [0070]][before forming the via contacts, the planarized dielectric layer [1103] must have a second planar surface/bottom surface extending from a outermost side of the dielectric layer [1103] to another outermost side of the dielectric layer];
performing an etching process to form a first opening [opening for gate via contact 1105], wherein the first opening [opening for gate via contact 1105] extends through the dielectric layer [1103] and the etch stop layer [1101] to expose the gate contact layer [301], the performing the etching process producing etch by-products in the first opening [Fig. 11, paragraph [0071]][Tsai discloses the claimed etching process. Tsai further discloses “the openings may be formed using any combination of acceptable photolithography and suitable etching techniques such as dry etching process (e.g., plasma etch, reactive ion etch (RIE), physical etching (e.g., ion beam etch (IBE))), wet etching, combinations thereof, and the like. However, any suitable etching processes may be utilized to form the contact via openings”. Thus, it appears that the etching processes disclosed by Tsai would produce etch by-products in the first opening as the claimed etching process.]
performing a deposition process to deposit a first material [material of 1105], wherein the performing the deposition process initializes a growth of the first material [material of 1105] on the gate contact layer [301][Fig. 11, paragraph [0072]].
Tsai et al. fails to disclose
wherein the gate contact layer comprises fluorine free tungsten.
Huang et al. discloses in Fig. 2J, paragraph [0023]
wherein the gate contact layer [128] comprises fluorine free tungsten.
Huang et al. further discloses in Fig. 2J,
before forming via contacts, the dielectric layer [152] having a second planar surface facing the substrate, the second planar surface extending from a first side of the dielectric layer [152] to a second side of the dielectric layer [152] opposite the first side of the dielectric layer [152], the first side of the dielectric layer [152] and the second side of the dielectric layer [152] being outermost sides of the dielectric layer [152].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Huang et al. into the method of Tsai et al. to include wherein the gate contact layer comprises fluorine free tungsten. The ordinary artisan would have been motivated to modify Tsai et al. in the above manner for the purpose of providing suitable material of gate contact layer.
Tsai et al. fails to disclose
the deposition process to deposit the first material comprises a bottom-up deposition process; and
wherein after the performing the bottom-up deposition process, the first material has a top surface between a top surface of the dielectric layer and a bottom surface of the dielectric layer.
Chandrashekar et al. discloses in Fig. 3B, Fig.4B, paragraph [0042], [0061], [0062], [0070], [0079], [0086], [0088]
the deposition process [335 or 464] to deposit the first material [tungsten] comprises a bottom-up deposition process; and
wherein after the performing the bottom-up deposition process [335 or 464], the first material [404] has a top surface between a top surface of the dielectric layer and a bottom surface of the dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chandrashekar et al. into the method of Tsai et al. to include the deposition process to deposit the first material comprises a bottom-up deposition process; and wherein after the performing the bottom-up deposition process, the first material has a top surface between a top surface of the dielectric layer and a bottom surface of the dielectric layer. The ordinary artisan would have been motivated to modify Tsai et al. in the above manner for the purpose of providing a method for forming a tungsten layer with large, vertically-oriented grain growth to provide improved electrical characteristics while the formation of a seam can be avoided, providing advantages such as no trapping of CMP slurry along the seam, no trapping of gaseous impurities like HF in the seam, and minimize electron transport losses at the seam in device [paragraph [0086], [0088] of Chandrashekar et al., and paragraph [0047] of Khaderbad et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Tsai et al. fails to disclose
performing a post etching treatment, wherein the post etching treatment comprises forming a plasma comprising oxygen and hydrogen, wherein the plasma does not comprise nitrogen; and
after the performing the post etching treatment, performing the bottom-up deposition process to fill the first opening;
wherein the plasma further does not comprise an inert gas.
Khaderbad et al. discloses in in Fig. 16A-17A, paragraph [0046]-[0047]
performing a post etching treatment [pre-clean process], wherein the post etching treatment does not comprise nitrogen [using process gases such as hydrogen]; and
after the performing the post etching treatment [pre-clean process], performing the bottom-up deposition process to fill the opening [84].
Chiang et al. discloses in Fig. 3C-Fig. 3D, Fig. 4, Fig. 7, paragraph [0021], [0024]-[0025], [0029]-[0031], [0043], [0052]
performing a post etching treatment [plasma treatment process], wherein the post etching treatment [plasma treatment process] comprises forming a plasma comprising oxygen and hydrogen [vaporized H2O] or [H2 and (vaporized H2O or O2)], wherein the plasma [vaporized H2O] or [H2 and (vaporized H2O or O2)] does not comprise nitrogen; and
after the performing the post etching treatment [plasma treatment process], performing the deposition process to fill the opening [301];
wherein the plasma [vaporized H2O] or [H2 and (vaporized H2O or O2)] further does not comprise an inert gas.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Khaderbad et al. and Chiang et al. into the method of Tsai et al. to include performing a post etching treatment, wherein the post etching treatment comprises forming a plasma comprising oxygen and hydrogen, wherein the plasma does not comprise nitrogen; and after the performing the post etching treatment, performing the bottom-up deposition process to fill the first opening; wherein the plasma further does not comprise an inert gas. The ordinary artisan would have been motivated to modify Tsai et al. in the above manner for the purpose of providing a method for treating an exposed upper surface of a layer of conductive material on a substrate to remove residues which can cause corrosion of the exposed surface, as well as any residues formed on the sidewalls proximate the exposed surface, e.g. the sidewalls of a contact via [paragraph [0009], [0021] of Chiang et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 2, Tsai et al. discloses in Fig. 11, paragraph [0073] wherein the deposition process deposits tungsten. Khaderbad et al. discloses in paragraph [0047] and Chandrashekar et al. discloses in paragraph [0042], [0061], [0062], [0070], [0079], [0086], [0088] wherein the bottom-up deposition process deposits tungsten.
Regarding claim 6, Chiang et al. disclose in paragraph [0052]
wherein the plasma is formed from a gas mixture comprising 95% hydrogen gas and 5% oxygen gas [a volumetric flow ratio of H2O:H2 is in the range of 1:10 to about 1:1000]
Further, selecting optimal value for hydrogen gas and oxygen gas in a gas mixture to achieve the intended performance is within a skill of one ordinary artisan.
In addition, Applicant has not provided any criticality of the claimed value.
It would have been obvious to modify Tsai et al., Chandrashekar et al., Khaderbad et al. and Chiang et al. to provide wherein the plasma is formed from a gas mixture comprising 95% hydrogen gas and 5% oxygen gas. The ordinary artisan would have been motivated to modify Tsai et al., Chandrashekar et al., Khaderbad et al. and Chiang et al. in the manner set forth above for at least the purpose of optimization and routine experimentation to achieve desired preclean efficiency and selectivity. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US Pub. 20200365698) in view of Huang et al. (US Pub. 20200243385), Chandrashekar et al. (US Pub. 20130302980), Khaderbad et al. (US Pub. 20210083119) and Chiang et al. (US Pub. 20060102197) as applied to claim 1 above and further in view of Xu et al. (US Pub. 20210159070)
Regarding claim 7, Tsai et al., Chandrashekar et al., Khaderbad et al. and Chiang et al. fails to disclose
wherein the bottom-up deposition process has an incubation time delay ranging from about 6.0 seconds to about 14.7 seconds.
Xu et al. discloses in paragraph [0004] “incubation delay could be leveraged to enable bottom-up gap fill without seam/void and liner film.”
In addition, Applicant has not provided any criticality of the claimed range.
It would have been obvious to modify Tsai et al., Chandrashekar et al., Khaderbad et al. and Chiang et al. to provide wherein the bottom-up deposition process has an incubation time delay ranging from about 6.0 seconds to about 14.7 seconds. The ordinary artisan would have been motivated to modify Tsai et al., Chandrashekar et al., Khaderbad et al. and Chiang et al. in the manner set forth above for at least the purpose of optimization and routine experimentation to achieve desired bottom-up gap fill without seam/void [paragraph [0004] of Xu et al.]. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Claims 8-9, 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US Pub. 20200279774) in view of Yen et al. (US Pub. 20150364371), Khaderbad et al. (US Pub. 20210083119), Chiang et al. (US Pub. 20060102197), Huang et al. (US Pub. 20200243385).
Regarding claims 8 and 9, Su et al. discloses in Fig. 1G, Fig. 1I-1J a method of manufacturing a semiconductor device, the method comprising:
forming a gate stack [110a] over a substrate [100 and 102][Fig. 1G, paragraph [0017]];
forming a source/drain plug [134] to a source/drain [116] adjacent to the gate stack [110a];
forming a contact layer [114] over the gate stack [110a], wherein the gate contact layer [114] comprises tungsten and has a planar surface [bottom surface] facing the substrate [100 and 102], the planar surface [bottom surface] extending from a first side [left side] of the contact layer [114] to a second side [right side] of the contact layer [114] opposite the first side [left side], the first side [left side] and the second side [right side] being outermost sides of the contact layer [114][Fig. 1G, paragraph [0017]];
forming a source/drain contact [148] to the source/drain plug [134];
forming a gate stack via opening [144] exposing the contact layer [114], wherein the forming the gate stack via opening [144] produces etch by-products in the gate stack via opening [144][“produces etch by-products in the gate stack via opening” is a result of the step of “forming a gate stack via opening.” Thus, the step of forming a gate stack via opening disclosed by Su et al. would produces etch by-products in the gate stack via opening][Fig. 1I, paragraph [0036]];
performing a deposition process in the gate stack via opening [144] by initializing a growth of a conductive via material [150] on the contact layer [114][Fig. 1J and paragraph [0037]].
Su et al. fails to disclose
forming a dielectric layer over the source/drain contact having a second planar surface facing the substrate, the second planar surface extending from a first side of the dielectric layer to a second side of the dielectric layer opposite the first side of the dielectric layer, the first side of the dielectric layer and the second side of the dielectric layer being outermost sides of the dielectric layer;
after the forming the source/drain contact, forming the gate stack via opening through the dielectric layer.
Yen et al. discloses in Fig. 9-Fig. 11, paragraph [0031], [0034]-[0035]
forming a dielectric layer [58] over the source/drain contact [52] having a second planar surface facing the substrate [20], the second planar surface extending from a first side of the dielectric layer [58] to a second side of the dielectric layer [58] opposite the first side of the dielectric layer [58], the first side of the dielectric layer [58] and the second side of the dielectric layer [58] being outermost sides of the dielectric layer [58];
after the forming the source/drain contact [52], forming the gate stack via opening [62A] through the dielectric layer [58].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yen et al. into the method of Su et al. to include forming a dielectric layer over the source/drain contact having a second planar surface facing the substrate, the second planar surface extending from a first side of the dielectric layer to a second side of the dielectric layer opposite the first side of the dielectric layer, the first side of the dielectric layer and the second side of the dielectric layer being outermost sides of the dielectric layer; after the forming the source/drain contact, forming the gate stack via opening through the dielectric layer. The ordinary artisan would have been motivated to modify Su et al. in the above manner for the purpose of providing suitable alternative method and suitable order for forming source/drain contact and gate contact to increase a flexibility of wiring pattern designing, to prevent undesirable shorting between contact plug if a misalignment occurs [paragraph [0008], [0036], [0039] of Yen et al.]. Further, selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946).
Su et al. fails to disclose
the deposition process in the gate stack via opening is a bottom-up deposition process.
Khaderbad et al. discloses in Fig.17A, paragraph [0047]
the deposition process in a via opening [84] is a bottom-up deposition process.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Khaderbad et al. into the method of Su et al. to include the deposition process in the gate stack via opening is a bottom-up deposition process. The ordinary artisan would have been motivated to modify Su et al. in the above manner for the purpose of providing a method of filling openings with no air-gap generated therein [paragraph [0047] of Khaderbad et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Su et al. fails to disclose
cleaning the etch by-products by exposing the gate stack via opening to a plasma comprising a first high energy species and hydrogen;
wherein the first high energy species comprises oxygen.
Khaderbad et al. discloses in in Fig. 16A-17A, paragraph [0046]-[0047]
cleaning the etch by-products by exposing the gate stack via opening to a cleaning material comprising hydrogen [pre-clean process using process gases such as hydrogen];
Khaderbad et al. further discloses after the performing the cleaning the etch by-products [pre-clean process], performing the bottom-up deposition process to fill the via opening [84].
Chiang et al. discloses in Fig. 3C-Fig. 3D, Fig. 4, Fig. 7, paragraph [0021], [0024]-[0025], [0029]-[0031], [0043], [0052]
cleaning the etch by-products [plasma treatment process] by exposing a via opening [301] to a plasma comprising a first high energy species [oxygen-containing gas; (vaporized H2O or O2)] and hydrogen [H2] and;
wherein the first high energy species comprises oxygen [oxygen-containing gas, (vaporized H2O or O2)].
Chiang further discloses in Fig. 3D, paragraph [0025] after the cleaning the etch by-products [plasma treatment process], performing the deposition process to fill the via opening [301].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Khaderbad et al. and Chiang et al. into the method of Su et al. to include cleaning the etch by-products by exposing the gate stack via opening to a plasma comprising a first high energy species and hydrogen; wherein the first high energy species comprises oxygen. The ordinary artisan would have been motivated to modify Su et al. in the above manner for the purpose of providing a method for treating an exposed upper surface of a layer of conductive material on a substrate to remove residues which can cause corrosion of the exposed surface, as well as any residues formed on the sidewalls proximate the exposed surface, e.g. the sidewalls of a contact via [paragraph [0009], [0021] of Chiang et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Su et al. fails to disclose
wherein the gate contact layer comprises fluorine-free tungsten
Huang et al. discloses in paragraph [0023]
wherein the gate contact layer [128] comprises fluorine-free tungsten.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Huang et al. into the method of Su et al. to include wherein the gate contact layer comprises fluorine-free tungsten. The ordinary artisan would have been motivated to modify Su et al. in the above manner for the purpose of providing suitable alternative material of the gate contact layer [paragraph [0023] of Huang et al.].
Regarding claims 11 and 13, the combination of Su et al., Khaderbad et al. and Chiang et al. discloses the cleaning of claim 8. Similar to the claimed invention, the combination of Su et al., Khaderbad et al. and Chiang et al. further discloses the plasma used in the cleaning comprises oxygen and hydrogen and does not comprise nitrogen. Su et al. and Huang et al. further discloses the contact layer comprises tungsten.
Therefore, it appears, if not it is obvious that the cleaning disclosed by Huang et al., Su et al., Khaderbad et al. and Chiang et al. would result to wherein after the cleaning the contact layer comprises between 0 and 1E+21 nitrogen atoms per cubic centimeter; wherein after the cleaning the contact layer comprises tungsten oxide compounds. “Where the claimed and prior art products …are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Regarding claim 12, Chiang et al. discloses in paragraph [0030], [0052] wherein the first high energy species comprises oxygen [oxygen-containing gas, such as O2, or vaporized H2O].
Huang et al., Su et al., Khaderbad et al. and Chiang et al. fails to disclose
wherein during the cleaning a total volume of hydrogen and oxygen exposed to the gate stack via opening is between about 8,000 cubic centimeters to about 30,000 cubic centimeters.
However, adjusting process conditions including volume of hydrogen and oxygen to achieve desired cleaning performance is within a skill of one ordinary artisan.
In addition, Applicant has not provided any criticality of the claimed range.
It would have been obvious to modify Huang et al., Su et al., Khaderbad et al. and Chiang et al. to provide wherein during the cleaning a total volume of hydrogen and oxygen exposed to the gate stack via opening is between about 8,000 cubic centimeters to about 30,000 cubic centimeters. The ordinary artisan would have been motivated to modify Huang et al., Su et al., Khaderbad et al. and Chiang et al. in the manner set forth above for at least the purpose of optimization and routine experimentation to achieve desired cleaning performance. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US Pub. 20200279774) in view of Yen et al. (US Pub. 20150364371), Khaderbad et al. (US Pub. 20210083119), and Chiang et al. (US Pub. 20060102197) and Huang et al. (US Pub. 20200243385) as applied to claim 8 above and further in view of Chen et al. (US Pat. 7569492), hereafter Chen492.
Regarding claim 14, Huang et al., Su et al., Khaderbad et al. and Chiang et al. fails to disclose
following the cleaning, rinsing the gate stack via opening.
Chen492 discloses in Fig. 2, column 2, column 3, lines 45-67, column 4
following the cleaning [plasma clean], rinsing [HO based process] the opening [contact etch, via etch].
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to incorporate the teachings of Chen492 into the method of Huang et al., Yen et al., Su et al., Khaderbad et al. and Chiang et al. to include following the cleaning, rinsing the gate stack via opening. The ordinary artisan would have been motivated to modify Huang et al., Yen et al., Su et al., Khaderbad et al. and Chiang et al. in the above manner for the purpose of dissolving the soluble oxide and/or fluoride formed, for example, during the plasma clean. Additionally, in embodiments where the wafer is rinsed, for example with de-ionized water, the physical action of the rinsing can help dislodge residues from the surface or can break them into smaller residues that may be removed more readily and thus providing a cleaning process that provides greater cleaning efficiency with less damage to device structures [column 2, column 3, lines 60-67 of Chen492].
Claims 21-22, 24-25, 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US Pub. 20200279774) in view of Khaderbad et al. (US Pub. 20210083119), and Chiang et al. (US Pub. 20060102197) and Huang et al. (US Pub. 20200243385)
Regarding claims 21, 22, 24, 25, Su et al. discloses in Fig. 1G-1J a method of manufacturing a semiconductor device, the method comprising:
forming a gate stack [110a and 114] over a substrate [100 and 102], the gate stack [110a and 114] comprising a conductive feature [114] comprises tungsten, the tungsten having a first planar surface [bottom surface] facing the substrate [100 and 102], the first planar surface [bottom surface] extending from a first side [left side] of the tungsten [114] to a second side [right side] of the tungsten [114] opposite the first side [left side], the first side [left side] of the tungsten [114] and the second side [right side] of the tungsten [114] being outermost sides of the tungsten [114] [Fig. 1G, paragraph [0017]];
forming a mask layer [124a] over the gate stack [110a and 114], wherein the mask layer [124a] has a second planar surface facing the substrate [100], the second planar surface extending from a first side of the mask layer [124a] to a second side of the mask layer [124a] opposite the first side, the first side and the second side being outermost sides of the mask layer [124a];
forming a first dielectric layer [138] over the conductive feature [114] and having a third planar surface facing the substrate [100], the third planar surface extending from a first side of the first dielectric layer [138] to a second side of the first dielectric layer [138] opposite the first side of the first dielectric layer [138], the first side of the first dielectric layer [138] and the second side of the first dielectric layer [138] being outermost sides of the first dielectric layer [138];
etching the first dielectric layer [138] to form a first opening [144], wherein the first opening [144] extends through the first dielectric layer [138] to the conductive feature [114], wherein etching the first dielectric layer [138] deposits by-products on the conductive feature [114] [“deposits etch by-products on the conductive feature” is a result of the step of “etching the first dielectric layer.” Thus, the step of etching the first dielectric layer disclosed by Su et al. would deposits by-products on the exposed conductive feature 114 [Fig. 1I, paragraph [0036]];
performing a deposition process to form a contact [150] in the first opening [144] over the conductive feature [114][Fig. 1J and paragraph [0037]].
Su et al. fails to disclose
performing a post etching treatment in a nitrogen-free environment to remove by- products on the conductive feature, the post etching treatment comprising exposing the conductive feature to a plasma comprising a first high energy species and hydrogen;
after the performing the post etching treatment, performing a bottom-up deposition process to form the contact in the first opening;
wherein the post etching treatment comprises forming the plasma from a mixture of a first gas and a second gas;
wherein the first gas is diatomic hydrogen, wherein the second gas is diatomic oxygen;
wherein the plasma is free of an inert gas.
Khaderbad et al. discloses in in Fig. 16A-17A, paragraph [0046]-[0047]
performing a post etching treatment in a nitrogen-free environment to remove by- products [pre-clean process using process gases such as hydrogen];
after the performing the post etching treatment [pre-clean process], performing a bottom-up deposition process to form the contact in the first opening [84].
Chiang et al. discloses in Fig. 3C-Fig. 3D, Fig. 4, Fig. 7, paragraph [0021], [0024]-[0025], [0029]-[0031], [0043], [0052]
performing a post etching treatment [plasma treatment process] in a nitrogen-free environment to remove by- products on a feature, the post etching treatment [plasma treatment process] comprising exposing the feature to a plasma comprising a first high energy species [oxygen-containing gas; (vaporized H2O or O2)] and hydrogen [H2]];
after the performing the post etching treatment [plasma treatment process], performing a deposition process to form a contact in a first opening [301][Fig. 3D, paragraph [0025]];
wherein the post etching treatment [plasma treatment process] comprises forming the plasma from a mixture of a first gas [H2] and a second gas [oxygen-containing gas; (vaporized H2O or O2)];
wherein the first gas is diatomic hydrogen [H2], wherein the second gas is diatomic oxygen [O2];
wherein the plasma [(vaporized H2O or O2)] and hydrogen [H2]] is free of an inert gas.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Khaderbad et al. and Chiang et al. into the method of Su et al. to include performing a post etching treatment in a nitrogen-free environment to remove by- products on the conductive feature, the post etching treatment comprising exposing the conductive feature to a plasma comprising a first high energy species and hydrogen; after the performing the post etching treatment, performing a bottom-up deposition process to form the contact in the first opening; wherein the post etching treatment comprises forming the plasma from a mixture of a first gas and a second gas; wherein the first gas is diatomic hydrogen, wherein the second gas is diatomic oxygen; wherein the plasma is free of an inert gas. The ordinary artisan would have been motivated to modify Su et al. in the above manner for the purpose of providing a method for treating an exposed upper surface of a layer of conductive material on a substrate to remove residues which can cause corrosion of the exposed surface, as well as any residues formed on the sidewalls proximate the exposed surface, e.g. the sidewalls of a contact via [paragraph [0009], [0021] of Chiang et al.]; and providing a method of filling openings with no air-gap generated therein [paragraph [0047] of Khaderbad et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Su et al. fails to disclose
wherein the conductive feature comprises fluorine-free tungsten
Huang et al. discloses in paragraph [0023]
wherein the conductive feature [128] comprises fluorine-free tungsten.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Huang et al. into the method of Su et al. to include wherein the conductive feature comprises fluorine-free tungsten. The ordinary artisan would have been motivated to modify Su et al. in the above manner for the purpose of providing suitable alternative material of the conductive feature [paragraph [0023] of Huang et al.].
Regarding claim 27, Chiang et al. disclose in paragraph [0052]
wherein the mixture is about 5% oxygen and about 95% hydrogen [a volumetric flow ratio of H2O:H2 is in the range of 1:10 to about 1:1000]
Further, selecting optimal value for hydrogen gas and oxygen gas in a gas mixture to achieve the intended performance is within a skill of one ordinary artisan.
In addition, Applicant has not provided any criticality of the claimed value.
It would have been obvious to modify Su et al., and Chiang et al. to provide wherein the plasma is formed from a gas mixture comprising 95% hydrogen gas and 5% oxygen gas. The ordinary artisan would have been motivated to modify Su et al., and Chiang et al. in the manner set forth above for at least the purpose of optimization and routine experimentation to achieve desired preclean efficiency and selectivity. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Regarding claim 28, Chiang et al. discloses in paragraph [0038]
wherein the post etching treatment is performed at least in part at a pressure of between about .5 Torr to about 1 Torr [0.1 to 999 mTorr].
Besides, adjusting process conditions including pressure to achieve desired cleaning performance is within a skill of one ordinary artisan. In addition, Applicant has not provided any criticality of the claimed range.
It would have been obvious to modify Huang et al., Su et al., Khaderbad et al. and Chiang et al. to provide wherein the post etching treatment is performed at least in part at a pressure of between about .5 Torr to about 1 Torr. The ordinary artisan would have been motivated to modify Huang et al., Su et al., Khaderbad et al. and Chiang et al. in the manner set forth above for at least the purpose of optimization and routine experimentation to achieve desired cleaning performance. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US Pub. 20200279774) in view of Khaderbad et al. (US Pub. 20210083119), and Chiang et al. (US Pub. 20060102197) and Huang et al. (US Pub. 20200243385) as applied to claim 21 above and further in view of Chandrashekar et al. (US Pub. 20130302980).
Regarding claim 26, Su et al., Khaderbad et al., Chiang et al. and Huang et al. fails to disclose
forming a plug layer over the contact; and
planarizing the plug layer to expose the contact.
Chandrashekar et al. discloses in Fig. 4B, paragraph [0086]
forming a plug layer [465 and 405] over the contact [404]; and
planarizing the plug layer [465 and 405] to expose the contact [404].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chandrashekar et al. into the method of Su et al., Khaderbad et al., Chiang et al. and Huang et al. to include forming a plug layer over the contact; and planarizing the plug layer to expose the contact. The ordinary artisan would have been motivated to modify Su et al., Khaderbad et al., Chiang et al. and Huang et al. in the above manner for the purpose of protecting the contact from a coring risk during CMP and providing a void free contact with improved electrical characteristics [paragraph [0086] of Chandrashekar et al.].
Response to Arguments
Applicant’s arguments with respect to claims 1-3, 6-9, 11-14, 21-22, 24-28 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited art discloses similar materials, devices and methods.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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