Prosecution Insights
Last updated: April 19, 2026
Application No. 17/653,173

SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Mar 02, 2022
Examiner
ARDEO, EMILIO
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kabushiki Kaisha Toshiba
OA Round
3 (Non-Final)
40%
Grant Probability
Moderate
3-4
OA Rounds
3y 7m
To Grant
57%
With Interview

Examiner Intelligence

Grants 40% of resolved cases
40%
Career Allow Rate
2 granted / 5 resolved
-28.0% vs TC avg
Strong +17% interview lift
Without
With
+16.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
27 currently pending
Career history
32
Total Applications
across all art units

Statute-Specific Performance

§103
58.6%
+18.6% vs TC avg
§102
18.8%
-21.2% vs TC avg
§112
22.6%
-17.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 5 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/19/2025 has been entered. Claim Status Claims 1, 5-6 and 12 have been amended. Claims 4 and 13 are cancelled and have been withdrawn from consideration. Response to Arguments Applicant’s arguments, see pg. 7 of Remarks, filed 11/19/2025, with respect to the rejection(s) of the amended claims 1 under 35 U.S.C §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of Tang et al. ( doi: 10.1109/IIT.2018.8807951.). Applicant presents that the impurities as discussed by the disclosure of Shimizu are “found in the oxide film or the oxynitride film corresponding to insulation layer 21, not barrier layer 16. As described in [0079], insulation layer 21 is changed into heavily doped region 22a by heat treatment. Implantation is not mentioned. Gallium comes from the nitride semiconductor layer, as described in [0107].” Upon further consideration, the examiner agrees that although Shimizu takes advantage of the available Gallium atoms in the semiconductor structure, Shimizu fails to teach the implantation of Gallium atoms specifically. However, the examiner submits a new reference that teaches the implantation of Gallium atoms. The examiner maintains that ion implantation is a known method of fine tuning the device characteristics of semiconductor devices as taught be Lee and Tanaka. Shimizu further teaches the role of impurities including Gallium atoms in improving device characteristics. The new disclosure of Tang provides evidence that Gallium atoms can be deliberately introduced into the device in order to take advantage of the known electrical properties of Gallium when introduced into specific regions of the semiconductor device. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 1-3, 7-8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US 20170278950), hereinafter, Tanaka, in further view of Lee et al. (US 20140021481 A1), hereinafter, Lee, in further view of Tang et al. (( doi: 10.1109/IIT.2018.8807951.), hereinafter, Tang. With regards to the independent claim 1: Tanaka discloses a method manufacturing a semiconductor device comprising: performing first ion implantation implanting carbon (C) into a nitride semiconductor layer (Tanaka [0008] "a process of forming a p-type semiconductor layer that contains a p-type impurity...an n-type semiconductor region forming process of forming an n-type semiconductor... ion-implanting an n-type impurity into the p-type semiconductor layer and" Tanaka [0012-0013] "the p-type impurity may include at least one selected from the group consisting of beryllium, magnesium, carbon and zinc.”); forming a coating layer on a surface of the nitride semiconductor layer (Tanaka [0076] "…the manufacturer forms the cap film 240 by plasma CVD…the cap film 240 is mainly made of silicon nitrides (SiNx)); performing a first heat treatment (Tanaka [0077] "subsequently heats the p-type semiconductor layer 114 and the ion implanted region 116N."); removing the coating layer (Tanaka [0081] "After the heat treatment, the manufacturer removes the cap film 240 from on the p-type semiconductor layer 114 and the ion implanted region 116A (i.e., then-type semiconductor region 116...removes the cap film 240 by wet etching."); and a second heat treatment (Tanaka [0082]-[0083], where a first heat treatment process (130) is followed by second heat treatment (135)). Although Tanaka also teaches multiple implantations, Tanaka fails to teach a method comprising performing [a] second ion implantation implanting hydrogen (H) into the nitride semiconductor layer . However, Lee, in a similar field of endeavor, discloses a method of manufacturing a semiconductor device comprising performing [a] second ion implantation implanting hydrogen (H) into the nitride semiconductor layer (Lee [0042] "...the at least one ion implanted layer 140 may be a triple layered ion implanted layer including a first ion implanted layer 142, a second ion implanted layer 144, and a third ion implanted layer…" Lee [0043] "The ion implanted layer 140 may include an impurity ion, and the impurity ion may be at least one of argon (Ar), carbon (C), hydrogen (H)..."); Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention to, to apply the teachings of Lee to that of Tanaka, in order to add additional ion implantations steps where the implanted species may include hydrogen, as this is a well-known method of being able to modify the electrical properties of a nitride-based semiconductor device, e.g., implanting multiple ions at targeted depths in-order to form a heterojunction structure to support electrical switching applications (Lee [0061] “the nitride-based semiconductor device 100 according to example embodiments, a two-dimensional electron gas (2DEG) layer 151 may be formed due to a hetero junction structure between the nitride-based semiconductor layer 130 and the channel layer 150, i.e., different band gap energies of the nitride-based semiconductor layer 130 and the channel layer 150, thereby resulting in an interface polarization [in] between” The disclosure of Tanaka and Lee fail to teach the semiconductor manufacturing method further comprising performing third ion implantation implanting Gallium (Ga) in the nitride semiconductor layer. However, in related field of endeavor, Tang teaches the use of Gallium as a semiconductor dopant is well-known in the art (Tang I. Introduction “… gallium has been studied as an alternative p-type dopant due to its high solubility in Ge as compared to boron. In recent reports on PMOS transistor, lower contact resistivity can be achieved by gallium implant”). Therefore, it would have been obvious to a person having ordinary skill in the art, to apply the teachings of Tang to the combined disclosure of Tanaka and Lee in order to dope the nitride semiconductor layer with Gallium (Ga), as Gallium is well-known dopant in the art that can be implanted using known ion implantation techniques as taught by Tang. This is obvious to try as Ga was well-known effects in fine tuning the electrical characteristics of semiconductor devices as well as having known advantages over other dopants such high solubility and lower contact resistivity (Tang ibid.). With regards to claim 2: The combined disclosure of Tanaka, Lee, and Tang teaches the method of claim 1: Tanaka fails to teach a method wherein a dose amount of hydrogen in the second ion implantation is larger than a dose amount of carbon in the first ion implantation. Tanaka, however, teaches that the dosage of the ions can be varied according to methods known in the art (Tanaka, Section B. Evaluation Test, [0093], where different sample were treated with varying implantation dosage). Furthermore, Lee also teaches that the dosage of the ion can also be adjusted according to the desired property of the device (Lee [0068] “The ion implanted layer 235 may be formed at different amounts of the impurity ion being implanted into the nitride-based semiconductor layer 230 or at different depths in the nitride-based semiconductor layer 230 by adjusting a dose of the impurity ion or the implantation energy.") Therefore, in-view of the combined disclosure of Tanaka and Lee, it would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention, to have been able to vary the dosage of the implanted ion as this is common practice in the art, with the known and obvious result of being able to adjust the concentration of implanted ions embedded in a semiconductor layer. With regards to claim 3: The combined disclosure of Tanaka, Lee, and Tang teaches the method of claim 1: Tanaka fails to teach the method wherein a concentration of hydrogen implanted by the second ion implantation at an arbitrary position in depth direction in the nitride semiconductor layer is higher than a concentration of carbon implanted by the first ion implantation. Tanaka, however, teaches that the dosage of the ions can be varied according to methods known in the art (Tanaka, Section B. Evaluation Test, [0093], where different sample were treated with varying implantation dosage). Furthermore, Lee also teaches that the dosage of the ions, including Hydrogen, can also be adjusted according to the desired property of the device (Lee [0068] “The ion implanted layer 235 may be formed at different amounts of the impurity ion being implanted into the nitride-based semiconductor layer 230 or at different depths in the nitride-based semiconductor layer 230 by adjusting a dose of the impurity ion or the implantation energy.") Therefore, in-view of the combined disclosure of Tanaka and Lee, it would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention, to have been able to vary the dosage of the implanted Hydrogen ion as this is common practice in the art, with the known and obvious result of being able to adjust the concentration of implanted ions embedded in a semiconductor layer. With regards to claim 7: The combined disclosure of Tanaka, Lee, and Tang teaches the method of claim 1 Tanaka further teaches a method wherein a dose amount of carbon in the first ion implantation is equal to or more than 1 x 1011 cm-2 and equal to or less than 1 x 1015 cm-2. (Tanaka [0093]-[0142]). Tanaka, with a discussion under the section title B. Evaluation test, describes the implantation conditions for the various embodiments they are teaching. The first operation for example is shown to have two implantation processes there both dose amounts were equal to 1x1015 cm-2 (Tanaka [0097] and [0100]). Another exemplary implantation operation teaches a method where the dose amount is equal to 5x1014 cm-2 (Tanaka [0111], [0114]) With regards to claim 8: The combined disclosure of Tanaka, Lee, and Tang teaches the method of claim 1: Tanaka further teaches a method wherein a dose amount in the second ion implantation is equal to or more than 1 x 1015 cm-2. See rejection of claim 7. Tanaka fails to teach a method where the second ion implant is hydrogen. However, Lee, in a related field of endeavor teaches that hydrogen can also be implanted according to well-known methods in the art (Lee [0043] "The ion implanted layer 140 may include an impurity ion, and the impurity ion may be at least one of argon (Ar), carbon (C), hydrogen (H)..."). Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to consider implanting hydrogen unto semiconductor substrates as it is a known dopant in the art as thought by Lee, with the predictable result of being able to alter the electrical properties of the semiconductor material. With regards to claim 10: The combined disclosure of Tanaka, Lee, and Tang teaches the method of claim 1: Tanaka further teaches the method wherein the coating layer contains silicon nitride (Tanaka Fig. 7 (240), [0076] "… the manufacturer forms the cap film 240 by plasma CVD. According to this embodiment, the cap film 240 is mainly made of silicon nitrides (SiNx) and has a film thickness of about 50 nm."). Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka, Lee, Tang, and in further view of Shimizu et al. (US 20180026124), hereinafter, Shimizu. With regards to claim 5: The combined disclosure of Tanaka, Lee, and Tang teaches the method of claim 1. Tanaka and Lee fail to disclose wherein a dose amount of gallium in the third ion implantation is smaller than a dose amount of carbon in the first ion implantation. This is because the disclosure of Tanaka and Lee fail to teach a method wherein gallium is implanted. As indicated in the rejection of claim 1, Tang teaches that the implantation of Gallium in nitride semiconductors is known in the art. Even though Tang does not teach specific impurity concentrations within a device, it teaches the ability to vary beam current which directly affects dopant concentration and depth of deposition. However, in a related field of endeavor, Shimizu teaches a method wherein the “peak concentration” of a first impurity, (that includes gallium), is equal or greater than 80% of the of the “peak concentration” of a distinct second impurity (i.e. carbon) (Shimizu [0051] "For example, the first peak concentration is equal to or greater than 80° of the second peak concentration." The examiner notes that the “peak concentration” is directly correlated to dosing as is known in the art. ). Therefore, a person having ordinary skill in the art would have been motivated, prior to the effective filing date of the claimed invention, to apply the teachings of Shimizu to the combined disclosure of Tanaka, Lee, and Tang, in order to recreate the invention as described in claim 4, which includes the disclosed advantages of being able to fabricate a more reliable semiconductor device through the introduction of gallium in controlled doses as taught by Shimizu, where the gallium concentration can be 80% the concentration of the carbon impurity. The examiner also restates the same argument put forward in the rejection of claim 2 wherein the combined disclosure of Tanaka and Lee, would have made it obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to have been able to vary the dosage of the implanted ions according to the desired characteristics of the device, as both disclosures teach that the variation of dopant dose is a common practice in the art, with the known and obvious result of being able to adjust the concentration of implanted ions embedded within a semiconductor layer. With regards to claim 6: The combined disclosure of Tanaka, Lee, and Tang teaches the method of claim 1. Tanaka and Lee both fail to teach a method wherein a concentration of gallium implanted by the third ion implantation at an arbitrary position in depth direction in the nitride semiconductor layer is lower than a concentration of carbon implanted by the first ion implantation. As indicated in the rejection of claim 1, Tang teaches that the implantation of Gallium in nitride semiconductors is known in the art. Even though Tang does not teach specific impurity concentrations within a device, it teaches the ability to vary beam current which directly affects dopant concentration and depth of deposition. However, Shimizu, in a related field of endeavor, teaches a method of fabricating a semiconductor device wherein two distinct ionic species, gallium and carbon, are implanted unto the same general depth or layer within the semiconductor device, resulting in an overlap of their respective spatial concentration distribution (Shimizu [0031] “impurity selected from the group consisting of boron (B), gallium (Ga), aluminum (Al), and indium (In) and carbon (C)... A first peak of a concentration distribution of the at least one impurity in the insulating layer is present in the oxide film or the oxynitride film. Second peak of a concentration distribution of carbon in the insulating layer is present in the oxide film or the oxynitride film.”, see also Fig. 2B along with ¶[0048]) As previously mentioned in the rejection of claim 3 the overlapping spatial distribution of multiple ionic species, within the same layer or within close proximity to each other, is taught by Shimizu to enhance the reliability of the device via the formation of complexes that have dangling bonds. The free electron from these dangling bonds alter the band energy levels of the interface such that the electrons from the gate side are restricted from crossing over towards the insulating or barrier layer, thus preventing current collapse or unwanted variation in threshold voltages (Shimizu [0092]). Therefore, a person having ordinary skill in the art would have been motivated, prior to the effective filing date of the claimed invention, to apply the teachings of Shimizu to the combined disclosure of Tanaka, Lee, and Tang in order to improve the reliability of the semiconductor device by combining multiple ionic impurities within the semiconductor layer with the obvious result of being able to mitigate the unwanted effects of electron trapping, i.e. “current collapse or variation in threshold voltage” (Shimizu [0037]). Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Tanaka, Lee, and Tang and in further view of Olsen et al. (US 7429540 B2), hereinafter, Olsen With regards to claim 9: The combined disclosure of Tanaka Lee, and Tang teaches the method of claim 1. Tanaka, Lee, and Tang fails to teach a method wherein the second heat treatment is performed at a pressure lower than a pressure in the first heat treatment. However, Olsen, in a similar field of fabricating semiconductor devices, teaches a method with multiple annealing steps where the first annealing pressure is higher than the second annealing pressure (Olsen Col. 3 Line 41, “The second step 206 of the anneal process is performed at a reduced pressure of about 10 mTorr to about 100 Torr” Olsen varies the pressure of the annealing step as it is shown to affect the properties/characteristic of the semiconductor device as pressure is known in the art to affect reaction rates and diffusion rates. In this case, Olsen, varies the pressure, along with temperature and flow-rates, to control the effective oxide thickness of the semiconductor device (Olsen Col. 3 Line 44, “The second step 206 is controlled to provide a 0.1 to about 2 increase in the silicon oxynitride EOT”). Therefore, it would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention, to have been able to apply the teachings of Olsen to the fabrication methods of Tanaka, Lee, and, Tang in order to be able to modify the properties of their semiconductor devices, in order to achieve desirable properties such as improves channel mobility and drive current (Olsen Col. 2 Line 1). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILIO ARDEO whose telephone number is (703)756-1235. The examiner can normally be reached Mon-Fri EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EMILIO ARDEO/Examiner, Art Unit 2899 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

Mar 02, 2022
Application Filed
Feb 19, 2025
Non-Final Rejection — §103
May 27, 2025
Response Filed
Aug 14, 2025
Final Rejection — §103
Nov 19, 2025
Request for Continued Examination
Nov 24, 2025
Response after Non-Final Action
Mar 23, 2026
Non-Final Rejection — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
40%
Grant Probability
57%
With Interview (+16.7%)
3y 7m
Median Time to Grant
High
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