DETAILED ACTION
This application, 17/654530, attorney docket 507814.5000432, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to The University of Chicago, and has an effective filing date of 3/15/2019. It is a National Stage entry of PCT/US20/22702, and claims Priority from Provisional Application 62819221 , filed 03/15/2019. Claims 1-12 and 15-22 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Response to Arguments
Applicant has amended claims 1, 15 and 18 to include the limitation that the upper electrode of the MIM capacitors is shared and correctly argues that the art of record Rui does not teach the added limitation. Therefore, the previous rejection is withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-6, 12 and 21 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Kang et al. (U.S. 2017/0098652).
As for claim 1,
Kang teaches in figure 1, an integrated circuit (IC) comprising:
A first transistor device (two transistors with gates 13 are shown in figure 1, first device mapped on the left);
a first metal-insulator-metal (MIM) capacitor comprising a first layer (131, [0065]) comprising electrically conductive material ([0072]), the first layer conductively coupled to the first transistor device (at 18),
a second layer (300) comprising electrically conductive material ([0076]) above the first layer,
and one or more intervening layers ([0075]) between the first and second layers,
the one or more intervening layers comprise at least a third layer (220), wherein the third layer comprise (i) a first metal, (ii) oxygen, and (iii) one or both of a second metal or an oxide thereof within the third layer. (may be RuO [0075]).
a second transistor device (mapped on the right of fig1);
a second MIM capacitor comprising a fourth layer (131) comprising electrically conductive material ([0072]), the fourth layer (131) conductively coupled to the second transistor device (at 18),
a fifth layer (300) comprising electrically conductive material above the fourth layer, and one or more additional intervening layers ([0075]) between the fourth and fifth layers, the one or more additional intervening layers comprise at least a sixth layer (220), wherein the sixth layer comprises (i) a third metal, (ii) oxygen, and (iii) one or both of a fourth metal or an oxide thereof within the sixth layer (may be AlN and ZrO, [0075]),
wherein the second layer is an upper electrode of the first MIM capacitor, the fifth layer is an upper electrode of the second MIM capacitor, and the second and fifth layers form a continuous upper electrode for both the first and second MIM capacitors (shown across the fin 121).
As for claim 3,
Kang teaches the integrated circuit of claim 1, wherein the second metal is elementally different from the first metal. (Al is the first metal and the second is Zr)
As for claim 4,
Kang teaches the integrated circuit of claim 1, wherein the first metal comprises one of hafnium, aluminum, zirconium, titanium, or tantalum. (Al, [0075]).
As for claim 5,
Kang teaches the integrated circuit of claim 1, wherein the second metal comprises one of hafnium, aluminum, zirconium, titanium, lanthanum, yttrium, gadolinium, or palladium. (Hf is listed [0075]).
As for claim 6,
Kang teaches the integrated circuit of claim 1, wherein each of the first and second layers comprise a metal or an alloy thereof. ([0075]).
As for claim 12,
Kang teaches the integrated circuit of claim 1, wherein the first layer is conductively coupled to a drain of the transistor device. (107b, claim 31).
As for claim 21,
Kang teaches the integrated circuit of claim 1, and Kang teaches that the first MIM capacitor is laterally adjacent to the second MIM capacitor above the first and second transistor devices. (shown in figure 1)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 7-11, 15-20 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Kang view of Rui et al. (U.S. 2015/0228710) .
As for claim 2,
Kang teaches integrated circuit of claim 1,
But does not teach that the concentration of the second metal or the oxide thereof in the third layer is in the range of 1E 12 to 1E24 atoms per cubic cm.
However, Rui teaches the second metal or the oxide thereof in the third layer is in the range of (below 10 atomic %,Rai [0159]).
It would have been obvious to one skilled in the art at the effective filing date of this application to substitute the dielectric of Rui into Kang because the “dielectric layer that exhibits lower leakage current, a high EOT, and a high k-value” (Rai [0009]). One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 7,
Kang teaches the integrated circuit of claim 1,
But does not teach that the one or more intervening layers further comprise (i) a seventh layer (1104) comprising a fifth metal and oxygen (TiOx, [0158]),
and (ii) an eighth layer (1112) comprising a sixth metal and oxygen (TiOx, 0162]),
and wherein at least one of the seventh layer or the eighth layer is substantially undoped. (Both are undoped).
However, Rui teaches one or more intervening layers further comprise (i) a seventh layer (1104) comprising a fifth metal and oxygen (TiOx, [0158]),
and (ii) an eighth layer (1112) comprising a sixth metal and oxygen (TiOx, 0162]),
and wherein at least one of the seventh layer or the eighth layer is substantially undoped. (Both are undoped).
It would have been obvious to one skilled in the art at the effective filing date of this application to substitute the dielectric of Rui into Kang because the “dielectric layer that exhibits lower leakage current, a high EOT, and a high k-value” (Rai [0009]). One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 8,
Kang in view of Rui makes obvious the integrated circuit of claim 7,
And in the substitution, Rui teaches that the third layer is between the seventh and eighth layers. (shown in figure 11).
As for claim 9,
Kang in view of Rui makes obvious the integrated circuit of claim 8,
And in the substitution, Rui teaches that the fifth metal and the sixth metal are the same metal (both can be TiOx).
As for claim 10,
Kang in view of Rui makes obvious the integrated circuit of claim 7,
And in the substitution, Rui teaches that the seventh layer is between the third and eighth layers. (shown in figure 11)
As for claim 11,
Kang in view of Rui makes obvious the integrated circuit of claim 10,
And in the substitution, Rui teaches that the first metal and the sixth metal are the same metal. (both can be Ti).
As for claim 15,
Kang teaches in figure 1, a memory array comprising:
a memory cell comprising (i) a first transistor, (ii) a first capacitor above and conductively coupled to the first transistor, (iii) a second transistor, and (iv) a second capacitor above and conductively coupled to the second transistor, (two transistors with gates 13 are shown in figure 1, first device mapped on the left and connected to the capacitors by via 18 shown in figure 1),
wherein the capacitor comprises a first electrode (300, [0065]),
a second electrode (131)
and one or more layers (220, [0075]) of metal oxide between the first and second electrodes,
wherein the second capacitor comprises a third electrode (300), a fourth electrode (131),
wherein the first electrode is an upper electrode of the first capacitor, the third electrode is an upper electrode of the second capacitor, and the first and third electrodes form a continuous upper electrode for both the first and second capacitors.(shown in figure 1).
Kang does not teach that a first layer of the one or more layers of metal oxide comprises (i) an oxide of a first metal, and (ii) a second metal or an oxide thereof within the first layer. (ZrO doped with aluminum, cerium, cobalt, erbium, gallium, gadolinium, germanium, hafnium, lanthanum, magnesium, molybdenum, niobium, silicon, tin, strontium, titanium, vanadium, yttrium, or combinations thereof, [0159]).
However, Rui teaches that a first layer of the one or more layers of metal oxide comprises (i) an oxide of a first metal, and (ii) a second metal or an oxide thereof within the first layer. (ZrO doped with aluminum, cerium, cobalt, erbium, gallium, gadolinium, germanium, hafnium, lanthanum, magnesium, molybdenum, niobium, silicon, tin, strontium, titanium, vanadium, yttrium, or combinations thereof, [0159]).
It would have been obvious to one skilled in the art at the effective filing date of this application to substitute the dielectric of Rui into Kang because the “dielectric layer that exhibits lower leakage current, a high EOT, and a high k-value” (Rai [0009]). One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 16,
Kang in view of Rui makes obvious the memory array of claim 15,
And Kang teaches that the memory cell is an embedded dynamic random-access memory (eDRAM) cell. (Kang [0140])
As for claim 17,
Kang in view of Rui makes obvious the memory array of claim 15,
And in the combination, the substituted dielectric of Rui includes one or more layers of metal oxide comprises a third layer (1104) that includes an oxide of a fifth metal, and wherein the third layer is substantially undoped (undoped TiOx, [0158]).
As for claim 18,
Kang teaches a capacitor structure comprising:
a first capacitor (top left of figure 1) comprising a first electrode (300) comprising conductive material ([0076]);
a second electrode (131) comprising conductive material ([0071]);
and a second capacitor (top right of figure 1) comprising a third electrode (300) comprising conductive material ([0076);
a fourth electrode (131) comprising conductive material ([0072]);
and wherein the first electrode is an upper electrode of the first capacitor, the third electrode is an upper electrode of the second capacitor, and the first and third electrodes form a continuous upper electrode for both the first and second capacitors (shown continuous in figure 1).
Kang does not teach that the capacitor dielectrics comprise a first layer, a second layer, and a third layer between the first and second electrodes, wherein the first layer comprises an oxide of a first metal, the second layer comprises an oxide of a second metal, and the third layer comprises an oxide of a third metal, wherein at least one of the first, second, or third layers is doped with one or both of (i) a fourth metal or (ii) an oxide of the fourth metal, and wherein at least another of the first, second, or third layers is substantially undoped;
However, Riu teaches a capacitor dielectric that includes a first layer (1108),
a second layer (1102), and a third layer (1108) between the first and second electrodes,
wherein the first layer comprises an oxide of a first metal (ZrOx, [0159]), the second layer comprise an oxide of a second metal (TiOx, [0158]), and the third layer comprises an oxide of a third metal (TiOx [0162]).
wherein at least one of the first, second, or third layers is doped with one or both of (i) a fourth metal or (ii) an oxide of the fourth metal ( first layer is doped ZrO[0159]) , and wherein at least another of the first, second, or third layers is substantially undoped.(1104 and 1112 are undoped).
It would have been obvious to one skilled in the art at the effective filing date of this application to substitute the dielectric of Rui into Kang because the “dielectric layer that exhibits lower leakage current, a high EOT, and a high k-value” (Rai [0009]). One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 19,
Kang in view of Rui makes obvious the capacitor structure of claim 18,
And in the substitution, the first layer is doped with one or both of the fourth metal or the oxide of the fourth metal, and wherein the fourth metal is elementally different from the first metal. (ZrO doped with aluminum, cerium, cobalt, erbium, gallium, gadolinium, germanium, hafnium, lanthanum, magnesium, molybdenum, niobium, silicon, tin, strontium, titanium, vanadium, yttrium, or combinations thereof, [0159]).
As for claim 20,
Kang in view of Rui makes obvious the capacitor structure of claim 18, and Kang teaches that the first and second capacitors are above, and conductively coupled to, respective drain terminals of a first transistor and a second transistor. (figure 1).
As for claim 22,
Kang in view of Rui makes obvious the memory array of claim 15, and in the combination, Kang teaches that the first capacitor is laterally adjacent to the second capacitor above the first and second transistor devices. (figure 1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOHN A BODNAR/ Primary Examiner, Art Unit 2893