DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Prior rejection of Claims 7-11 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, is withdrawn in view of applicant’s amendments to claim 7.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Yeon et al. (US 2022/0139999 A1, of record), and further in view of Kabe et al. (US 2016/0043060 A1, of record) and Higuchi et al. (US 2016/0181228 A1, of record).
Re Claim 1, Yeon teaches a hybrid bonded structure comprising:
a first substrate stack (250, Fig. 3, para [0063]) comprising:
a silicon substrate (210, Fig. 3, para [0063]);
a first plurality of first conductive bonding regions (242, Fig. 3, para [0063]);
a first dielectric layer (241, Fig. 3, para [0063]); and
metal-oxide-silicon (MOS) circuitry (245, Fig. 3, para [0063]) patterned into the silicon substrate (210) and electrically connected with the first plurality of first conductive bonding regions (see Fig. 3);
wherein the first substrate stack (250) is characterized by a first coefficient of thermal expansion (CTE);
a second substrate stack (190+160+280, Fig. 3, paras [0044] and [0063]) comprising:
a plurality of diodes (LC_A1, LC_A2, LC_A3, para [0044] - [0045], Fig. 3) formed of III-V inorganic semiconductor-based materials (AlN or AlGaN, para [0046]);
a second dielectric layer (159, Fig. 3, para [0061]) around the plurality of diodes;
a second plurality of second conductive bonding regions (285+285P, Fig. 3, para [0065]) formed on the plurality of diodes; and
an intermediate adhesive layer (281, Fig. 3, para [0064]);
wherein the second substrate stack (190+160+280) is characterized by a second CTE different from the first CTE (the second stack has a plurality of diodes while the first stack has a plurality of transistors, thus having different structures, which will result in different CTE);
wherein the first substrate stack (250) and the second substrate stack (190+160+280) are bonded together at a bonding interface (interface of 280 and 250, Fig. 3), wherein the bonding interface is formed where the first plurality of first conductive bonding regions (242) is bonded directly to the second plurality of second conductive bonding regions (285+285P), and the first dielectric layer (241) directly contacts and is bonded to the intermediate adhesive layer (281).
Yeon does not disclose the material of the insulating layer 241 and hence does not teach that the first dielectric layer is made of SiCN.
However, in a related direct bonding art, Higuchi teaches an insulating layer 104a (Fig. 1, para [0061]) of semiconductor stack 100 (Fig. 1, para [0055]) that directly bonds to the layer 204a (Fig. 1, para [0069]) of semiconductor stack 200 (Fig. 1, para [0055]), where the layer 104a can be silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), nitrogen-containing silicon carbide (SiCN) or oxygen-containing silicon carbide (SiCO).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the semiconductor device of Yeon such that the first insulating layer is made of SiCN as disclosed by Higuchi. Higuchi teaches that silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), nitrogen-containing silicon carbide (SiCN) or oxygen-containing silicon carbide (SiCO) are art recognized alternative materials for a direct bond interface, and one of ordinary skill in the art would have found it obvious to select one of the known materials for the insulating layer of Yeon. The selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Yeon also does not disclose the material for the dielectric layer 281 within the second stack and hence does not teach that the layer is made up of an organic adhesive layer.
However, in a related direct bonding art, Kabe teaches an intermediate adhesive layer (141, Fig. 1, para [0041]) which can be made up of a variety of materials including SiOx, SiNx, or SiOxNy or an organic film of benzocyclobutene (BCB), polybenzoxazole (PBO), polyimide (PI), or any other organic material.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the semiconductor device of Yeon such that the intermediate adhesive layer is made up of an organic adhesive layer as disclosed by Kabe. Kabe teaches an intermediate adhesive layer which can be made up of a variety of materials including SiOx, SiNx, or SiOxNy or an organic film of benzocyclobutene (BCB), polybenzoxazole (PBO), polyimide (PI), or any other organic material, and one of ordinary skill in the art would have found it obvious to select one of the known materials for the intermediate adhesive layer of Yeon. The selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Re Claim 4, Yeon modified by Higuchi and Kabe teaches the hybrid bonded structure of claim 1, wherein the bonding interface is a planar bonding interface (bonding interface of 280 and 250 is planar, see Fig. 3, Yeon).
Re Claim 5, Yeon modified by Higuchi and Kabe teaches the hybrid bonded structure of claim 1, wherein the first plurality of first conductive bonding regions is a first plurality of first bond pads (242, Fig. 3, Yeon), and the second plurality of second conductive bonding regions is a second plurality of second bond pads (285+285P, Fig. 3, Yeon).
Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yeon et al. (US 2022/0139999 A1, of record), Higuchi et al. (US 2016/0181228 A1, of record) and Kabe et al. (US 2016/0043060 A1, of record) as applied to claim 1 above, and further in view of Hu et al. (US 2014/0159066 A1, of record).
Re Claim 7, Yeon modified by Higuchi and Kabe teaches the hybrid bonded structure of claim 1, but does not explicitly state that the plurality of micro-LEDs (LED pixels, LC_A1, LC_A2, LC_A3, para [0044] - [0045], Fig. 3, Yeon) are each characterized by a maximum lateral dimension of less than 100 microns.
However, in the related field of art, Hu discloses LED display devices wherein each micro-LED has a maximum dimension of 1 to 100 µm (para [0028]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to use micro-LEDs having dimensions disclosed by Hu in the modified display device disclosed by Yeon, Higuchi and Kabe, for smaller pixels thereby enabling higher resolution images.
Re Claim 8, Yeon modified by Higuchi, Kabe and Hu teaches the hybrid bonded structure of claim 7, wherein a pitch between the plurality of micro diodes is less than 20 microns (pitch can be 5 µm, para [0028], Hu).
Re Claim 9, Yeon modified by Higuchi, Kabe and Hu teaches the hybrid bonded structure of claim 8, wherein the plurality of micro diodes is dispersed across an area greater than 1 mm by 1 mm (Yeon discloses conventional LED display apparatus, e.g. TVs, PCs, mobile phones, etc., paras. [0002]-[0003], all known to have display areas much larger than 1 mm x 1 mm; Hu discloses micro-LED device can be dispersed within a 1 cm by 1cm array, para [0034]).
Re Claim 10, Yeon modified by Higuchi, Kabe and Hu teaches the hybrid bonded structure of claim 8, integrated into a display device (display apparatus, abstract, Yeon).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yeon et al. (US 2022/0139999 A1, of record), Higuchi et al. (US 2016/0181228 A1, of record), Kabe et al. (US 2016/0043060 A1, of record) and Hu et al. (US 2014/0159066 A1, of record) as applied to claim 8 above, and further in view of Bower et al. (US 2015/0371585 A1, of record).
Re Claim 11, Yeon modified by Higuchi, Kabe and Hu teaches the hybrid bonded structure of claim 8, but is silent about the integration into an image sensor device.
However, in the related semiconductor field of art, Bower teaches that an array of micro-LEDs can be interlaced between functional elements to integrate in to an image capture device or optical sensors (paras [0010], [0228], [0229], and [0251]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to integrate the modified device disclosed by Yeon, Higuchi, Kabe, and Hu, with an image sensor device as disclosed by Bower in order to create a multifunctional and economical semiconductor device.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In the remarks, the applicant argued that “none of the cited references suggests (nor would one of ordinary skill in the art have been motivated upon review of the cited references to arrive at) a hybrid bonded structure in which the second substrate stack includes a plurality of diodes formed of III-V inorganic semiconductor-based materials and the intermediate organic adhesive layer”.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
The examiner respectfully disagrees with the applicant. Yeon et al. shows a hybrid bonding structure in which the second stack includes a plurality of diodes formed of III-V inorganic semiconductor-based materials and an intermediate adhesive layer. Yeon does not give the material for the first dielectric layer nor the material for the intermediate adhesive layer. Higuchi is relied upon to select a known dielectric material like SiCN and Kabe is relied upon to select an intermediate organic adhesive layer from a selection of known materials as described in claim 1 above. Additionally, the bonding of an SiCN layer to an organic adhesive layer is also known in the art, for example, see Fig. 5 of Usui et al. (US 2005/0067682 A1), where the element 450 is bonded to the element 430 via a direct bonding of SiCN layer 451 and a polyimide film 452, or see Ohnishi et al. (US 2004/0041269 A1), Fig. 6, where the two MSQ layers 102 and 112 are bonded together via a SiCN (108) - BCB (110) bonded layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINAKI DAS whose telephone number is (703)756-5641. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898