DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 8/26/2025 and 10/17//2025 were filed after the mailing date of the final rejection on 6/27//2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 1, 2, 3, 4, 6, 7, 9, and 21 are objected to because of the following informalities:
Claim 1 recites “the first side of first transistor” in lines 12 and 13. The examiner suggests “the first side of the first transistor”.
Claim 2, 3, 4, 6, 7, 9, and 21 depend from and incorporate claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 3, 4, 6, 7, 9, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Majhi (US 2023/0197612) in view of Bohr (US 2019/0378790).
Regarding claim 1
Majhi teaches an apparatus, comprising: a first transistor (fig 2:104d;paragraph 28) formed within a transistor region (fig 1b:106;paragraph 34) of an integrated circuit (fig 1a:100;paragraph 34); a first metal layer (fig 1a:112;paragraph 38) located above the transistor region (fig 1b:106; paragraph 34) in a vertical dimension (fig 1a:z) perpendicular to the transistor region (fig 1a:106;paragraph 34); a second metal layer (fig 2:122, paragraph 39) located below the transistor region (106) in the vertical dimension (fig 1a:z); a first wire (fig 2:114-3;paragraph 73) located in the first metal layer (fig 2:112, paragraph 58), the first wire (fig 2:114-3,paragraph 73) being connected to a signal input of the first transistor (fig 2:104d, paragraph 70); a second wire (fig 1a:124a; paragraph 43) located in the second metal layer (fig 1:122; paragraph 39), wherein the second wire (fig 1a:122,paragraph 39) passes below the first transistor (fig 2:104d;paragraph 68) in the vertical dimension (fig 2:z) from a first side of the first transistor (fig 2:104d; paragraph 68) to a second side of the first transistor (fig 2:104d,paragraph 68) in a horizontal dimension (X) perpendicular to the vertical dimension (z) (see annotated fig 2); and at least one via structure (see annotated figure 2) positioned [ . . . ] adjacent to the first side of the first transistor (fig 2:104d; paragraph 68), wherein the at least one via structure connects the first wire (fig 2:114-3;paragraph 73) to the second wire (fig 2:122,paragraph 39), a control signal routed to the signal input of the first transistor (annotated fig 2:104d;paragraph 68), […] wherein the control signal is routed from the second side of the first transistor (fig 2:104d;paragraph 68) to the first side of the first transistor (fig 2:104d;paragraph 68) through the second wire (fig 2:122; paragraph 39), and then from the second wire(fig 2:122; paragraph 39) to the first wire (fig 2:114-3,paragraph 73) and into the signal input of the first transistor (fig 2:104d;paragraph 68).
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Majhi does not teach that the control signal is routed to pass below the first transistor in the vertical dimension in the disclosed example embodiment.
Majhi teaches that the control signal is routed to pass below a transistor (fig 2:104c,paragraph 68) in the vertical dimension (z), through the at least one via.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to route the control signal to another transistor because many such logic signal routing between different devices of the device layer are done through the corresponding interconnect features (paragraph 68) and numerous configurations and variations will be apparent in light of this disclosure (paragraph 33).
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Majhi does not teach an inactive cell.
Bohr teaches at least one via structure (fig 1c:102, paragraph 40) positioned in an inactive cell (paragraph 37) adjacent to the first side of first transistor (fig 1a:106,104;paragraph 38), wherein the at least one via structure (fig 1b:102;paragraph 40) connects the first wire (fig 1c:128;paragraph 37) to the second wire (fig 1c:130;paragraph 37), wherein the at least one via structure (fig 1c:134, paragraph 40) includes at least one source/drain region (annotated fig 1a, paragraph 36) in the transistor region (annotated fig 1a;paragraph 38), and through the at least one source/drain region (annotated fig 1a).
Note an inactive cell comprises a dummy gate according to applicant’s disclosure (US 2023/0299068 paragraph 67).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to pass the through silicon via through an inactive region in order avoid interference with active device that could be negatively affected by the presence of the via.
Regarding claim 2.
Majhi in view of Bohr teaches the structure of claim 1.
Majhi teaches a power rail (fig 4:144b;paragraph 44) connected to a third wire (fig 4:129;paragraph 50) in the first metal layer (fig 4:112,paragraph 38) and a fourth wire (fig 4:124b;paragraph 43) in the second metal layer (fig 4:122;paragraph 43), wherein the first transistor (fig 4:104d;paragraph 68) is connected to the power rail (fig 4:144b,paragraph 44) via the third wire (fig 4:129;paragraph 50) and the fourth wire (fig 4:124b;paragraph 43).
Regarding claim 3
Majhi in view of Bohr teaches the structure of claim 1.
Majhi teaches a second transistor (fig 2:104a;paragraph 44) formed within the transistor region (fig 1b:106,paragraph 64), wherein the first transistor (fig 2:104d;paragraph 68) and the second transistor (fig 2:104a;paragraph 68) are separated in the horizontal dimension (fig 2:x).
Regarding claim 4
Majhi in view of Bohr teaches the structure of claim 3.
Majhi teaches the control signal is routed from a signal output of the second transistor (fig 2:104a;paragraph 68) on the second side of the first transistor (fig 2:104d;paragraph 68), from the second wire (fig 2:124a;paragraph 43) to the first wire (fig 2:114-3;paragraph 73) on the first side of the first transistor (fig 2:104d;paragraph 68), and to the signal input of the first transistor (fig 2:104d;paragraph 68) (paragraph 70) (fig 2).
Majhi does not teach that the control signal is routed to pass below the first transistor in the vertical dimension.
Majhi teaches that the control signal is routed to pass below a transistor (fig 2:104c,paragraph 68) in the vertical dimension (z), through the at least one via.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to route the control signal to another transistor because many such logic signal routing between different devices of the device layer are done through the corresponding interconnect features (paragraph 68) and numerous configurations and variations will be apparent in light of this disclosure (paragraph 33).
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Regarding claim 6.
Majhi in view of Bohr teaches the structure of claim 1.
Bohr teaches the at least one source/drain region (fig 1a:104,paragraph 36) in the transistor region (fig 1a;106;paragraph 36) without power (dummy) (fig 1c;paragraph 36-37).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to comprise source/drain regions without power in order for there to be an interface between the source and the contact where voltage can be supplied to the transistor and thereby be controlled.
Regarding claim 7.
Majhi in view of Bohr teaches the structure of claim 1.
Majhi teaches the first metal layer (fig 2:114-3;paragraph 73) is positioned on a topside (fig 2:110;paragraph 68) of the transistor region (fig 2:106;paragraph 74), and wherein the second metal layer (fig 2:124a’;paragraph 55) is positioned on a backside (fig 2:120;paragraph 55) of the transistor region (fig 2:106;paragraph 34).
Regarding claim 9.
Majhi in view of Bohr teaches the structure of claim 1.
Majhi teaches at least one via between the first wire (fig 2:114-3;paragraph 72) and the first transistor (fig 2:104d;paragraph 68).
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Regarding claim 21.
Majhi in view of Bohr teaches the structure of claim 1.
Bohr teaches the first wire (fig 1c:128;paragraph 37) is connected to the second wire (fig 1b:130,paragraph 37) in at least one inactive transistor (dummy gate) (fig 1a:102;paragraph 47) adjacent to the first side of the first transistor (annotated fig 1a:106;paragraph 33, the at least one inactive transistor (dummy gate) (fig 1a:102;paragraph 37) having an inactive gate (fig 1c:134;paragraph 40) and at least one inactive source/drain region (fig 1c:104;paragraph 37).
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Claim(s) 10, 11, 12, 22, 13, 14, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Majhi (US 2023/0197612)
Regarding claim 10.
Majhi teaches an apparatus, comprising: a first transistor (fig 2:104d;paragraph 68) formed within a transistor region (fig 2:106;paragraph 68) of an integrated circuit (fig 2:100;paragraph 68); a first metal layer located (fig2:112;paragraph 38) above the transistor region (fig 2:106;paragraph 68) in a vertical dimension (fig 2:z) perpendicular to the transistor region (fig 2:106;paragraph 68) (fig 2); a second metal layer (fig 2:122;paragraph 41) located below the transistor region (fig 2:106;paragraph 68) in the vertical dimension (fig2:z); a first wire (fig 2:114-3;paragraph 73) located in the first metal layer (fig 2:112; paragraph 38), the first wire (fig 2:114-3;paragraph 73) being connected to a signal input of the first transistor (fig 2:104d;paragraph 68); a second wire (fig 2:124a;paragraph 56) located in the second metal layer (fig2:122;paragraph 56), at least [one] via structure (fig 2:130a2,paragraph 72) connecting the first wire (fig 2:114-3;paragraph 73) to the second wire (fig 1:124a;paragraph 56), the at least [one] via structure (fig 2:130a2;paragraph 72) (fig 1b,2) being positioned on the first side of the first transistor (fig 2:104d;paragraph 68); and wherein the at least [one] via structure (fig 2:130a2;paragraph 72) between the first metal layer (fig 2:114-3;paragraph 73) and the second metal layer (fig 1:124a;paragraph 56); and a control signal routed to the signal input of the first transistor (fig 2:104d;paragraph 68), wherein the control signal is routed through the second wire (fig 1:124a,paragraph 56), […] through the at least [one] via structure (fig 2:130a2;paragraph 72), and through the first wire (fig 2:114-3;paragraph 73) to the signal input of the first transistor (fig 2:104d;paragraph 68).
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Majhi does not teach that the control signal is routed to pass below the first transistor in the vertical dimension.
Majhi teaches wherein the second wire (fig 2:124;paragraph 56) passes below [a] transistor (fig 2:104c;paragraph 68) in the vertical dimension (fig 2:z) from a first side of [the] (fig 2:104c;paragraph 68) to a second side of the first transistor (fig 2:104c;paragraph 68) in a horizontal dimension (fig 2:x) perpendicular to the vertical dimension (fig 2:z);
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to route the control signal to another transistor because many such logic signal routing between different devices of the device layer are done through the corresponding interconnect features (paragraph 68) and numerous configurations and variations will be apparent in light of this disclosure (paragraph 33).
Majhi does not teach the at least one via structure comprises at least two via structures.
Bohr teaches at least two via structures (fig 1c:136;paragraph 40) connecting the first wire (fig 1c:128;paragraph 37) to the second wire (fig 1c:130;paragraph 37), the at least two via structures (fig 1c:136;paragraph 40) being positioned on the first side of the first transistor (fig 1a,1b:106;paragraph 33), wherein the at least two via structures (fig 1c:136;paragraph 40) are spaced apart (fig 1c:paragraph 33) in the horizontal dimension between the first metal layer (fig 1c:128;paragraph 37) and the second metal layer (fig 1c:130;paragraph 37), in parallel from the first wire (fig 1c:128;paragraph 37) to the second wire (fig 1c:130;paragraph 40)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide at least two via structure in order to reduce the resistance.
Regarding claim 11.
Majhi in view of Bohr teaches the structure of claim 10.
Majhi teaches a second transistor (fig 2:104a;paragraph 68) formed within the transistor region (fig 2:106;paragraph 68) on the second side of the first transistor (fig 2:104d;paragraph 68), wherein the control signal is routed from a signal output of the second transistor (fig 2:104a;paragraph 68), through the at least [one] via structure (fig 2:124a’,130;paragraph 70), and to the signal input of the first transistor (fig 2:104d;paragraph 68) .
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Bohr teaches at least two via structures (fig 1c:136: paragraph 40)
Regarding claim 12
Majhi in view of Bohr teaches the structure of claim 10.
Bohr teaches the at least one two via structures (fig 1c:136;paragraph 40) include at least one source/drain region (fig 1a,c:104;paragraph 36) in the transistor region (fig 1a;paragraph37) and one or more via connections (fig 1c:136;paragraph 40) between the at least one source/drain region and thefirst (fig 1c:128;paragraph 37) and the second (fig 1b:130;paragraph 37) wires.
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It would have been obvious to one of ordinary skill in the art for the via to comprise inactive doped regions in order for there to be an interface between the source and the contact where voltage can be supplied to the transistor and thereby be controlled.
Regarding claim 22.
Majhi teaches the control signal is routed (fig 2) through the [via] (fig 2:130;paragraph 74)
Bohr teaches the [via] is through the at least one source/drain region in the transistor region (annotated fig 1a,1b;paragraph 37,40)
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Regarding claim 13.
Majhi in view of Bohr teaches the structure of claim 10.
Bohr teaches the at least two via structure (fig 1c:136;paragraph 40) are spaced apart in the horizonal dimension and electrically separated (fig 1b:105;paragraph 34) between the first wire (fig 1c:128;paragraph 37) and the second wire (fig 1b:130;paragraph 37).
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Regarding claim 14.
Majhi in view of Bohr teaches the structure of claim 10.
Bohr teaches the at least two via structures (fig 1c:136,paragraph 40) are connected together in the first metal layer (fig 1c:132,128;paragraph 39).
Regarding claim 15.
Bohr teaches the at least two via structures (fig 1c:136;paragraph 40) is located in an inactive (dummy) portion of the apparatus (paragraph 37).
Claim(s) 16, 17, 18, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Majhi (US 2023/0197612) in view of Bohr (US 2019/0378790) in view of Wei (US 2023/0207465)
Regarding claim 16.
Majhi teaches an apparatus, comprising: a transistor region (fig 1a:106;paragraph 36) of an integrated circuit (fig 1a:100;paragraph 34) (fig 2); a first transistor (fig 2:104d;paragraph 68) located in the transistor region (fig 2:106;paragraph 68); a second transistor (fig 2:104a;paragraph 68) located in the transistor region (fig 2:106;paragraph 68), the second transistor (fig 2:104a;paragraph 68) being located on a first side of the first transistor (fig 2:104d;paragraph 68) in a horizontal dimension (fig 2:x) parallel to the transistor region (fig 2:106;paragraph 68); a first metal layer (fig 1a:112;paragraph 38) located above the transistor region (fig 2:106;paragraph 68) in a vertical dimension (fig 2:z) perpendicular to the transistor region (fig 2:106;paragraph 68); a second metal layer (fig 1:122;paragraph 41) located below the transistor region (fig 2:106;paragraph 68) in the vertical dimension (fig 2:z); a first connection (fig 2:139;paragraph 69) between a signal input of the first transistor (fig 2:104d;paragraph 68) and a first wire (fig 2:114-3;paragraph ) located in the first metal layer (112) (see annotated figure 2); a second connection between the second transistor (fig 2:104a;paragraph 68) and a second wire (fig 1:124a;paragraph 55) located in the second metal layer (fig 2:122;paragraph 41) […]; at least one via structure (fig 2:130a2;paragraph 72) connecting the first wire (fig 2:114-3;paragraph 73) to the second wire (fig 2:124;paragraph 43), the at least one via structure (fig 2:130a2;paragraph 72) being positioned […] on a second side of the first transistor (fig 2:104b;paragraph 68) in the horizontal dimension (fig 2:x); and a control signal routed from the second transistor (fig 2:104a;paragraph 68) to the first transistor (fig 2:104d;paragraph 68) that goes from the second transistor (fig 2:104a;paragraph 68) to the second wire through the second connection, from the second wire (fig 1:124a;paragraph 55) to the at least one via structure (fig 2:130a2;paragraph 72), from the at least one via structure (fig 2:130a2;paragraph 72) to the first wire (fig 2:114-3;paragraph 73), and from the first wire (fig 2:114-3;paragraph 73) to the first transistor (fig 2:104d;paragraph 68) through the first connection (fig 1b,2) (paragraph 68-74).
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Majhi does not teach that the control signal is routed to pass below the first transistor in the vertical dimension.
Majhi teaches that the control signal is routed to pass below a transistor (fig 2:104c;paragraph 68) in the vertical dimension (fig 2:Y).
It would have been obvious to one of ordinary skill in the art to route the control signal to another transistor because many such logic signal routing between different devices of the device layer are done through the corresponding interconnect features (paragraph 68) and numerous configurations and variations will be apparent in light of this disclosure (paragraph 33).
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Majhi does not teach an inactive cell.
Bohr teaches at least one via structure (fig 1c,102;paragraph 40) connecting the first wire (fig 1c:128;paragraph 39) to the second wire (fig 1c:130; paragraph 37), the at least one via structure (fig 1c:102;paragraph 40) being positioned in an inactive cell (paragraph 37) on a second side of the first transistor (fig 1a:106;paragraph 36) in the horizontal dimension, wherein the at least one via structure (fig 1c:102;paragraph 40) includes at least one source/drain region (fig 1a:104;paragraph 36) in the transistor region (annotated figure 1a).
Note an inactive cell comprises a dummy gate according to applicant’s disclosure (US 2023/0299068 paragraph 67).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to pass the through silicon via through an inactive region in order avoid interference with active device that could be negatively affected by the presence of the via.
Majhi does not teach the components of a transistor.
Wei teaches that a transistor comprises a source region, drain region and a gate region (fig 1a,1b:1050,1052,1004b;paragraph 72)
It would have been obvious to one of ordinary skill in the art for a transistor to comprise the components of a transistor in order for voltage to be controlled by the transistor
Regarding claim 17.
Majhi in view of Bohr teaches the structure of claim 16.
Majhi teaches the first transistor (fig 2:104d;paragraph 68) is connected to additional wiring (fig 2:114-2,124a2;paragraph 72) in the first metal layer (fig 2:112;paragraph 56) and the second metal layer (fig 1:122;paragraph 56).
Wei teaches that a transistor comprises a source region, drain region and a gate region (fig 1a,1b:1050,1052,1004b;paragraph 72)
Regarding claim 18.
Majhi in view of Wei teaches elements of the claim 16 above.
Bohr teaches the at least one via structure (fig 1c:102;paragraph 37) includes one or more via connections (fig 1c:136;paragraph 40) between the first wire (fig 1c:128;paragraph 39) and the second wire (fig 1c:130; paragraph 39).
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It would have been obvious to one of ordinary skill in the art for the via to comprise inactive doped regions in order for there to be an interface between the source and the contact where voltage can be supplied to the transistor and thereby be controlled.
Regarding claim 19.
Majhi in view of Wei teaches elements of the claim 16 above.
Bohr teaches the at least one via structure (fig 1c:102;paragraph 40) spaced apart in the horizontal dimension includes two or more via structures (fig 1c:136;paragraph 40) spaced apart in the horizontal dimension (annotated figure 1c) and connected in parallel between the first wire (fig 1c:128;paragraph39) and the second wire (fig 1c:130;paragraoh 40) the two or more via structures (fig 1c:136;paragraph 40) (see annotated figure 1c) being located in an inactive (dummy) portion of the transistor (fig 1c;paragraph 37-38). Wherein the [via structure] is in parallel from the first wire (fig 1c:128;paragraph 39) to the second wire (fig 1c:130;paragraph39) through the at least two via structures (see annotated fig 1c)
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide two vias in parallel connecting the first and second wire in order to reduce the resistance of the connection.
Regarding claim 20.
Majhi in view of Bohr teaches the structure of claim 16.
Majhi teaches the second connection includes at least one via (139) between the second wire (fig 2:124a;paragraph 43) and the signal output of second transistor (fig 2:104a;paragraph 68).
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Response to Arguments
Applicant's arguments filed 8/15/2025 have been fully considered but they are not persuasive.
The applicant argues that Bohr does not teach a signal path through at least one source/drain region.
The applicant is incorrect, the applicant will note figure 1a, which shows the via 102 passing through the source/drain region of an inactive transistor
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The applicant will further note that figure 1c shows the via structures to be passing through the source/drain region, which comprises semiconductor fins.
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Figure 1c also illustrates at least two via structures (via 102 comprises a first via structure 134 and second structures 136) that are separated by dielectric material (105) in a horizontal direction, and electrically connect the first and second wires in parallel.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817