DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/23/2026 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 11-14, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi (U.S. PG Pub No US2016/0105967A1) (of record).
Regarding claim 1, Choi teaches a method of manufacturing a component carrier [see title, 0042], the method comprising:
providing a core (lower 121) fig. 6 [0060], the core (lower 121) (121 being an insulating core of material [0060]) having at least one through hole (lower 125 through lower 121) fig. 7 [0059], wherein the at least one through hole (lower 125) extends entirely through the core (lower 121);
then arranging at least one carrier plate (comprising lower 140) fig. 8 [0062] (acting as a supportive/carrying plate) in the at least one through hole (125), forming a hybrid core (140-material hybrid with 121 material) [0023, 0028];
thereafter forming a stack (upper stack of upper 122, upper 126) figs. 9-10 [0063-0065, 0069] directly over the entire hybrid core (lower 140 with lower 121), wherein the stack (upper 122, upper 126) comprises at least one electrically conductive layer structure (upper 126; formed of conductive metal [0069]) and at least one electrically insulating layer structure (upper 122; formed of insulating material [0068]);
thereafter entirely removing [see fig. 11, 0070-0071] the at least one carrier plate (lower 140) from the stack (upper 122 with upper 126) (lower 140 entirely separated [0070-0071] from upper stack comprising upper 122 and upper 126).
Regarding claim 2, Choi teaches the method [see title, 0042] of claim 1. Choi also teaches wherein a plurality of carrier plates (at least 4 110’s) fig. 10 [0025, 0055] are embedded in the core (lower 121) fig. 6 [0060].
Regarding claim 3, Choi teaches the method [see title, 0042] of claim 2. Choi also teaches wherein two carrier plates (left, right 110) fig. 10 [0025, 0055] of the plurality of carrier plates (at least 4 110s) are separated (laterally) by a portion of the core (comprising lower 121) fig. 10 [0060].
Regarding claim 4, Choi teaches the method [see title, 0042] of claim 1. Choi also teaches wherein the at least one carrier plate (comprising lower 140) fig. 8 [0062] is attached to the core (comprising lower 121) fig. 10 [0060] (at least in part) by an adhesive (comprising 312 adhered to 121 and 140) fig. 9 [0044].
Regarding claim 5, Choi teaches the method [see title, 0042] of claim 1. Choi also teaches wherein the core (121) fig. 6 [0060] and the at least one carrier plate (comprising lower 140 and 110s) fig. 8 [0055, 0062] form part of a panel (solid panel shown in fig. 10), by means of which a plurality of component carriers (supporting devices 150s as shown in fig. 10 onwards) can be manufactured.
Regarding claim 6, Choi teaches the method [see title, 0042] of claim 1. Choi also teaches wherein the at least one carrier plate (comprising lower 140 and 110s) fig. 8 [0055, 0062] comprises a seed layer (formed from 310 base), which is configured to (structurally) facilitate the formation of the stack (comprising upper 122 with upper 126) figs. 9-10 [0063-0065, 0069] on (supported by) the (bottom of) at least one carrier plate (comprising lower 110, 140) (by facilitating formation of upper 122, lower upper bulk material [0065-0069]).
Regarding claim 11, Choi teaches the method [see title, 0042] of claim 1. Choi also teaches wherein the method comprises surface mounting a component (upper 150) fig. 10 [0061-0065] on the (supported by bottom of) stack (comprising upper 122 with upper 126) figs. 9-10 [0063-0065, 0069] before removing [see fig. 11, 0069-0070] the at least one carrier plate (comprising upper 140) fig. 11 [0055, 0062].
Regarding claim 12, Choi teaches the method [see title, 0042] of claim 11. Choi also teaches wherein the method comprises overmolding (with upper 122 material) fig. 10 [0066-0067] the component (upper 150) fig. 10 [0061-0063] (in excess encapsulant 122) before removing the at least one carrier plate (comprising lower 140) fig. 11 [0055, 0062] [see fig. 11, 0070-0071].
Regarding claim 13, Choi teaches the method [see title, 0042] of claim 1. Choi also teaches wherein the method comprises exposing (top) part [see fig. 12, 0068] of an electrically conductive layer (312) fig. 11 [0044] on the at least one carrier plate (comprising lower 140 and 110s) fig. 8 [0055, 0062] by patterning (removing lower 122-pattern from upper stack) an electrically insulating layer (lower 122) fig. 12 [0068] on the (bottom of) electrically conductive layer (312 in fig. 11).
Regarding claim 14, Choi teaches the method [see title, 0042] of claim 13. Choi also teaches wherein the method comprises applying electrically conductive material (131) fig. 11 [0032] selectively on (supported by) the exposed part of the electrically conductive layer (312) fig. 11 [0044].
Regarding claim 21, Choi teaches a method of manufacturing a component carrier [see title, 0042], the method comprising:
providing a core (lower 121) fig. 6 [0060], the core (lower 121) having at least one through hole (lower 125 through lower 121) fig. 7 [0059] entirely through the core (lower 121);
then arranging at least one carrier plate (comprising lower 140) fig. 8 [0062] (acting as a supportive/carrying plate) in the at least one through hole (125), forming a hybrid core (140-material hybrid with 121 material) [0023, 0028];
thereafter forming a stack (upper stack of upper 122, upper 126) figs. 9-10 [0063-0065, 0069] directly over the entire hybrid core (lower 140 with lower 121), wherein the stack (upper 122, upper 126) comprises at least one electrically conductive layer structure (upper 126; formed of conductive metal [0069]) and at least one electrically insulating layer structure (upper 122; formed of insulating material [0068]);
thereafter (entirely) removing [see fig. 11, 0070-0071] the at least one carrier plate (lower 140) from the stack (upper 122 with upper 126) (lower 140 entirely separated [0070-0071] from upper stack comprising upper 122 and upper 126).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (U.S. PG Pub No US2016/0105967A1) (of record), as applied in claim 1 above, in view of Fang (U.S. PG Pub No US2018/0061805A1) (of record).
Regarding claim 7, Choi teaches the method [see title, 0042] of claim 1. However, Choi does not explicitly disclose wherein the stack (comprising upper 122 with upper 126) figs. 9-10 [0063-0065, 0069] is configured as a redistribution layer for a component mounted to the stack (comprising upper 122 with upper 126) figs. 9-10 [0063-0065, 0069].
Fang teaches a method [see title, abstract, 0002] wherein the stack (14 with 22) fig. 15 [0061, 0072] is configured as a redistribution layer [0072] for a component (12) fig. 15 [0061] mounted to the stack (14 with 22).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Choi with the teachings of Fang such that the stack is configured to support a redistribution layer in order to facilitate well-controlled electrical connections with adjacent conductive structures [0003, 0046], as taught by Fang.
Regarding claim 8, Choi in view of Fang teaches the method [see title, abstract, 0002] of claim 7. Choi in view of Fang (with reference to Fang) also teaches wherein the redistribution layer (comprising conductive material of 14 with 22 stack) fig. 15 [0061, 0072] enlarges the footprint (expands footprint over interconnect structure) of the component (12).
Regarding claim 9, Choi teaches the method [see title, 0042] of claim 1. However, Choi does not explicitly disclose wherein the at least one carrier plate (comprising lower 140) fig. 8 [0062] comprises a plastic plate.
Fang teaches a method [see title, abstract, 0002] wherein the at least one carrier plate (62) fig. 9 [0058] comprises a plastic plate [0059].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Choi with the teachings of Fang such that the carrier plate includes a plastic plate [0059] in order to facilitate strong surface bonding with components supported thereon [0059], as taught by Fang.
Regarding claim 10, Choi teaches the method [see title, 0042] of claim 1. However, Choi does not explicitly disclose wherein the at least one carrier plate (comprising lower 140) fig. 8 [0062] has a surface roughness Ra of not more than 450 nm (roughness not specified).
Fang teaches a method [see title, abstract, 0002] wherein the at least one carrier plate (62) fig. 9 [0058] has a surface roughness Ra of not more than 450 nm (roughness of 64 [0075], which conforms to surface of 62 [0058-0060], may be about 0.01 micron = 10 nm [0075] < 450 nm).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Choi with the teachings of Fang such that the carrier plate is provided with a surface roughness [0055, 0075] on the order of tens of nanometers in order to improve surface adhesion between adjacent layers of the stacked configuration [0055], as taught by Fang.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (U.S. PG Pub No US2016/0105967A1) (of record), as applied in claim 1 above, in view of Yu (U.S. PG Pub No US2017/0170415A1).
Regarding claim 22, Choi teaches the method [see title, 0042] of claim 1. However, Choi does not explicitly disclose wherein the at least one carrier plate (comprising lower 140) fig. 8 [0062] comprises a release layer and/or a detachable interface configured to remove the stack (upper stack of upper 122, upper 126) figs. 9-10 [0063-0065, 0069] from the at least one carrier plate (140).
Yu teaches a method [see figs. 5-6, 0054-0055] wherein the at least one carrier plate (comprising 1) fig. 6 [0060] comprises a release layer (2) fig. 6 [0061] configured to remove the stack (upper stack of upper 4, 5, 6) fig. 5 [0055] from the at least one carrier plate (1) [see fig. 6, 0061, 0065].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Choi such that the carrier plate is provided with a release layer [0060-0061] in order to enhance separability between the carrier plate and upper stack layers [0061] as well as reduce damage associated with the separation process [0061], as taught by Yu.
Response to Arguments
Applicant's arguments filed 06/23/2026 with respect to claims 1-14 and 21 have been fully considered but they are not persuasive.
With respect to Applicant’s argument(s) that “According to Choi, the cavity 125 extends only through the insulating layer 121 and does not extend through the carrier board 310. See, e.g., Choi, Fig. 7. Choi does not disclose at least one through hole, wherein the at least one through hole extends entirely through the core.” Examiner agrees that the through hole 125 extends only entirely through layer 121, hence the new grounds of rejection for claims 1 and 21 in view of Choi relies upon a reinterpretation of the claimed “core” to be only layer 121.
With respect to Applicant’s argument that “Choi's bonding layer 140 is not a carrier plate arranged in a through hole to form a hybrid core; it is an adhesive used to mount device 150 in cavity 125” neither the amended claims nor the instant application provide any insight into what is meant by the term “hybrid core”, and what limitation(s) that this “hybrid” term imposes on the claims that prevents choosing element 140 [see fig. 10, 0062] of Choi as a part of the claimed hybrid core. For the purposes of Examination, Examiner has interpreted “hybrid core” as (140-material hybrid with 121 material) fig. 10 [0023, 0028 Choi] – that being the combination of the core 121 with 140, formed as a hybrid of these two materials. In order to definitively overcome this interpretation, Applicant would need to place additional limitations on the term “hybrid core” that definitively excludes consideration of layer 140 as a component of said hybrid core.
With respect to Applicant’s argument(s) that “Choi also does not disclose thereafter forming a stack directly over the entire hybrid core. The Office Action maps the claimed stack to Choi's lower device/electrode/insulating/metal structures, including device 150, electrodes 151, second insulating layer 122, and metal layer 126. But Choi describes device 150 as an electronic device mounted on bonding layer 140 and disposed in cavity 125, not as a layer structure of a stack formed directly over an entire hybrid core…” it is noted that the “stack” of Choi has been reinterpreted as the upper stack comprising (upper 122, upper 126) figs. 9-10 [0063-0065, 0069] – rendering particular arguments with respect to layer(s) 150 and the stack moot. Further, it is emphasized that the positions of core layer 121 and carrier plate 40 have been reinterpreted as corresponding to the lower versions of these components shown in the method of Choi such that the upper 122, upper 126 stack layers are formed “directly over” the hybrid core.
Applicant’s arguments with respect to claim(s) 22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form (of record) are considered relevant to the present disclosure because they all feature plates embedded in and removed from core material.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892
07/04/2026
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