DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
2. The Amendments filed February 2nd, 2026 are noted in response to the Non-Final Office Action mailed 10/31/2025 are noted.
Applicant’s amendments to the claims are noted.
3. Claims 15-20 are now canceled; Claim 21 is newly-added; Claims 1-14 and 21 remain pending in the application.
4. Claims 1-14 and 21 have been fully considered in examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 11-14, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi (U.S. PG Pub No US2016/0105967A1) (of record).
Regarding claim 1, Choi teaches a method of manufacturing a component carrier [see title, 0042], the method comprising:
providing a core (310 with upper 121) fig. 6 [0060], the core (310 with upper 121) having at least one through hole (upper 125 through upper 121) fig. 7 [0059];
then arranging at least one carrier plate (comprising upper 140) fig. 8 [0062] in the at least one through hole (125);
thereafter forming a stack (comprising lower 150-151 stacked with lower 122 with lower 126) figs. 9-10 [0063-0065, 0069] (lower 150-151 formed in fig. 9, lower 122 and lower 126 formed in fig. 10 – after upper 140 formed in fig. 8) on (supported by bottom of) the at least one carrier plate (upper 140), wherein the stack (lower 150-151 with lower 122 with lower 126) comprises at least one electrically conductive layer structure (lower 126; formed of conductive metal [0069]) and at least one electrically insulating layer structure (lower 122; formed of insulating material [0068]);
thereafter entirely removing [see fig. 11, 0070-0071] the at least one carrier plate (upper 140) from the stack (comprising lower 150-151 with lower 122 with lower 126) (upper 140 entirely separated [0070-0071] from lower stack comprising lower 150-151, lower 122, and lower 126).
Regarding claim 2, Choi teaches the method [see title, 0042] of claim 1. Choi also teaches wherein a plurality of carrier plates (at least 4 110’s) fig. 10 [0025, 0055] are embedded in the core (310 with upper 121) fig. 6 [0060].
Regarding claim 3, Choi teaches the method [see title, 0042] of claim 2. Choi also teaches wherein two carrier plates (left, right 110) fig. 10 [0025, 0055] of the plurality of carrier plates (at least 4 110s) are separated (laterally) by a portion of the core (comprising upper 121) fig. 10 [0060].
Regarding claim 4, Choi teaches the method [see title, 0042] of claim 1. Choi also teaches wherein the at least one carrier plate (comprising upper 140) fig. 8 [0062] is attached to the core (comprising 121) fig. 10 [0060] (at least in part) by an adhesive (lower 140 material) fig. 9 [0062].
Regarding claim 5, Choi teaches the method [see title, 0042] of claim 1. Choi also teaches wherein the core (310 with 121) fig. 6 [0060] and the at least one carrier plate (comprising upper 140 and 110s) fig. 8 [0055, 0062] form part of a panel (solid panel shown in fig. 10), by means of which a plurality of component carriers (supporting devices 150s as shown in fig. 10 onwards) can be manufactured.
Regarding claim 6, Choi teaches the method [see title, 0042] of claim 1. Choi also teaches wherein the at least one carrier plate (comprising upper 140 and 110s) fig. 8 [0055, 0062] comprises a seed layer (formed from 310 base), which is configured to (structurally) facilitate the formation of the stack (comprising lower 150-151 stacked with lower 122 with lower 126) figs. 9-10 [0063-0065, 0069] on (supported by) the (bottom of) at least one carrier plate (comprising upper 110, 140) (by facilitating formation of lower 150/151, lower 122, lower 126 bulk material [0065-0069]).
Regarding claim 11, Choi teaches the method [see title, 0042] of claim 1. Choi also teaches wherein the method comprises surface mounting a component (upper 150) fig. 10 [0061-0065] on the (supported by top of) stack (comprising lower 150-151 stacked with lower 122 with lower 126) figs. 9-10 [0063-0065, 0069] before removing [see fig. 11, 0069-0070] the at least one carrier plate (comprising upper 140) fig. 11 [0055, 0062].
Regarding claim 12, Choi teaches the method [see title, 0042] of claim 11. Choi also teaches wherein the method comprises overmolding (with upper 122 material) fig. 10 [0066-0067] the component (upper 150) fig. 10 [0061-0063] (in excess encapsulant 122) before removing the at least one carrier plate (comprising upper 140) fig. 11 [0055, 0062] [see fig. 11, 0070-0071].
Regarding claim 13, Choi teaches the method [see title, 0042] of claim 1. Choi also teaches wherein the method comprises exposing part [see fig. 12, 0068] of an electrically conductive layer (upper 126) fig. 10 [0069] on the at least one carrier plate (comprising upper 140 and 110s) fig. 8 [0055, 0062] by patterning an electrically insulating layer (upper 122) fig. 12 [0068] on the (bottom of) electrically conductive layer (126 in fig. 11).
Regarding claim 14, Choi teaches the method [see title, 0042] of claim 13. Choi also teaches wherein the method comprises applying electrically conductive material (137 via fill [0080]) fig. 14 [0080] selectively on the exposed part of the electrically conductive layer (etched sidewalls of upper 126).
Regarding claim 21, Choi teaches a method of manufacturing a component carrier [see title, 0042], the method comprising:
providing a core (upper 121) fig. 6 [0060], the core (upper 121) having at least one through hole (upper 125 through upper 121) fig. 7 [0059] entirely (vertically) through the core (upper 121);
then arranging at least one carrier plate (comprising upper 140) fig. 8 [0062] in the at least one through hole (upper 125);
thereafter forming a stack (comprising lower 150-151 stacked with lower 122 with lower 126) figs. 9-10 [0063-0065, 0069] (lower 150-151 formed in fig. 9, lower 122 and lower 126 formed in fig. 10 – after upper 140 formed in fig. 8) on (supported by bottom of) the at least one carrier plate (upper 140), wherein the stack (lower 150-151 with lower 122 with lower 126) comprises at least one electrically conductive layer structure (lower 126; formed of conductive metal [0069]) and at least one electrically insulating layer structure (lower 122; formed of insulating material [0068]);
thereafter removing [see fig. 11, 0070-0071] the at least one carrier plate (upper 140) from the stack (comprising lower 150-151 with lower 122 with lower 126) (upper 140 entirely separated [0070-0071] from lower stack comprising lower 150-151, lower 122, and lower 126).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (U.S. PG Pub No US2016/0105967A1) (of record), as applied in claim 1 above, in view of Fang (U.S. PG Pub No US2018/0061805A1) (of record).
Regarding claim 7, Choi teaches the method [see title, 0042] of claim 1. However, Choi does not explicitly disclose wherein the stack (comprising lower 150-151 stacked with lower 122 with lower 126) figs. 9-10 [0063-0065, 0069] is configured as a redistribution layer for a component mounted to the stack (comprising lower 150-151 stacked with lower 122 with lower 126) fig. 10 [0063-0065, 0069].
Fang teaches a method [see title, abstract, 0002] wherein the stack (14 with 22) fig. 15 [0061, 0072] is configured as a redistribution layer [0072] for a component (12) fig. 15 [0061] mounted to the stack (14 with 22).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Choi with the teachings of Fang such that the stack is configured to support a redistribution layer in order to facilitate well-controlled electrical connections with adjacent conductive structures [0003, 0046], as taught by Fang.
Regarding claim 8, Choi in view of Fang teaches the method [see title, abstract, 0002] of claim 7. Choi in view of Fang (with reference to Fang) also teaches wherein the redistribution layer (comprising conductive material of 14 with 22 stack) fig. 15 [0061, 0072] enlarges the footprint (expands footprint over interconnect structure) of the component (12).
Regarding claim 9, Choi teaches the method [see title, 0042] of claim 1. However, Choi does not explicitly disclose wherein the at least one carrier plate (comprising upper 140) fig. 8 [0062] comprises a plastic plate.
Fang teaches a method [see title, abstract, 0002] wherein the at least one carrier plate (62) fig. 9 [0058] comprises a plastic plate [0059].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Choi with the teachings of Fang such that the carrier plate includes a plastic plate [0059] in order to facilitate strong surface bonding with components supported thereon [0059], as taught by Fang.
Regarding claim 10, Choi teaches the method [see title, 0042] of claim 1. However, Choi does not explicitly disclose wherein the at least one carrier plate (comprising upper 140) fig. 8 [0062] has a surface roughness Ra of not more than 450 nm (roughness not specified).
Fang teaches a method [see title, abstract, 0002] wherein the at least one carrier plate (62) fig. 9 [0058] has a surface roughness Ra of not more than 450 nm (roughness of 64 [0075], which conforms to surface of 62 [0058-0060], may be about 0.01 micron = 10 nm [0075] < 450 nm).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Choi with the teachings of Fang such that the carrier plate is provided with a surface roughness [0055, 0075] on the order of tens of nanometers in order to improve surface adhesion between adjacent layers of the stacked configuration [0055], as taught by Fang.
Response to Arguments
Applicant's arguments filed 02/02/2026 have been fully considered but they are rendered largely moot by a reinterpretation of the claimed “stack” to correspond to “lower 150-151 stacked with lower 122 with lower 126” fig. 10 [0063-0065, 0069], which are formed in figs. 9-10, after upper 140 is formed in fig. 8, and are “on” carrier plate the at least one carrier plate (upper 140) in the sense that they are “supported by” the bottom surface of 140 in the composite structure of fig. 10. It is noted that this reinterpreted stack explicitly comprises an insulating layer (lower 122) fig. 10 [0066] and a conductive metal layer (lower 126) fig. 10 [0069] – and the carrier plate (upper 140) and stack (lower 150-151 with lower 122 with 126) are entirely removed/ separated from each other in the “removal” step shown in fig. 11 [0070-0071] of Choi.
Further, with respect to Applicant’s argument of newly-added claim 21 that “cavity 125 only penetrates through the first insulating layer 121” – the “core” of claim 21 has been considered as only (upper 121) fig. 6 [0060 Choi] for the purposes of the rejection of claim 21.
Therefore, the claimed invention of claim 1 and claim 21 are held unpatentable under 35 U.S.C. 102 in view of Choi (U.S. PG Pub No US2016/0105967A1) (of record). In order to definitively overcome these interpretations, Applicant would need to place additional limitations on the claimed “carrier plate”, “stack”, and/or “core layer” of claims 1 and 21.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form (of record) are considered relevant to the present disclosure because they all feature plates embedded in and removed from core material.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892
03/09/2026
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892