DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 02/03/2026 have been fully considered but they are not persuasive.
Applicant argues that prior art of record does not teach “a first metal layer having a first thickness, the first thickness excluding any thickness of an adjacent via layer” in conjunction with “a pad metal layer having a second thickness less than the first thickness”.
The applicant in part argues that Swaminathan’s pad 112 together with via 106b, precludes inclusion of via 106 in determining the thickness. The examiner agrees however the first thickness (126) of the first metallization comprising 112 and 106b does not include the thickness of the via 106b, (122), as illustrated fig. 1.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies ( “the first metal layer does not include any vias” and/or “the first metal layer has only one thickness in a vertical direction” and/or “the thickness as measured from a bottom most surface of the first metal layer to the top most surface of the first metal layer, does not include the thickness of any via layer) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant in part argues that Persons of skill in the art would recognize pads and vias are two distinct and different types of interconnects. The examiner agrees that one of ordinary skill in the art before the effective filing date of the claimed invention would recognize pads and vias as two distinct types of interconnects. However distinct and/or recognizable as different does not mean that pads and vias are mutually exclusive features, an interconnect may comprise both the structural and compositional features of a pad and a via. The applicant general defines pads as “lands for soldering component terminations” and vias as “plated holes providing vertical interconnection between layers” the examiner agrees with these definitions. Feature 106A fig. 1 of Swaminathan appears to have both the structure and composition of a “land” and of a “plated hole” while “for soldering component terminations” and “providing vertical interconnection between layers” refence functionality which is met in view of MPEP 2112.01 as the structure and composition is the same as claimed and/or disclosed. IPC-T-50M (See attached) defines Pad as “Land”, Land as “A portion of a conductive pattern usually used for connection and/or attachment of components” under this definition the only structural requirement is that it is part of a conductive pattern. . IPC-T-50M defines Via as “a plated hole that is used as an interlayer connection but is not intended for inserting a component lead or metallic part” under this definition the only structural requirement is that it is a plated hole. Feature 106A fig. 1 of Swaminathan is explicitly referred to as a via and/or is illustrated as having the structure and composition of a plated hole in addition is at least a portion of a conductive pattern as illustrated in fig. 1 the functionality is met under MPEP 2112.01 as it is structurally and compositionally the same and/or capable of the intended function, Thus Feature 106A as defined by IPC-T-50M meets the requirements of being both a pad and a via.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “the pad metal layer is not a via and/or does not include a via”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 and 14-29 are rejected under 35 U.S.C. 103 as being obvious over US 20160044786 A1 Swaminathan et al hereafter “Swaminathan”, in further view of US 20160111378 A1 Chen et al hereafter “Chen”
Regarding claim 1 Swaminathan teaches a die package, comprising:
a die (embodied by “chip package” 202 fig. 2, under broadest reasonable interpretation meets the qualification of being a die);
a package substrate (embodied by “electronic package” 100 fig. 2) comprising:
a first metallization layer (comprising 106B, 106F, 106G and 112s in 102A and 102B fig. 1, illustrated fig. 2 but not labeled), comprising:
a first metal layer having (comprising the plurality of elements 112s and 106Bs fig. 1) a first thickness (126, fig. 1, “15 micrometers” paragraph [0019]), the first thickness excluding any thickness of an adjacent via layer [sufficiently illustrated fig. 1 thickness 126 does not include a thickness of any via layer such as 120 and/or 122],
the first metal layer comprising one or more first metal interconnects (the individual elements of 112 electrically coupled to 106A fig. 1, note the examiner is relying on the embodiment of “one” in “one or more” in this limitation and future limitations);
a pad metallization layer (comprising 106A fig. 1) comprising a first surface (bottom surface) disposed adjacent to the first metallization layer and a second surface (top surface) opposite the first surface, the pad metallization layer comprising:
a pad metal layer (106A fig. 1) having a second thickness (120 fig. 1, “7 micrometers” paragraph [0019]) less than the first thickness [illustrated in fig. 1],
the pad metal layer comprising one or more metal pads adjacent to the second surface and each coupled to a first metal interconnect (112 directly coupled 106A fig. 1) of the one or more first metal interconnects [illustrated in fig. 1, the 112 interconnect directly contacting 106A, note this limitation does not limit the pad metal layer to be coupled to --only one first metal interconnect of the one or more first metal interconnects--]; the die coupled to at least one first metal interconnect of the one or more first metal interconnects in the first metal layer [illustrated fig. 3]; and
one or more external interconnects ( 208 fig. 2 is sufficiently disclosed) each coupled to a metal pad of the one or more metal pads [illustrated in fig. 2 and/or 3, the metal pad directly contacting].
Wherein the pad metal layer is a top-most metal layer of the package substrate [illustrated fig. 1]
Swaminathan does not teach wherein the pad metal layer is the bottom-most metal layer of the package substrate; and the first metallization layer is between the die and the pad metallization layer
Chen teaches a die package (fig. 3) comprising;
a die (101 fig. 3);
a substrate package (200 fig. 3);
a first metallization layer (comprising M1-M3 fig. 3) comprising one or more first metal interconnects (“traces” a central portion of 204, 205, and/or 206 fig. 3, see annotation below met under broadest reasonable interpretation a trace is a specific type of metal interconnect and/or mpep 2112.01 structurally and/or compositionally identical to a metal interconnect);
a pad metal layer ( a central portion of 208 fig. 3, see annotation below, met under MPEP 2112.01 as it is structurally and/or compositionally identical to that of 106 a pad metal layer, and/or disclosed paragraph 0028 and fig. 1 elemental 106 being a metal pads which is disclosed as structurally identical to elements 204, 205, 206, and 208 of fig. 3) that is a bottom-most a metal layer (M4 fig. 3 bottom-most metal layer that is explicitly disclosed as a metal layer) of the package substrate;
the die coupled to at least one first metal interconnect of the one or more first metal interconnects in the first metal layer such that the first metallization layer is between the die and the pad metallization layer [sufficiently illustrated fig. 3].
One or more external interconnects each (109 and/or 105 fig 3) coupled to a metal pad of the one or more metal pads (illustrated fig. 3 109 is electrically and physical coupled to external interconnects 208 and 105 is electrically coupled to external interconnects 208 fig. 3)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to rearrange the die package of Swaminathan in view of the structure and/or arrangement of the die package of Chen such that “the pad metal layer is the bottom-most metal layer of the package substrate” and “the first metallization layer is between the die and the pad metallization layer” for the benefit the flip chip design and/or arrangement which results in a smaller size, greatly reduced inductance and resistive heat, and/or higher-speed [Paragraph 0002 Chen].
PNG
media_image1.png
441
519
media_image1.png
Greyscale
Chen annotated figure 3; highlighting one or more first metal interconnects and a pad metal layer
Regarding claim 2 modified Swaminathan in view of Chen as shown above teaches the die package of claim 1, wherein each metal pad of the one or more metal pads is coupled to an external interconnect of the one or more external interconnects [illustrated in fig. 2 and/or 3, the external interconnect directly contacting].
Regarding claim 3 modified Swaminathan in view of Chen as shown above teaches the die package of claim 1, wherein:
the first metallization layer further comprises one or more second metal interconnects (112 coupled to 106D and 106E fig. 1); and each of the one or more second metal interconnects are not coupled to a metal pad of the one or more metal pads [note 106D and 106E are not included as part of the one or more metal pads 106A, also the limitation is does not read as --each of the one or more second metal interconnects are not coupled to any metal pads within the device--].
Regarding claim 4 modified Swaminathan in view of Chen teaches the die package of claim 3, wherein:
the one or more first metal interconnects each have a first width (128 fig. 1, “77 micrometers” paragraph [0019]); and
the one or more second metal interconnects each have a second width (144, “50 micrometers” paragraph [0019]) less than the first width.
Regarding Claim 5 modified Swaminathan in view of Chen teaches as shown above the die package of claim 1, wherein a ratio of the first thickness of the first metal layer to the second thickness of the pad metal layer is at least 1.2 [“15 micrometers” and “7 micrometers” a ratio of 2.14 paragraph [0019] sufficiently meets this limitation].
Regarding Claim 6 modified Swaminathan in view of Chen teaches as shown above the die package of claim 1, wherein:
the first thickness of the first metal layer is between twelve (12) micrometers (µm) sixteen (16) µm [“15 micrometers” Paragraph [0019] meets this limitation]; and
“a layer 102A has a thickness 134 of twelve (12) micrometers from a top 136 of the pad 108 to the exterior surface 138 of the electronic package 100” [Fig. 1, Paragraph (0019)].
Swaminathan does not teach the second thickness of the pad metal layer is between ten (10) µm and twelve (12) µm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adjust the 7μm thickness of the pad metal layer in Swaminathan to be between 10μm and 12μm. As set forth in MPEP § 2144.05(II), it is prima facie obvious to optimize a result-effective variable. In this case, the thickness of a metal pad is a known result-effective variable that impacts manufacturability and reliability. This is evidenced by Brown et al. (US 2019/0371744 A1, paragraph [0026]), which teaches that utilizing a thicker conductive pad reduces the aspect ratio of the connecting via, thereby improving manufacturability and reliability. Furthermore, a person of ordinary skill in the art would have been motivated to increase this thickness to more completely fill the bond pad hole, as illustrated by thickness 134 in Figure 1 of Swaminathan. Therefore, adjusting the pad thickness to fall within the claimed range would have been a matter of routine optimization.
Regarding claim 7 modified Swaminathan in view of Chen teaches as shown above the die package of claim 1, Wherein the device includes a pad via layer (the layer comprising 106B and/or 106C fig. 1) comprising one or more pad vias (106B and/or 106C fig. 1) each coupled to a first metal interconnect (the 112 elements directly contacting) of the one or more first metal interconnects and to a metal pad of the one or more metal pads.
Does not teach wherein the pad metallization layer further comprises the pad via layer disposed adjacent to the pad metal layer;
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to duplicate and/or rearrange the Via’s within the device as taught by Swaminathan such that “the pad metallization layer further comprises a pad via layer disposed adjacent to the pad metal layer” and “the pad via layer comprising one or more pad vias each coupled to a first metal interconnect of the one or more first metal interconnects and to a metal pad (106A) of the one or more metal pads” to electrically connect the 106A bond pad to the first interconnects and/or increase the effective height of the device and/or duplication/rearrangement of parts is prima facie type obviousness [see MPEP 2144.04 VI]
Regarding claim 8 modified Swaminathan in view of Chen teaches as shown above the die package of claim 7, wherein the first metallization layer further comprises a first via layer (comprising 106B fig. 1) disposed adjacent to the first metal layer;
the first via layer comprising one or more first vias each coupled to a first metal (112 in 102B and/or 102A) interconnect of the one or more first metal interconnects [illustrated fig. 1].
Regarding claim 9 modified Swaminathan in view of Chen teaches as shown above the die package of claim 8, further comprising:
a second metallization (Comprising 106C and 112 in 102C fig. 1) layer adjacent to the first metallization layer such that the first metallization layer is disposed between the second metallization layer and the pad metallization layer,
the second metallization layer comprising a second metal layer (112 in 102C fig. 1) comprising one or more second metal interconnects.
Regarding claim 10 modified Swaminathan in view of Chen teaches as shown above the die package of claim 8, wherein:
the one or more pad vias have a first height [in view of the 103 obvious statements above the one or more pad vias would have a height equal to 106Bs height 122 fig. 1], the one or more first vias have a second height [122 fig. 1]; and
a third Via height (height of 106F and/or 106G, illustrated in Fig. 1, but not labeled) less than the first height and the second height.
Swaminathan does not teach the second height greater than the first height.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to change the relative size and/or proportion of the first height as Swaminathan teaches such that “the second height greater than the first height” as changes in relative size and/or proportion is prima facie obviousness [see MPEP 2144.04IV A] and/or to reduce the size/height of the device.
Regarding claim 11 modified Swaminathan in view of Chen teaches as shown above the die package of claim 7, wherein the pad via layer does not contain glass material [in view of the modification made above the material is Sufficiently disclosed in Paragraph 0018, the materials are disclosed as nickel and/or copper which are not glass].
Regarding claim 14 modified Swaminathan in view of Chen teaches as shown above the die package of claim 7, wherein:
the first via layer has a third thickness (118 fig. 1, Paragraph 0019 discloses 106B has a top diameter of 49 micrometers); and
the pad via layer has a fourth thickness (in view of the modification as shown above the pad via layer would have the same thickness as 106B).
a fifth thickness of a via (130 fig. 1, Paragraph 0019 discloses top diameter 130 as 22 micrometers)
Swaminathan does not teach the fourth thickness less than the third thickness.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to change relative size/proportion of the fourth thickness of modified Swaminathan such that it is proportional to the fifth thickness such that “the fourth thickness less than the third thickness” as changes in relative size/proportion are prima facie type obviousness [see MPEP 2144.04 IV B].
Regarding claim 15 modified Swaminathan in view of Chen teaches as shown above the die package of claim 14, wherein a ratio of the third thickness of the first via layer to the fourth thickness of the pad via layer is at least 1. [in view of the modification as made in claim 14, the ratio is 49:22 micrometers, a ratio of 2.22, see paragraph 0018].
Regarding claim 16 modified Swaminathan in view of Chen teaches as shown above the die package of claim 14 the third thickness of the first via layer is 49 micrometers, and the fourth thickness of the pad via layer is 22 micrometers (in view of the modification made in claim 14).
Modified Swaminathan does not teach the third thickness of the first via layer is between twenty five (25) µm and forty-five (45) µm; and
the fourth thickness of the pad via layer is between ten (10) µm and fifteen (15) µm.
It would have been obvious to one of ordinary skill in the art to adjust the values of the third thickness and the fourth thickness such that “the third thickness of the first via layer is between twenty five (25) µm and forty-five (45) µm; and the fourth thickness of the pad via layer is between ten (10) µm and fifteen (15) µm” as it is prima facie obviousness to adjust a range or an amount that do not overlap with prior art but are merely close [See MPEP 2144.05].
Regarding claim 17 modified Swaminathan in view of Chen teaches as shown above the die package of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device;
a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a
portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter [Swaminathan disclosed in Paragraph 0032 “personal computers, tablet computers, mobile telephones, personal data assistants, MP3 or other digital music players, wearable devices, Internet of things (IOTS) devices, etc”].
Regarding claim 18 Swaminathan in view of Chen teaches a method of fabricating a die package, comprising:
forming a first metallization layer (comprising, 106B, 106F, 106G and 112s in 102A and 102B fig. 1), comprising:
forming a first metal layer (comprising the plurality of elements 112s and 106B fig. 1) having a first thickness (126, fig. 1, “15 micrometers” paragraph 0019), the first thickness excluding any thickness of an adjacent via layer [sufficiently illustrated fig. 1 thickness 126 does not include a thickness of any via layer such as 120 and/or 122]; and
forming one or more first metal interconnects (the individual elements of 112 electrically coupled to 106A fig. 1, note the examiner is relying on the embodiment of “one” in “one or more” in this limitation and future limitations) in the first metal layer;
forming a pad metallization layer (comprising 106A fig. 1) comprising a first surface (bottom surface) adjacent to the first metallization layer and a second surface (top surface) opposite the first surface, wherein forming the pad metallization layer comprises:
forming a pad metal layer having a second thickness ((120 fig. 1, “7 micrometers” paragraph [0019]) less than the first thickness [illustrated in fig. 1];
forming one or more metal pads (106A fig. 1) in the pad metal layer adjacent to the second surface [illustrated in fig. 1]; and
coupling each metal pad of the one or more metal pads to a first metal interconnect of the one or more first metal interconnects [illustrated in fig. 1 directly coupled to a 112]; coupling a die to at least one first metal interconnect of the one or more first metal interconnects in the first metal layer; and forming one or more external interconnects (302 fig. 3 and/or 208 fig. 2) each coupled to a metal pad of the one or more metal pads [illustrated in fig. 3 and/or 2].
Wherein the pad metal layer is a top-most metal layer of the package substrate [illustrated fig. 1]
Swaminathan does not teach the pad metal layer is the bottom-most metal layer of the package substrate, nor the first metallization layer is between the die and the pad metallization layer
Chen teaches fabricating a die package (fig. 3) comprising;
forming a package substrate (200 fig. 3), comprising
forming a first metallization layer (comprising M1-M3 fig. 3) comprising; a first metal layer (comprising 204, and/or 205, and/or 206 fig. 3)
forming one or more first metal interconnects (“traces” central portion of 204, 205, and/or 206 fig. 3, see annotation below, met under broadest reasonable interpretation a trace is a specific type of metal interconnect and/or mpep 2112.01 structurally and/or compositionally identical to a metal interconnect) in the first metal layer;
forming a pad metallization layer (M4 fig. 3) comprising a first surface (the top surface of M4 fig. 3) adjacent to the first metallization layer (illustrated fig. 3, it is adjacent [“not distance; nearby” Meriam-Webster dictionary]) and a second surface (the bottom surface fig. 3) opposite the first surface [illustrated fig. 3];
Forming a pad metal layer (a central portion of 208 fig. 3 met under MPEP 2112.01 as it is structurally and/or compositionally identical to that of106 a pad metal layer, and/or disclosed paragraph 0028 and fig. 1 elemental 106 being a metal pads which is disclosed as structurally identical to elements 204, 205, 206, and 208 of fig. 3) that is a bottom-most a metal layer (M4 fig. 3 bottom-most metal layer that is explicitly disclosed as a metal layer) of the package substrate;
Coupling each metal pad of the one or more metal pads to a first metal interconnect of the one or more first metal interconnects [illustrated fig. 3 each metal pad are at least electrically coupled, fig. 12A sufficiently illustrates an embodiment in which each metal pad is directly/physically coupled]; coupling a die (101 fig. 3) to at least one first metal interconnect of the one or more first metal interconnects in the first metal layer such that the first metallization layer is between the die and the pad metallization layer [sufficiently illustrated fig. 3].
forming one or more external interconnects each (109 and/or 105 fig 3) coupled to a metal pad of the one or more metal pads (illustrated fig. 3 109 is electrically and physical coupled to external interconnects 208 and 105 is electrically coupled to external interconnects 208 fig. 3)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the process of fabricating the die package of Swaminathan in view of the process of fabrication and/or arranging the die package of Chen such that “the pad metal layer is the bottom-most metal layer of the package substrate” and “the first metallization layer is between the die and the pad metallization layer” for the benefit the flip chip design and/or arrangement which results in a smaller size, greatly reduced inductance and resistive heat, and/or higher-speed [Paragraph 0002 Chen] and/or routine optimization of process stress and/or process thermal expansion and/or to prevent peel-off and/or delamination [Paragraph 0003 Chen] and/or Warpage between the device die and Carrier substrate [fig. 8 Chen].
PNG
media_image1.png
441
519
media_image1.png
Greyscale
Chen Annotated fig. 3; highlighting one or more first metal interconnects and a pad metal layer
Regarding claim 19 modified Swaminathan in view of Chen teaches as shown above the method of claim 18, wherein forming the one or more external interconnects comprises coupling an external interconnect of the one or more external interconnects to each metal pad of the one or more metal pads [illustrated in fig. 3 and/or 2].
Regarding claim 20 modified Swaminathan in view of Chen teaches as shown above the method of claim 18, further comprising:
forming one or more second metal interconnects (112 coupled to 106D and 106E fig. 1 in the first metallization layer; and
not coupling each of the one or more second metal interconnects to a metal pad (106A fig. 1)of the one or more metal pads [illustrated in fig. 1, note 106D and 106E are not included as part of the one or more metal pads 106A, also the limitation is does not read as --each of the one or more second metal interconnects are not coupled to any metal pads within the device--].
Regarding claim 21 modified Swaminathan in view of Chen teaches as shown above the method of claim 20, wherein:
forming the one or more first metal interconnects comprises forming the one or more first metal interconnects each of a first width in the first metal layer (128 fig. 1, “77 micrometers” paragraph [0019]); and
forming the one or more second metal interconnects comprises forming the one or more second metal interconnects each of a second width (144, “50 micrometers” paragraph [0019]) less than the first width in the first metal layer (illustrated fig. 1).
Regarding claim 22 modified Swaminathan in view of Chen teaches as shown above the method of claim 18, wherein forming the device includes forming a pad via layer (the layer comprising 106B and/or 106C fig. 1) comprising one or more pad vias (106B and/or 106C fig. 1) each coupled to a first metal interconnect (the 112 elements directly contacting) of the one or more first metal interconnects and to a metal pad of the one or more metal pads.
Does not teach wherein forming the pad metallization layer further comprises forming the pad via layer disposed adjacent to the pad metal layer;
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to duplicate and/or rearrange the Via’s within the device as taught by Swaminathan such that “forming the pad metallization layer further comprises; forming a pad via layer disposed adjacent to the pad metal layer” and “forming one or more pad vias in the pad via layer each coupled to a first metal interconnect of the one or more first metal interconnects and to a metal pad of the one or more metal pads” to electrically connect the 106A bond pad to the first interconnects and/or increase the effective height of the device and/or duplication/rearrangement of parts is prima facie type obviousness [see MPEP 2144.04 VI].
Regarding claim 23 modified Swaminathan in view of Chen teaches as shown above the method of claim 22, wherein forming the first metallization layer further comprises:
forming a first via layer (106B fig. 1) adjacent to the first metal layer; and
forming one or more first vias each coupled to a first metal interconnect of the one or more first metal interconnects [illustrated in fig. 1].
Regarding claim 24 modified Swaminathan in view of Chen teaches as shown above the method of claim 23, further comprising forming a second metallization layer (comprising 106C and 112 in 102C fig. 1) adjacent to the first metallization layer such that the first metallization layer is disposed between the second metallization layer and the pad metallization layer [illustrated in fig. 1],
wherein forming the second metallization layer comprises forming a second metal layer comprising one or more second metal interconnects [112 in 102C fig. 1].
Regarding claim 25 modified Swaminathan in view of Chen teaches as shown above the method of claim 22, wherein:
forming the first via layer in the first metallization layer comprises forming the first via layer having a third thickness (118 fig. 1, Paragraph 0019 discloses 106B has a top diameter of 49 micrometers); and
forming the pad via layer in the pad metallization layer comprises forming the pad via layer having a fourth thickness (in view of the modification as made in claim 22, 118 fig. 1, Paragraph 0019 discloses 106B has a top diameter of 49 micrometers).
A fifth thickness of a via (130 fig. 1, Paragraph 0019 discloses top diameter 130 as 22 micrometers).
Modified Swaminathan in view of Chen does not teach the fourth thickness is less than the third thickness.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to change relative size/proportion of the fourth thickness of modified Swaminathan such that it is proportional to the fifth thickness such that “the fourth thickness less than the third thickness” as changes in relative size/proportion are prima facie type obviousness [see MPEP 2144.04 IV B].
Regarding Claim 26 modified Swaminathan in view of Chen teaches as shown above the die package of claim 1, wherein:
the one or more first metal interconnects each have a first width (128 fig. 1); and
the one or more metal pads each have a second width (118 fig. 1)
Swaminathan does not teach the second width is greater than the first width.
However, Chen teaches the one or more first metal interconnects each have a first width (see annotation below); and the one or more metal pads each have a second width (see annotation below) greater than the first width [illustrated fig. 3]; and that the size and/or area metal layers impacts warpage of the carrier substrate [Paragraph 0023-0026 and fig. 8].
It would have been obvious to one of ordinary skill in the art before the effective filing date to change the size of one or more metal pads of Swaminathan in view the one or more metal pads of Chen such that “the one or more metal pads each have a second width (see annotation below) greater than the first width [illustrated fig. 3]” as part of routine optimization of the warpage of the carrier substrate and/or conductivity of the one or more metal pads [See 2144.05 II] and/or changes in relative size is prima facie type obviousness [2144.04 IV A.].
PNG
media_image2.png
441
519
media_image2.png
Greyscale
Chen annotated fig. 3: highlight a first width and a second width
Regarding Claim 27 modified Swaminathan in view of Chen as shown above the die package of claim 26;
Swaminathan does not teach the first metallization layer further comprises one or more second metal interconnects; and each of the one or more second metal interconnects are not coupled to a metal pad of the one or more metal pads; and
the one or more second metal interconnects each have a third width less than the first width.
Chen teaches the first metallization layer further comprises one or more second metal interconnects (a right-side portion of 206 and/or 204 fig. 3, see annotation below); and each of the one or more second metal interconnects are not coupled to a metal pad of the one or more metal pads [sufficiently illustrated fig. 3]; and
the one or more second metal interconnects each have a third width less than the first width [sufficiently illustrated fig. 3].
It would have been obvious to one of ordinary skill in the art to select one or more metal interconnection and/or duplicate the metal interconnects structures of Swaminathan in view of the one or more second metal interconnect of Chen such that there are “one or more second metal interconnects; and each of the one or more second metal interconnects are not coupled to a metal pad of the one or more metal pads” to interconnect elements of the device to each other and not the metal pad, and/or duplication of part is prima facie type obviousness [see MPEP 2144.04 VI B].
PNG
media_image3.png
441
519
media_image3.png
Greyscale
Chen Annotated fig. 3; highlighting one or more second metal interconnects
PNG
media_image4.png
441
519
media_image4.png
Greyscale
Chen Annotated fig. 3; highlighting a third width
Regarding Claim 28 modified Swaminathan in view of Chen the method of claim 18, wherein:
forming the one or more first metal interconnects further comprises forming the or more first metal interconnects each of a first width (128 fig. 1); and
forming the one or more metal pads further comprises forming the one or more metal pads each of a second width (118 fig. 1)
Swaminathan does not teach the second width greater than the first width.
However, Chen teaches forming the one or more first metal interconnects each have a first width (see annotation below); and forming the one or more metal pads comprises forming the one or more metal pads each of a second width (see annotation below) greater than the first width [illustrated fig. 3]; and that the size and/or area metal layers impacts warpage of the carrier substrate [Paragraph 0023-0026 and fig. 8].
It would have been obvious to one of ordinary skill in the art before the effective filing date to change the size of one or more metal pads of Swaminathan in view the one or more metal pads of Chen such that “the one or more metal pads each have a second width (see annotation below) greater than the first width [illustrated fig. 3]” as part of routine optimization of the warpage of the carrier substrate and/or conductivity of the one or more metal pads [See 2144.05 II] and/or changes in relative size is prima facie type obviousness [2144.04 IV A.].
PNG
media_image2.png
441
519
media_image2.png
Greyscale
Chen annotated fig. 3: highlight a first width and a second width
Regarding Claim 29 modified Swaminathan in view of Chen teaches as shown above the method of claim 28.
Swaminathan does not teach forming the first metallization layer further comprises forming one or more second metal interconnects in the first metal layer each of a third width less than the first width and each not coupled to a metal pad of the one or more metal pads.
Chen teaches forming the first metallization layer further comprises forming one or more second metal interconnects (a right-side portion of 206 and/or 204 fig. 3, see annotation below) in the first metal layer [illustrated fig. 3] each of a third width [illustrated fig. 3 see annotation below] less than the first width and each not coupled to a metal pad of the one or more metal pads [sufficiently illustrated fig. 3].
It would have been obvious to one of ordinary skill in the art modify the process by forming and/or duplicate the metal interconnects structures of Swaminathan in view of the one or more second metal interconnect of Chen such that there are “forming the first metallization layer further comprises forming one or more second metal interconnects in the first metal layer each of a third width less than the first width and each not coupled to a metal pad of the one or more metal pads.” to interconnect elements of the device to each other and not the metal pad and/or duplication of part is prima facie type obviousness [see MPEP 2144.04 VI B].
PNG
media_image3.png
441
519
media_image3.png
Greyscale
Chen Annotated fig. 3; highlighting one or more second metal interconnects
PNG
media_image4.png
441
519
media_image4.png
Greyscale
Chen Annotated fig. 3; highlighting a third width
Claim 12 are rejected under 35 U.S.C. 103 as being unpatentable over modified Swaminathan in view of Chen as applied the claim above, and further in view of US 20200027728 A1 Wang et al hereafter “Wang”.
Regarding claim 12 modified Swaminathan in view of Chen teaches as shown above the die package of claim 8, wherein:
the pad via layer does not contain glass material [in view of the modification made above the material is Sufficiently disclosed in Paragraph 0018, the materials are disclosed as nickel and/or copper which are not glass].
Swaminathan in view of Chen does not teach the first via layer comprises a glass material.
Wang teaches a via layer (comprising 120 and 135 fig. 1) comprises a glass material (120 figure. 1 paragraph 0044)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select an additional glass material for the first via layer as Wang teaches in the device Swaminathan teach to electrically insulate the via from adjacent conductive structures and/or to reduce parasitic capacitance, and/or it is prima facie obviousness to select a material based on its art recognized suitability for an intended purpose [See MPEP 2144.07].
Claim 13 are rejected under 35 U.S.C. 103 as being unpatentable over modified Swaminathan in view of Chen as applied the claim above, and further in view of Wang and US 20180138127 A1 Lee et al hereafter “Lee”.
Regarding claim 13 modified Swaminathan in view of Chen teaches as shown above the die package of claim 8, wherein:
Modified Swaminathan in view of Chen does not teach the pad via layer comprises a photo-imageable dielectric (PID) layer; and
the first via layer comprises a pre-impregnated glass (PPG) layer.
Lee teaches a photo-imageable dielectric layer (140 fig. 7G) with a via hole (141 fig. 7G) that is filled with a via (142 fig. 7H).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select an additional PID material for the pad via layer as Lee teaches in the device modified Swaminathan in view of Chen teach to electrically insulate the via from adjacent conductive structures and/or to reduce parasitic capacitance, and/or it is prima facie obviousness to select a material based on its art recognized suitability for an intended purpose [See MPEP 2144.07].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a glass material in the first via layer as Wang teaches in the device modified Swaminathan in view of Lee teach to electrically insulate the via from adjacent conductive structures and/or to reduce parasitic capacitance, and/or it is prima facie obviousness to select a material based on its art recognized suitability for an intended purpose [See MPEP 2144.07].
Wang teaches a via layer (comprising 120 and 135 fig. 1) comprises a glass material (120 figure. 1 paragraph 0044)
In view of Wang the limitation “the first via layer comprises a pre-impregnated glass (PPG) layer” is met under broadest reasonable interpretation as the ordinary meaning of pre-impregnated glass is broad enough as to include the product by process in which glass is inserted into the material before curing and in view MPEP 2113.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WCT/Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights