DETAILED ACTION
This action is responsive to communication filed 03/25/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see page 7 paragraph 3, filed 03/25/2026, with respect to the 112(b) rejection of claim 22 have been fully considered and are persuasive. The rejection of office action 02/05/2026 has been withdrawn.
Applicant’s arguments, see page 9 paragraph 2 and page 10 paragraphs 1-6, filed 03/25/2026, with respect to the rejections of claims 1, 3-6, 15, and 18-28 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of a different interpretation of the previously applied references, see rejections below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 15, and 18-28 are rejected under 35 U.S.C. 103 as being unpatentable over Paul (US 10,418,449 B2) in view of Zhang (US 2020/0211902 A1).
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s)
Regarding claim 1, Paul (see, e.g., annotated FIGS. 8 and 8B below) discloses a transistor circuitry comprising:
a first set of nanosheets (see annotated Fig. 8 below: 10 and “first set of nanosheets”) used in an n-type transistor (see annotated Fig. 8B below: 54 and 56; col. 7, lines 21-24: transistors 54 and 56 are n-type SRAM access transistors);
and a second set of nanosheets (see annotated Fig. 8 below: 10 and “second set of nanosheets”) horizontally corresponding to the first set of nanosheets (see annotated Fig. 8B below),
one or more nanosheets of the second set of nanosheets being used in a p-type transistor (see annotated Fig. 8B below: 50 and 52; col. 6, lines 61-67, col. 7, lines 4-5: transistors 50 and 52 define an inverter (i.e. a p-type transistor coupled with a n-type transistor),
wherein a width of the second set of nanosheets is wider than a width of the first set of nanosheets and wherein the one or more nanosheets is a first sub-set of the second set of nanosheets (see annotated Fig. 8 below: “first subset”) and the second set of nanosheets further comprises a second sub-set (see annotated Fig. 8 below: “second subset”),
the p- type transistor has source/drain regions (see annotated Fig. 8 below: 38) formed at two ends of the first sub-set of the second set of nanosheets,
and two ends of the second sub-set of the second set of nanosheets are isolated from the source/drain regions of the p-type transistor (see annotated Fig. 8 below: the second subset depicted in annotated Fig. 8 is isolated from source/drain 38 on both the left and right ends).
Paul fails to disclose: wherein a width of the second set of nanosheets is wider than a width of the first set of nanosheets. However, Zhang disclose a similar nanosheet device comprises nanosheets with different widths. Fig. 1 of Zhang discloses:
wherein a width of the second set of nanosheets (135) is wider than a width of the first set of nanosheets (130).
In view of Zhang, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the nanosheets of Paul with different (i.e. narrow and wide) widths in order to control current flow based on channel length and to control gate dielectric quality (Zhang: paragraph [0017]).
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Regarding claim 3, Paul (see, e.g., annotated Rotated FIG. 8 below) discloses the transistor circuitry of claim 1, wherein:
the first sub-set of the second set of nanosheets is positioned above the second sub-set of the second set of nanosheets (Note: The term “above” is interpreted based on the spatial orientation of the device shown in annotated Rotated Fig. 8 of Paul below).
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Regarding claim 4, Paul (see, e.g., annotated Fig. 8 above) discloses the transistor circuitry of claim 1, wherein:
the first set of nanosheets and the second set of nanosheets have a same number of nanosheets (see annotated Fig. 8 above),
the p-type transistor is a pull-up transistor of a static-random-access memory (SRAM) (col. 7, lines 1-15: “The CFETs 50, 52 may be pull-up transistors of the 6-T SRAM cell.”),
and the n-type transistor is either a pull-down transistor of the SRAM or a pass-gate transistor of the SRAM (col. 7, lines 24-27: "The NSFETs 54, 56 may constitute access transistors of the 6-T SRAM.").
Regarding claim 5, Paul (see, e.g., annotated Fig. 8 above) discloses the transistor circuitry of claim 1, wherein:
the second set of nanosheets has a same number of nanosheets as the first set of nanosheets (see annotated Fig. 8 above).
Regarding claim 6, the combination of Paul and Zhang (see, e.g., annotated Fig. 8 of Paul and annotated Fig. 1 of Zhang below) discloses the transistor circuitry of claim 1, wherein:
the width of the first set of nanosheets is a channel width of the n-type transistor and the width of the second set of nanosheets is a channel width of the p-type transistor (see annotated Figs. 8 and 1 below: “channel widths”).
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Regarding claim 15, Paul (see, e.g., annotated Fig. 8 below) discloses a semiconductor structure comprising:
a first set of nanosheets (see annotated Fig. 8 below: 10 and “first set of nanosheets”) used in an n-type transistor (see annotated Fig. 8B below: 54 and 56; col. 7, lines 21-24: transistors 54 and 56 are n-type SRAM access transistors);
and a second set of nanosheets (see annotated Fig. 8 below: 10 and “second set of nanosheets”) horizontally corresponding to the first set of nanosheets (see annotated Fig. 8B below) and having a first sub-set (see annotated Fig. 8 below: “first subset”) and a second sub-set (see annotated Fig. 8 below: “second subset”) thereof,
wherein the first sub-set of the second set of nanosheets is used in a p-type transistor (see annotated Fig. 8B below: 50 and 52; col. 6, lines 61-67, col. 7, lines 4-5: transistors 50 and 52 define an inverter (i.e. a p-type transistor coupled with a n-type transistor),
and a width of the second set of nanosheets is wider than a width of the first set of nanosheets,
wherein the p-type transistor has source/drain regions formed at two ends of the first sub-set of the second set of nanosheets (see annotated Fig. 8 below: 38),
and wherein two ends of the second sub- set of the second set of nanosheets are covered by a dielectric layer (see annotated Fig. 8 below: 60) and isolated from the source/drain regions of the p-type transistor (see annotated Fig. 8 below: the second subset depicted in annotated Fig. 8 is isolated from source/drain 38 on both the left and right ends).
Paul fails to disclose: a width of the second set of nanosheets is wider than a width of the first set of nanosheets. However, Zhang disclose a similar nanosheet device comprises nanosheets with different widths. Fig. 1 of Zhang discloses:
a width (135) of the second set of nanosheets is wider than a width (130) of the first set of nanosheets.
In view of Zhang, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the nanosheets of Paul with different (i.e. narrow and wide) widths in order to control current flow based on channel length and to control gate dielectric quality (Zhang: paragraph [0017]).
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Regarding claim 18, Paul (see, e.g., annotated Rotated FIG. 8 above) discloses the semiconductor structure of claim 15, wherein:
the first set of nanosheets and the second set of nanosheets have a same number of nanosheets (see annotated Fig. 8 above),
and the first sub-set of the second set of nanosheets is positioned above the second sub-set of the second set of nanosheets(Note: The term “above” is interpreted based on the spatial orientation of the device shown in annotated Rotated Fig. 8 of Paul above).
Regarding claim 19, Paul (see, e.g., FIG. 8) discloses the semiconductor structure of claim 15, wherein:
the first set of nanosheets and the second set of nanosheets are positioned in a same plane (horizontal plane) parallel to each other and separated by a dielectric layer (42).
Regarding claim 20, the combination of Paul and Zhang discloses the semiconductor structure of claim 15, wherein:
the p-type transistor is a pull-up transistor (col. 7, lines 24-27: "The NSFETs 54, 56 may constitute access transistors of the 6-T SRAM.") and the n-type transistor is either a pull-down transistor or a pass-gate transistor (col. 7, lines 24-27: "The NSFETs 54, 56 may constitute access transistors of the 6-T SRAM."),
and wherein the width of the first set of nanosheets is a channel width of the pull-down transistor or the pass-gate transistor and the width of the second set of nanosheets is a channel width of the pull-up transistor (see annotated Figs. 8 and 1 in the rejection of claim 6: “channel widths”).
Regarding claim 21, Paul (see, e.g., annotated FIG. 8 and 8B in the rejection of claim 1) discloses a transistor circuitry comprising:
a first set of nanosheets (see annotated Fig. 8: 10 and “first set of nanosheets”) used in an n-type transistor (see annotated Fig. 8B: 54 and 56; col. 7, lines 21-24: transistors 54 and 56 are n-type SRAM access transistors);
and a second set of nanosheets (see annotated Fig. 8: 10 and “second set of nanosheets”) that has a first sub-set (see annotated Fig. 8: 10 and “first subset”) of nanosheets used in a p-type transistor (see annotated Fig. 8B: 50 and 52; col. 6, lines 61-67, col. 7, lines 4-5: transistors 50 and 52 define an inverter (i.e. a p-type transistor coupled with a n-type transistor));
a second sub-set (see annotated Fig. 8: 10 and “second subset”) of nanosheets underneath the p-type transistor and the first set of nanosheets (see annotated Fig. 8);
and a same number of nanosheets as the first set of nanosheets (see annotated Fig. 8),
wherein a width of the second set of nanosheets is wider than a width of the first set of nanosheets.
Paul fails to disclose: wherein a width of the second set of nanosheets is wider than a width of the first set of nanosheets. However, Zhang disclose a similar nanosheet device comprises nanosheets with different widths. Fig. 1 of Zhang discloses:
wherein a width of the second set of nanosheets (135) is wider than a width of the first set of nanosheets (130).
In view of Zhang, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the nanosheets of Paul with different (i.e. narrow and wide) widths in order to control current flow based on channel length and to control gate dielectric quality (Zhang: paragraph [0017]).
Regarding claim 22, Paul (see, e.g., FIG. 8) discloses the transistor circuitry of claim 21, wherein:
the p-type transistor has source/drain regions (38) formed at two ends of the first sub-set of nanosheets of the second set of nanosheets.
Regarding claim 23, Paul (see, e.g., annotated FIG. 8 in the rejection of claim 15) discloses the transistor circuitry of claim 22, wherein:
two ends of the second sub-set of nanosheets of the second set of nanosheets are covered by a dielectric layer (see annotated Fig. 8: 60) and isolated from the source/drain regions of the p-type transistor (see annotated Fig. 8: the second subset depicted in annotated Fig. 8 is isolated from source/drain 38 on both the left and right ends).
Regarding claim 24, Paul (see, e.g., FIG. 8) discloses the transistor circuitry of claim 21, wherein:
each of the first set of nanosheets are respectively positioned in a same plane (horizontal plane) as each of the second set of nanosheets, parallel to each other,
and separated from each other by a dielectric layer (42).
Regarding claim 25, Paul discloses the transistor circuitry of claim 21, wherein:
the p-type transistor is a pull-up transistor of a static-random-access memory (SRAM) and the n-type transistor is a pull-down transistor of the SRAM (col. 7, lines 10-15).
Regarding claim 26, the combination of Paul and Zhang (see, e.g., annotated Fig. 8 of Paul and annotated Fig. 1 of Zhang in the rejection of claim 6) discloses the transistor circuitry of claim 25, wherein:
the width of the first set of nanosheets is a channel width of the pull-down transistor of the SRAM and the width of the second set of nanosheets is a channel width of the pull-up transistor of the SRAM (see annotated Figs. 8 and 1: “channel widths”).
Regarding claim 27, Paul discloses the transistor circuitry of claim 21, wherein:
the p-type transistor is a pull-up transistor of a static-random-access memory (SRAM) (col. 7, lines 10-15) and the n-type transistor is a pass-gate transistor of the SRAM (col. 7, lines 21-24).
Regarding claim 28, the combination of Paul and Zhang (see, e.g., annotated Fig. 8 of Paul and annotated Fig. 1 of Zhang in the rejection of claim 6) discloses the transistor circuitry of claim 27, wherein:
the width of the first set of nanosheets is a channel width of the pass-gate transistor of the SRAM and the width of the second set of nanosheets is a channel width of the pull-up transistor of the SRAM (see annotated Figs. 8 and 1: “channel widths”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AIDAN D BANKLER whose telephone number is (571)272-0883. The examiner can normally be reached Monday through Thursday 7:00-5:00.
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/AIDAN D BANKLER/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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