Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 (and dependent claims 22-28 dependent therefrom) is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 12, “and a same number of nanosheets as the first set of nanosheets,” in line 6 is unclear whether it is referring to the “second set of nanosheets”, the “first sub-set of nanosheets”, or the “second sub-set of nanosheets”. For the sake of compact prosecution, claim 21 is interpreted in the instant Office action as follows: “and a same number of nanosheets as the first set of nanosheets,” in line 6 is referring to the second set of nanosheets and is equivalent to “and the second set of nanosheets has a same number of nanosheets as the first set of nanosheets,”. This interpretation is based at least upon Fig. 1B of Applicant’s disclosure and is to be confirmed by applicant in next office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-22 and 24-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liaw (US 20200135740 A1).
Regarding independent claim 21 as noted in the 112(b) rejection, Liaw discloses a transistor circuitry comprising:
a first set of nanosheets (Fig. 2B: 255) used in an n-type transistor (the illustrated P Well is an ordinary and customary feature of an N-type transistor); and
a second set of nanosheets (Fig. 2C: 253) that has a first sub-set of nanosheets (See annotated figure for designated nanosheets) used in a p-type transistor (the illustrated N Well is an ordinary and customary feature of a P-type transistor);
a second sub-set of nanosheets (See annotated figure for designated nanosheets) underneath (Vertically “underneath”) the p-type transistor with end surfaces of the second sub-set of nanosheets (end portions of vertical-facing surfaces) in direct contact with a dielectric layer (233. Note: this layer is necessarily a dielectric layer to prevent shorting the gate 230 to the nanosheets, which is a scenario that would render the device inoperable); and the second set of nanosheets has a same number of nanosheets as the first set of nanosheets (3 sheets are illustrated for each transistor),
wherein a width of the second set of nanosheets (Fig. 2A: width W3) is wider than (the claimed configuration is encompassed in this cited range, [0027]: “a ratio of W1 over W3 (W1/W3) may be about 1.0, such as between about 0.9 and about 1.1”) a width of the first set of nanosheets (width W1).
Illustrated below are marked and annotated figures of Figs. 2A, 2B, and 2C of Liaw.
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483
761
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513
744
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Regarding claim 22, Liaw discloses the transistor circuitry of claim 21 (Fig. 2C), wherein the p-type transistor has source/drain regions (250) formed at two ends (horizontal ends) of the first sub-set of nanosheets of the second set of nanosheets.
Regarding claim 24, Liaw discloses the transistor circuitry of claim 21 (Fig. 2A), wherein each of the first set of nanosheets are respectively positioned in a same plane as each of the second set of nanosheets (horizontal “plane”), parallel to each other (“parallel” in the horizontal direction), and separated (horizontally “separated”) from each other by a dielectric layer (205).
Regarding claim 25, Liaw discloses the transistor circuitry of claim 21, wherein the p-type transistor is a pull-up transistor ([0023]: “the first pull-up node 206 and the second pull-up node 208 are formed in the N well 2001”) of a static-random-access memory (SRAM) ([0023]: “SRAM cell”) and the n-type transistor is a pull-down transistor ([0023]: “the first pull-down node 210, the second pull-down node 212…may be formed in the P wells 2002 and 2004”) of the SRAM.
Regarding claim 26, Liaw discloses the transistor circuitry of claim 25, wherein the width of the first set of nanosheets is a channel width of the pull-down transistor of the SRAM (this is the designation cited in the claim 21 rejection) and the width of the second set of nanosheets is a channel width of the pull-up transistor of the SRAM (this is the designation cited in the claim 21 rejection).
Regarding claim 27, Liaw discloses the transistor circuitry of claim 21 (Fig. 2A), wherein the p-type transistor is a pull-up transistor ([0023]: “the first pull-up node 206 and the second pull-up node 208 are formed in the N well 2001”) of a static-random-access memory (SRAM) ([0023]: “SRAM cell”) and the n-type transistor is a pass-gate transistor ([0023]: “the second pass-gate node 204 may be formed in the P wells 2002 and 2004”) of the SRAM.
Regarding claim 28, Liaw discloses the transistor circuitry of claim 27 (Fig. 2A), wherein the width of the first set of nanosheets is a channel width of the pass-gate transistor of the SRAM (this is the designation cited in the claim 21 rejection) and the width of the second set of nanosheets is a channel width of the pull-up transistor of the SRAM (this is the designation cited in the claim 21 rejection).
Allowable Subject Matter
Claims 1, 3-6, 15, 18-20, and 29-31 are allowed.
Claim 23 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claims 1, 3-6, and 29-31 is the inclusion of the limitation “wherein the one or more nanosheets is a first sub-set of the second set of nanosheets and the second set of nanosheets further comprises a second sub-set, the p-type transistor has source/drain regions formed at two ends of the first sub-set of the second set of nanosheets, and two ends of the second sub-set of the second set of nanosheets are in direct contact with a dielectric layer and isolated from the source/drain regions of the p- type transistor by the dielectric layer” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first sub-set”, “second sub-set”, “source/drain regions”, “dielectric layer”, and “isolated” in combination with all other limitations in claim 1. The inventive concept is directed to the inclusion of the second sub-set of nanosheets, without also including a corresponding electrical connection to the source/drain regions. This particular configuration was not found in the prior art, and could not reasonably be rendered as an obvious difference in shape, size, arrangement, or omission based on the teachings elsewhere in the prior art. MPEP 2144.04 (II), (III), (VI).
The primary reason for the allowable subject matter of claims 15 and 18-20 is the inclusion of the limitation “a second set of nanosheets horizontally corresponding to the first set of nanosheets and having a first sub-set and a second sub-set thereof, wherein the first sub-set of the second set of nanosheets is used in a p-type transistor, and a width of the second set of nanosheets is wider than a width of the first set of nanosheets, wherein the p-type transistor has source/drain regions formed at two ends of the first sub-set of the second set of nanosheets, and wherein two ends of the second sub-set of the second set of nanosheets are covered by and in direct contact with a dielectric layer and isolated from the source/drain regions of the p-type transistor by the dielectric layer” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first sub-set”, “second sub-set”, “source/drain regions”, “dielectric layer”, and “isolated” in combination with all other limitations in claim 15. The inventive concept is directed to the inclusion of the second sub-set of nanosheets, without also including a corresponding electrical connection to the source/drain regions. This particular configuration was not found in the prior art, and could not reasonably be rendered as an obvious difference in shape, size, arrangement, or omission based on the teachings elsewhere in the prior art. MPEP 2144.04 (II), (III), (VI).
The primary reason for the allowable subject matter of claim 23 is the inclusion of the limitation “wherein two ends of the second sub-set of nanosheets of the second set of nanosheets are covered by a dielectric layer and isolated from the source/drain regions of the p-type transistor” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first sub-set”, “second sub-set”, “source/drain regions”, “dielectric layer”, and “isolated” in combination with all other limitations in claims 23, 22, and 21. The inventive concept is directed to the inclusion of the second sub-set of nanosheets, without also including a corresponding electrical connection to the source/drain regions. This particular configuration was not found in the prior art, and could not reasonably be rendered as an obvious difference in shape, size, arrangement, or omission based on the teachings elsewhere in the prior art. MPEP 2144.04 (II), (III), (VI).
Response to Arguments
Applicant's arguments filed 8/5/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claim 15 that “the alleged second sub-set of the second set of nanosheets of, as illustrated in FIG. 8 of Paul, are not in direct contact with the dielectric layer 60. Paul does not disclose each and every distinct feature and element of claim 15. Zhang fails to cure the above deficiency of Paul. Claim 15 is patentable”. Remarks at pg. 9.
Examiner’s reply:
The examiner finds Applicant’s remarks persuasive and finds the claim allowable for reasons consistent with Applicant’s remarks.
Applicant argues:
Applicant argues with respect to amended claims 1 and 21 “recite similar features as recited above in amended claim 15. Applicant submits claims 1 and 21 are patentable as well”. Remarks at pg. 10.
Examiner’s reply:
With respect to amended claim 1 the examiner finds Applicant’s remarks persuasive and finds the claim allowable for reasons consistent with Applicant’s remarks.
With respect to amended claim 21 the examiner does not find Applicant’s remarks persuasive. Amended claim 21 does not include the “source/drain regions” or the “isolated” configuration required by claim 21. Accordingly, the examiner finds the claim anticipated by Liaw and the new grounds of rejection has been raised in the instant Office action as necessitated by the claim amendment.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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