DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 3, and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lane (US 9331062) in view of Preston (US 2022/0328399)
Regarding claim 1.
Lane teaches a semiconductor chip comprising: a device layer (Fig. 5: 202) having a first circuit region and a second circuit region (column 6 lines 40-45); a frontside distribution network (FSDN) (406) (column 6 lines 45-50) above the device layer (202) and delivering power to source/drain regions (405) of one or more transistors (404-1) of the first circuit region (column 6 lines 45-50); and a backside distribution network (BSDN) (410) below the device layer (202) and delivering power to source/drain regions (405) (column 6 lines 49-55) of one or more transistors (404-2) of the second circuit region, wherein the [backside] is electrically connected (408) to the FSDN (406) through the device layer (202); the FSDN (406) is electrically connected to the first circuit region through one or more frontside metal layers; and the BSDN (410) is electrically connected to the one or more transistors (404-2) of the second circuit region through the device layer (202) (column 6 lines 45-60) (fig 5).
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Lane does not teach the BSDN is electrically connected to the FSDN through the device layer
Preston teaches the BSDN (418) is electrically connected to the FSDN (414) through the device layer (408) (fig 4) (paragraph 36).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the connection from the backside part of the backside distribution network in order that the backside pads can be redistributed for improve accessibility.
Regarding claim 2.
Lane in view of Preston teaches the structure of claim 1.
Lane teaches the BSDN (410) is electrically connected to a bottom of at least one of the source/drain regions (405) of the one or more transistors (404-2) of the second circuit region through one or more through-device-layer- vias (TDLVs) (412) (fig 5) (column 6 lines 50-55).
Regarding claim 3.
Lane in view of Preston teaches the structure of claim 2.
Lane teaches the one or more TDLVs (412) are connected directly to the source/drain regions (405) of the one or more transistors (404-2) of the second circuit region (fig 5) (column 6 lines 50-60).
Regarding claim 4.
Lane in view of Preston teaches the structure of claim 1.
Preston teaches the BSDN (418) is directly connected to the FSDN (414) through one connection (fig 4) (paragraph 38), the one connection being a single power via, a power via (fsv) stacked on top of a through-device-layer-via (TDLV) (TSV), or a stack of wires and vias stacked on top of a TDLV (paragraph 38) (fig 4).
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lane (US 9331062) in view of Preston (US 2022/0328399) as applied to claim 1 above and further in view of White (US 2013/0011965).
Regarding claim 5.
Lane in view of Preston teaches elements of the structure in claim 1 above.
Preston teaches the FSDN (414) receives power from the BSDN (418) through an electrical connection (TSV) (fig 4) (paragraph 35-36)
Lane in view of Preston does not teach a power distribution network comprises a ring.
White teaches the FSDN comprises a ring (102) (fig 1) (paragraph 22) above the first circuit region (104) (fig 1a), the FSDN receives power from the BSDN (110) through an electrical connection made at the ring (fig 2) (paragraph 23).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a ring in order to convey power to provide power and ground to the integrated circuit (white paragraph 22)
Regarding claim 6.
Lane in view of Preston teaches elements of the structure in claim 1 above.
Lane in view of Preston does not teach a power distribution network comprises a grid.
White teaches the FSDN comprises a grid (102,106) (fig 1) above the first circuit region (104), the FSDN receives power from the BSDN (110) through two or more electrical connections (108,109) made to the grid (102,106) (fig 2) (paragraph 23).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a grid in order to convey power to provide power and ground to the integrated circuit (white paragraph 22)
Claim (s) 7, 8, 9, 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lane (US 93310062) in view of Preston (US 2022/0328399) as applied to claim 1 above and further in view of Li (US 2023/0260965)
Regarding claim 7.
Lane in view of Preston teaches elements of the structure of claim 1 above.
Preston teaches the FDSN (414) to provide a voltage to the first circuit region (424a) (fig 4)
Lane in view of Preston does not teach voltage regulators.
Li teaches the providing a voltage V2 (Vdd1) to the first circuit region (910a), the voltage V2 (Vdd1) being different from a voltage V1 (Vdd) of the BSDN (106) and being derived from the voltage V1 (Vdd) through a voltage regulator (920a) in the device layer (104) (fig 9) (paragraph 50-52).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide voltage regulators in the substrate in order to adjust the voltage and provide a regulated power supply to the active circuits (paragraph 19).
Regarding claim 8.
Lane in view of Preston teaches elements of the structure of claim 1 above.
Lane in view of Preston does not teach voltage regulators.
Li teaches a voltage V3 (Vdd2) derived from a voltage V1 (Vdd) of the BSDN (106) through a voltage regulator (920b) in the device layer (104) is provided back to the BSDN (106) and used to power the second circuit region (910b) through a through-device-layer-via (TDLV) (935) (fig 9) (paragraph 50-52).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide voltage regulators in the substrate in order to adjust the voltage and provide a regulated power supply to the active circuits (paragraph 19).
Regarding claim 9.
Lane in view of Preston in view of Li teaches the structure of claim 8.
Preston teaches the FSDN (414) to provide a voltage to the first circuit region (424a) (fig 4)
Li teaches providing the voltage V3 (Vdd2) back to the BSDN (106) (fig 9).
Regarding claim 10
Lane in view of Preston in view of Li teaches the structure of claim 8.
Li teaches the voltage regulator (920b) provides the voltage V3 (Vdd2) back to the BSDN (106) through the device layer (104) without going through the FSDN (fig 9) (paragraph 51).
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Regarding claim 11.
Lane in view of Preston teaches the structure of claim 1.
Preston teaches a FSDN (414) (fig 4)
Lane in view of Preston does not teach voltage regulators.
Li teaches providing a voltage V2 (Vdd2) to the first circuit region (102) and the BSDN (106) provides a voltage V1 (Vdd) directly to transistors (920c,910c) of the first circuit region through one or more through-device-layer-vias (TDLVs) (940,945), wherein the voltage V2 (Vdd2) being different from the voltage V1 (Vdd) and being derived from the voltage V1 (Vdd) through a voltage regulator (920b) in the device layer (106) (fig 9) (paragraph 50-52).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide voltage regulators in the substrate in order to adjust the voltage and provide a regulated power supply to the active circuits (paragraph 19).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lane (US 9331062) in view of Preston (US 2022/0328399) as applied to claim 4 above and further in view of Vanderbriel (US 2019/0165791)
Regarding claim 12.
Lane in view of Preston teaches elements of the claim 4 above.
Preston teaches the BSDN (418) receives a global clock signal and passes the global clock signal to the FSDN (414) through the one connection, the FSDN supplies the global clock signal to the first circuit region (paragraph 43).
Lane in view of Preston does not teach an external clock oscillator.
Vanderbriel teaches a global clock signal from an external clock oscillator (paragraph 107).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an external clock oscillator in order to be a source for a clock signal (Vanderbriel paragraph 107)
Claim(s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lane (US 9331062) in view of Preston (US 2022/0328399)
Regarding claim 13.
Lane teaches a semiconductor chip comprising: a device layer (202) having at least a first circuit region and a second circuit region (column 6 lines 40-45) (fig 5); a frontside distribution network (FSDN) (406) above the device layer (202); and a backside distribution network (BSDN) (410) below the device layer (202) (column 6 lines 49-55), wherein the [backside] is electrically connected to the FSDN (406) directly through one or more connections (408) (column 6 lines 45-50); the FSDN (406) is electrically connected to and powers the first circuit region through source/drain regions (405) of one or more transistors (404-1) of the first circuit region (column 6 lines 40-45); and the BSDN (410) is directly connected to source/drain regions (405) of one or more transistors (404-2) of the second circuit region (column 6 lines 50-55) electrically through one or more through-device-layer-vias (TDLVs) (412) (column 6 lines 50-55).
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Lane does not teach the BSDN is electrically connected to the FSDN through the device layer
Preston teaches the BSDN (418) is electrically connected to the FSDN (414) through the device layer (408) (fig 4) (paragraph 36).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the connection from the backside part of the backside distribution network in order that the backside pads can be redistributed for improve accessibility.
Regarding claim 14.
Lane in view of Preston teaches the structure of claim 13.
Preston teaches the one or more connections comprise a single power via, a power via (fsv) stacked on top of a TDLV (TSV_1), or a stack of wires and vias stacked on top of a TDLV (fig 4) (paragraph 38).
Claim(s) 15 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lane (US 9331062) in view of Preston (US 2022/0328399) as applied to claim 13 above and further in view of White (US 2013/0011965).
Regarding claim 15.
Lane in view of Preston teaches the structure of claim 13 above.
Preston teaches forming the FSDN and BSDN of metal layers (paragraph 9)
Lane in view of Preston does not teach a power distribution network comprises a ring.
White teaches the FSDN comprises a ring (102) (fig 1) (paragraph 22) above the first circuit region (104), the ring comprising two or more layers (fig 2) connected through vias (paragraph 22,23) (fig 2).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a ring in order to convey power to provide power and ground to the integrated circuit (white paragraph 22)
Regarding claim 16.
Lane in view of Preston teaches elements of the structure of claim 13 above.
Preston teaches the FSDN (414) receives power from the BSDN (418) through an electrical connection (TSV) (paragraph 35-36) (fig 4)
Lane in view of Preston does not teach a power distribution network comprises a grid.
White teaches the FSDN comprises a grid (102,106) above the first circuit region (104), the FSDN receives power from the BSDN (110) through the one or more connections (108,109), wherein the one or more connections includes two or more connections (108,109) made to the grid (102,106) fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a grid in order to convey power to provide power and ground to the integrated circuit (white paragraph 22)
Claim(s) 17, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lane (US 9331062) in view of Preston (US 2022/0328399) in view of Li (US 2023/0260965)
Regarding claim 17.
Lane teaches a semiconductor chip comprising: a backside distribution network (BSDN) (410); a device layer (202) over the BSDN (410) (column 6 lines 40-50), the device layer (202) having a first circuit region and a second circuit region; and a frontside distribution network (FSDN) (406) over the device layer (202) (fig 5) (column 6 lines 45-50), wherein the [backside] is electrically connected to the FSDN (406)to deliver power to source/drain regions (405) of transistors (404-1) of the first circuit region (fig 5); and wherein the BSDN (410) is directly connected to source/drain regions (405) of transistors (404-2) of the second circuit region through at least one through-device-layer-via (TDLV) (412) (fig 5) (column 6 lines 48-56).
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Lane does not teach the BSDN is electrically connected to the FSDN through the device layer
Preston teaches the BSDN (418) is electrically connected to the FSDN (414) through the device layer (408) (fig 4) (paragraph 36).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the connection from the backside part of the backside distribution network in order that the backside pads can be redistributed for improve accessibility.
Lane does not teach a voltage regulator.
Li teaches the BSDN (106) is electrically connected to the frontside through one or more voltage regulators (920a,b) in the device layer (104) to power the first circuit region (910a,b) (fig 9) (paragraph 50-51).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide voltage regulators in the substrate in order to adjust the voltage and provide a regulated power supply to the active circuits (paragraph 19).
Regarding claim 18.
Lane in view of Preston in view of Li teaches the structure of claim 17 above.
Li teaches the providing a voltage V2 (Vdd1) to the first circuit region (910a), the voltage V2 (Vdd1) being different from a voltage V1 (Vdd) of the BSDN (106) and being derived from the voltage V1 (Vdd) through the one or more voltage regulator (920a,b) in a device layer (104) (fig 9) (paragraph 50-52).
Regarding claim 19.
Lane in view of Preston in view of Li teaches the structure of claim 17 above.
Li teaches a voltage V3 (Vdd2) derived from a voltage V1 (Vdd) of the BSDN (106) through the one or more voltage regulators (920b) in the device layer (104) is provided back to the BSDN (106) and used to power the second circuit region (910b) through the at least one through-device-layer-via (TDLV) (935) (fig 9) (paragraph 50-52).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lane (US 9331062) in view of Preston (US 2022/0328399) in view of Li (US 2023/0260965) as applied to claim 17 above and further in view of Vanderbriel (US 2019/0165791)
Regarding claim 20.
Lane in view of Preston in view of Li teaches elements of the structure of claim 17 above.
Preston teaches the BSDN (418) receives a clock signal and passes the global clock signal to the FSDN (414) through the one or more connections, the FSDN supplies the global clock signal to the first circuit region (paragraph 43).
Lane in view Preston in view of Li does not teach an external clock oscillator.
Vanderbriel teaches a global clock signal from an external clock oscillator (paragraph 107).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an external clock oscillator in order to be a source for a clock signal (Vanderbriel paragraph 107)
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference combination applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The applicant argues that Preston does not teach all elements of the claim.
However, all elements of the claims are anticipated by the combination of Lane (US 9331062) in view of Preston (US 2022/0328399) as applied above.
The applicant amended the claims to correct grammatical errors, the objection for said errors has therefor been withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 December 26, 2025
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