DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: claims 1 through 12 and 14 through 20 rejected
Present action: claims 1 through 12 and 14 through 20 rejected
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1, 2, 3, 4, 6, 7, 10, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Noh (US 2019/0393315) in view of Hsu (US 2019/0172752)
Regarding claim 1.
Noh teaches:
A semiconductor device (fig 5:100a[0054]), comprising: a substrate (fig 5:101[0030]);
an active pattern (fig 5:105[0030]) disposed on the substrate (fig 5:101[0030]) and that extends in a first horizontal direction (fig 5:x[0029]);
a field insulating layer (fig 5:107[0054]) disposed on the substrate (fig 5:101[0030]) and that surrounds a sidewall of the active pattern (fig 5:105[0030]);
a gate electrode (fig 5:147,145[0038]) disposed on the field insulating layer (fig 5:107[0054]) and that extends in a second horizontal direction (fig 5:y[0029]) different from the first horizontal direction (fig 5:x[0029]);
a source/drain region (fig 5:110[0054]) disposed on at least one side of the gate electrode (fig 5:147,145[0038]);
a first interlayer insulating layer (fig 5,6:153[0054]) disposed on the field insulating layer (fig 5:107[0054]) and that surrounds a portion of a sidewall of the source/drain region (fig 5:110[0054]);
a second interlayer insulating layer (fig 6b:155[0054]) disposed on the first interlayer insulating layer (fig 5,6:153[0054]) and that surrounds a sidewall of the gate electrode (fig 5:147,145[0038]);
and a source/drain contact (fig 5,6b:180[0054]) that penetrates through the second interlayer insulating layer (fig 6b:155[0054])in a vertical direction (fig 5,6:Z[0029])and is electrically connected to the source/drain region (fig 5:110[0054]), wherein the source/drain contact (fig 5,6b:180[0054]) includes a portion of a lower sidewall of the source/drain contact (fig 5,6b:180[0054]) toward the second interlayer insulating layer (fig 6b:155[0054]) in the second horizontal direction (fig 5:y[0029]), and in a cross-section of the semiconductor device (fig 5:100a[0054]): the [portion] is disposed above an upper surface of the first interlayer insulating layer (fig 5:107[0054]) with respect to the substrate (fig 5:101[0030]) and has a sidewall having a slope with respect to the upper surface of the first interlayer insulating layer (fig 5:107[0054]) , and the portion of the lower sidewall of the source/drain contact (fig 5,6b:180[0054]) is disposed below a level of an upper surface of the source/drain region (fig 5:110[0054]) with respect to the substrate (fig 5:101[0030]).
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Noh does not teach the source drain contact comprises a skirt
Hsu teaches:
wherein the source/drain contact (fig 8:78[0028]) includes a skirt that protrudes from a portion of a lower sidewall of the source/drain contact (fig 8:78[0028]) toward the second interlayer insulating layer (fig 8:34[0014]) in the horizontal direction, and in a cross-section of the semiconductor device: the skirt is disposed above an upper surface of the first interlayer insulating layer (fig 8:16[0009]) with respect to the substrate (fig 8:12[0011]) and has a sidewall having a slope with respect to the upper surface of the first interlayer insulating layer (fig 8:16[0009]) that is less than a slope of the portion of the lower sidewall of the source/drain contact (fig 8:78[0028]) with respect to the upper surface of the first interlayer insulating layer (fig 8:16[0009]), and the portion of the lower sidewall of the source/drain contact (fig 8:78[0028]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the contact with a skirt in order that the area of contact and the size of the lower contact portion can provide lower resistance while the size of the contact is reduced (paragraph 3).
Regarding claim 2.
Noh in view of Hsu teaches the semiconductor device of claim 1, further
Hsu teaches:
a width of a lower surface of the source/drain contact (fig 8:78[0028])in the second horizontal direction is greater than a width of an upper surface of the source/drain contact (fig 8:78[0028])in the second horizontal direction.
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Regarding claim 3.
Noh in view of Hsu teaches the semiconductor device of claim 1, further
Noh teaches:
the source/drain contact (fig 5,6b:180[0046]) includes a first portion disposed on the source/drain region (fig 5:110[0054]) and a second portion disposed on the first portion (fig 6b annotated), the first portion includes first and second sidewalls that oppose each other in the second horizontal direction (fig 5,6b:y[0029]), and the second portion includes first and second sidewalls that oppose each other in the second horizontal direction (fig 5,6b:y[0029]), and the first sidewall of the first portion is continuous with the first sidewall of the second portion, and the second sidewall of the first portion is continuous with the second sidewall of the second portion.
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Hsu teaches:
the first sidewall of the first portion is continuous with the first sidewall of the second portion, and the second sidewall of the first portion is continuous with the second sidewall of the second portion (fig 8).
Regarding claim 4.
Noh in view of Hsu teaches the semiconductor device of claim 3, further
Hsu teaches:
the skirt includes: a first skirt that protrudes from the first sidewall of the first portion;
and a second skirt that protrudes from the second sidewall of the first portion.
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Regarding claim 6.
Noh in view of Hsu teaches the semiconductor device of claim 1, further
Hsu teaches:
a portion of the source/drain contact (fig 8:78[0028]) is disposed between the source/drain region (fig 8:30[0028]) and the second interlayer insulating layer (fig 8:34[0014]).
Regarding claim 7.
Noh in view of Hsu teaches the semiconductor device of claim 1, further
Noh teaches:
the [portion] (fig 6b annotated above]):
is in contact with an the upper surface of the first interlayer insulating layer (fig 6b:153[0054]).
Hsu teaches:
The skirt (fig 8 annotated above)
Regarding claim 10.
Noh in view of Hsu teaches the semiconductor device of claim 1, further
Noh teaches:
the source/drain contact (fig 5,6b:180[0054]) includes a first portion disposed on the source/drain region (fig 5,6b:110[0054]) and a second portion disposed on the first portion (fig 6b annotated above) and a portion of the first portion is in contact with the second interlayer insulating layer (fig 6b:155[0054]).
Hsu teaches:
a portion of an upper surface of the first portion is in contact with the second interlayer insulating layer (fig 8:34[0022]).
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Regarding claim 11.
Noh in view of Hsu teaches the semiconductor device of claim 1, further
Noh teaches:
a silicide layer (fig 6b:181[0050]) disposed between the source/drain region (fig 6b:110[0050]) and the source/drain contact (fig 6b:184[0050]);
and an etch stop layer (fig 6b:160[0045]) disposed between the first interlayer insulating layer (fig 6b:153[0045])and the silicide layer (fig 6b:181[0050]).
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Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Noh (US 2019/0393315) in view of Hsu (US 2019/0172752) as applied to claim 1 and further in view of Sherazi (US 2019/0229196)
Regarding claim 5.
Noh in view of Hsu the semiconductor device of claim 1, above
Noh in view of Hsu does not teach a capping pattern on the gate electrode and in contact with sidewalls of the source drain contacts.
Sherazi teaches:
a capping pattern (fig 4,13:15; [para 0147]) disposed on the gate electrode (dig 4,13:16; [para 0147]) and that extends in the second horizontal direction,
wherein the capping pattern (fig 4,13:15; [para 0147]) is in contact with a sidewall of the source/drain contact (fig 12,13:134a,b; [para 0167]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a capping layer in contact with the source drain electrode in order to provide a via landing portion and provide a margin for alignment (paragraph 14).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Noh (US 2019/0393315) in view of Hsu (US 2019/0172752) as applied to claim 1 and further in view of Wang (US 2022/0270971).
Regarding claim 8.
Noh in view of Hsu the semiconductor device of claim 1, above
Noh in view of Hsu does not teach an active region comprising nanosheets.
Wang teaches:
a plurality of nanosheets (fig 2,5:14; [para 0014]) stacked and spaced apart from each other in the vertical direction (fig 2,5:Z) on the active pattern (fig 2,5:20; [para 0011]) and surrounded by the gate electrode (fig 3,5:26; [para 0015]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide nanosheets in order to increase the surface area and thereby increase the coupling between the channel and the gate.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Noh (US 2019/0393315) in view of Hsu (US 2019/0172752) as applied to claim 1 and further in view of Huang (US 2021/0351299)
Regarding claim 9.
Noh in view of Hsu teaches the semiconductor device of claim 1, above.
Noh in view of Hsu does not teach that the first interlayer insulating layer and the second interlayer insulating layer include materials that differ from each other.
Huang teaches:
the first interlayer insulating layer (fig 11,12:90; [para 0051])and the second interlayer insulating layer (fig 11,12:92; [para 0051]) include materials that differ from each other (fig 11,12; [para 0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the first interlayer insulating layer and the second interlayer insulating layer include materials that differ from each other in order to optimize the dielectric separation between conductive features with the stability of the layers.
Claim(s) 12, 14, 15 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Noh (US 2019/0393315) in view of Hsu (US 2019/0172752)
Regarding claim 12.
Noh teaches:
A semiconductor device (fig 5:100a[0054]), comprising: a substrate (fig 5:101[0030]);
an active pattern (fig 5:105[0030]) disposed on the substrate (fig 5:101[0030]) and that extends in a first horizontal direction (fig 5:x[0029]);
a field insulating layer (fig 5:107[0054]) disposed on the substrate (fig 5:101[0030]) and that surrounds a sidewall of the active pattern (fig 5:105[0030]);
a gate electrode (fig 5:147,145[0038]) disposed on the field insulating layer (fig 5:107[0054]) and that extends in a second horizontal direction (fig 5:y[0029])different from the first horizontal direction (fig 5:x[0029]);
a source/drain region (fig 5:110[0054]) disposed on at least one side of the gate electrode (fig 5:147,145[0038]);
a first interlayer insulating layer (fig 5,6:153[0054])disposed on the field insulating layer (fig 5:107[0054]) and that surrounds a portion of a sidewall of the source/drain region (fig 5:110[0054]);
a second interlayer insulating layer (fig 6b:155[0054]) disposed on the first interlayer insulating layer (fig 5,6:153[0054]) and that surrounds a sidewall of the gate electrode (fig 5:147,145[0038]);
and a source/drain contact (fig 5,6b:180[0054]) that penetrates through the second interlayer insulating layer (fig 6b:155[0054]) in a vertical direction (fig 5:z[0029]) and is electrically connected to the source/drain region (fig 5:110[0054]), wherein the source/drain contact (fig 5,6b:180[0054]) includes a first portion disposed on the source/drain region (fig 5:110[0054]) and a second portion disposed on the first portion, the first portion includes first and second sidewalls that oppose each other in the second horizontal direction (fig 5:y[0029]), and the second portion includes first and second sidewalls that oppose each other in the second horizontal direction (fig 5:y[0029]), the first sidewall of the first portion is continuous with the first sidewall of the second portion, and the second sidewall of the first portion is continuous with the second sidewall of the second portion, , the source/drain contact (fig 5,6b:180[0054])further includes a a portion of a lower sidewall of the first portion, and in a cross-section of the semiconductor device (fig 5:100a[0054]): the [portion] is disposed above an upper surface of the first interlayer insulating layer (fig 5,6:153[0054]) with respect to the substrate (fig 5:101[0030]) and has a sidewall having a slope with respect to the upper surface of the first interlayer insulating layer (fig 5,6:153[0054]) (fig 5,6b:180[0054]) is disposed below a level of an upper surface of the source/drain region (fig 5:110[0054]), with respect to the substrate (fig 5:101[0030]).
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Noh does not teach the source/drain contact comprises a lower slope that is less than an upper slope
Hsu teaches:
a source/drain contact (fig 8:78[0028]) that penetrates through the second interlayer insulating layer (fig 8:34[0029]) in a vertical direction and is electrically connected to the source/drain region (fig 8:30[0013]), wherein the source/drain contact (fig 8:78[0028]) includes a first portion disposed on the source/drain region (fig 8:30[0013]) and a second portion disposed on the first portion (fig 8 annotated), the first portion includes first and second sidewalls that oppose each other in the second horizontal direction, and the second portion includes first and second sidewalls that oppose each other in the second horizontal direction, the first sidewall of the first portion is continuous with the first sidewall of the second portion, and the second sidewall of the first portion is continuous with the second sidewall of the second portion (fig 8), a width of a lower surface of the first portion in the second horizontal direction is greater than a width of a lower surface of the second portion in the second horizontal direction, the source/drain contact (fig 8:78[0028]) further includes a skirt that protrudes from a portion of a lower sidewall of the first portion toward the second interlayer insulating layer (fig 8:34[0015]) in the second horizontal direction, and in a cross-section of the semiconductor device: the skirt is disposed above an upper surface of the first interlayer insulating layer (fig 8:16[0013]) with respect to the substrate (fig 8:12[0012]) and has a sidewall having a slope with respect to the upper surface of the first interlayer insulating layer (fig 8:16[0013]) that is less than a slope of the portion of the lower sidewall of the first portion of the source/drain contact (fig 8:78[0028]) with respect to the upper surface of the first interlayer insulating layer (fig 8:16[0013]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the contact with a skirt in order that the area of contact and the size of the lower contact portion can provide lower resistance while the size of the contact is reduced (paragraph 3).
Regarding claim 14.
Noh in view of Hsu teaches the semiconductor device of claim 12, further
Hsu teaches:
the skirt includes: a first skirt that protrudes from the first sidewall of the first portion (fig 8);
and a second skirt that protrudes from the second sidewall of the first portion (fig 8).
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Regarding claim 15.
Noh in view of Hsu teaches the semiconductor device of claim 12, further
Noh teaches:
the [portion] (fig 6b annotated above]):
is in contact with an the upper surface of the first interlayer insulating layer (fig 6b:153[0054]).
Hsu teaches:
The skirt (fig 8 annotated above)
Regarding claim 18.
Noh in view of Hsu teaches the semiconductor device of claim 12, further
Noh teaches:
a portion of the first portion is in contact with the second interlayer insulating layer (fig 6b:155[0054]).
Hsu teaches:
a portion of an upper surface of the first portion is in contact with the second interlayer insulating layer (fig 8:34[0022]).
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Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Noh (US 2019/0393315) in view of Hsu (US 2019/0172752) as applied to claim 12 and further in view of Sherazi (US 2019/0229196)
Regarding claim 16.
Noh in view of Hsu the semiconductor device of claim 12, above
Noh in view of Hsu does not teach a capping pattern on the gate electrode and in contact with sidewalls of the source drain contacts.
Sherazi teaches:
a capping pattern (fig 4,13:15; [para 0147]) disposed on the gate electrode (dig 4,13:16; [para 0147]) and that extends in the second horizontal direction,
wherein the capping pattern (fig 4,13:15; [para 0147]) is in contact with a sidewall of the source/drain contact (fig 12,13:134a,b; [para 0167]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a capping layer in contact with the source drain electrode in order to provide a via landing portion and provide a margin for alignment (paragraph 14).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Noh (US 2019/0393315) in view of Hsu (US 2019/0172752) as applied to claim 12 and further in view of Huang (US 2021/0351299)
Regarding claim 17.
Noh in view of Hsu teaches the semiconductor device of claim 12, above.
Noh in view of Hsu does not teach that the first interlayer insulating layer and the second interlayer insulating layer include materials that differ from each other.
Huang teaches:
the first interlayer insulating layer (fig 11,12:90; [para 0051])and the second interlayer insulating layer (fig 11,12:92; [para 0051]) include materials that differ from each other (fig 11,12; [para 0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the first interlayer insulating layer and the second interlayer insulating layer include materials that differ from each other in order to optimize the dielectric separation between conductive features with the stability of the layers.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Noh (US 2019/0393315) in view of Hsu (US 2019/0172752) in view of Wang (US 2022/0270971).
Regarding claim 19.
Noh teaches:
A semiconductor device (fig 5:100a[0054]), comprising: a substrate (fig 5:101[0030]);
an active pattern (fig 5:105[0030]) disposed on the substrate (fig 5:101[0030]) and that extends in a first horizontal direction (fig 5:x[0029]);
a field insulating layer (fig 5:107[0054]) disposed on the substrate (fig 5:101[0030]) and that surrounds a sidewall of the active pattern (fig 5:105[0030]); a gate electrode (fig 5:147,145[0038]) disposed on the field insulating layer (fig 5:107[0054]) and that extends in a second horizontal direction (fig 5:y[0029]) different from the first horizontal direction (fig 5:x[0029]);
a source/drain region (fig 5:110[0054]) disposed on at least one side of the gate electrode (fig 5,6b:180[0054]);
a first interlayer insulating layer (fig 5,6:153[0054]) disposed on the field insulating layer (fig 5:107[0054]) and that surrounds a portion of a sidewall of the source/drain region (fig 5:110[0054]);
a second interlayer insulating layer (fig 6b:155[0054]) disposed on the first interlayer insulating layer (fig 5,6:153[0054]) and that surrounds a sidewall of the gate electrode (fig 5,6b:180[0054]);
and a source/drain contact (fig 5,6b:180[0054]) that penetrates through the second interlayer insulating layer (fig 6b:155[0054]) in a vertical direction (fig 5,6:Z[0029])and is electrically connected to the source/drain region (fig 5:110[0054]), wherein the source/drain contact (fig 5,6b:180[0054]) includes a first portion disposed on the source/drain region (fig 5:110[0054]), a second portion disposed on the first portion, the source/drain contact (fig 5,6b:180[0054]) includes a portion of a lower sidewall of the source/drain contact (fig 5,6b:180[0054]) toward the second interlayer insulating layer (fig 6b:155[0054]) in the second horizontal direction (fig 5:y[0029]), the first portion includes first and second sidewalls that oppose each other in the second horizontal direction (fig 5:y[0029]), and the second portion includes first and second sidewalls that oppose each other in the second horizontal direction (fig 5:y[0029]), the first sidewall of the first portion is continuous with the first sidewall of the second portion, and the second sidewall of the first portion is continuous with the second sidewall of the second portion (fig 5,6b), , and in a cross-section of the semiconductor device: the [portion] is disposed above an upper surface of the first interlayer insulating layer (fig 5,6:153[0054]) with respect to the substrate (fig 5:101[0030]) and has a sidewall having a slope with respect to the upper surface of the first interlayer insulating layer (fig 5,6:153[0054]) , and the portion of the lower sidewall of the source/drain contact (fig 5,6b:180[0054]) is disposed below a level of an upper surface of the source/drain region (fig 5:110[0054]).
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Noh does not teach that the source/drain contact comprises a l
Hsu teaches:
a source/drain contact (fig 8:78[0028]) that penetrates through the second interlayer insulating layer (fig 8:34[0014]) in a vertical direction and is electrically connected to the source/drain region (fig 8:30[0028]), wherein the source/drain contact (fig 8:78[0028]) includes a first portion disposed on the source/drain region (fig 8:30[0028]), a second portion disposed on the first portion, the source/drain contact (fig 8:78[0028]) includes a skirt that protrudes from a portion of a lower sidewall of the source/drain contact (fig 8:78[0028]) toward the second interlayer insulating layer (fig 8:34[0014]) in the second horizontal direction, the first portion includes first and second sidewalls that oppose each other in the second horizontal direction, and the second portion includes first and second sidewalls that oppose each other in the second horizontal direction, the first sidewall of the first portion is continuous with the first sidewall of the second portion, and the second sidewall of the first portion is continuous with the second sidewall of the second portion, a width of a lower surface of the first portion in the second horizontal direction is greater than a width of a lower surface of the second portion in the second horizontal direction, and in a cross-section of the semiconductor device: the skirt is disposed above an upper surface of the first interlayer insulating layer (fig 8:16[0009]) with respect to the substrate (fig 8:12[0011]) and has a sidewall having a slope with respect to the upper surface of the first interlayer insulating layer (fig 8:16[0009]) that is less than a slope of the portion of the lower sidewall of the source/drain contact (fig 8:78[0028]) with respect to the upper surface of the first interlayer insulating layer (fig 8:16[0009]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the contact with a skirt in order that the area of contact and the size of the lower contact portion can provide lower resistance while the size of the contact is reduced (paragraph 3).
Noh does not teach that the active pattern comprises a plurality of nanosheets
Wang teaches:
a plurality of nanosheets (fig 2,5:14; [para 0014]) stacked and spaced apart from each other in the vertical direction (fig 2,5:Z) on the active pattern (fig 2,5:20; [para 0011]) and surrounded by the gate electrode (fig 3,5:26; [para 0015]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide nanosheets in the active region in order to increase the surface area and thereby increase the coupling between the channel and the gate.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Noh (US 2019/0393315) in view of Hsu (US 2019/0172752) in view of Wang (US 2022/0270971) as applied to claim 19 and further in view of Huang (US 2021/0351299)
Regarding claim 20.
Noh in view of Hsu in view of Wang teaches the semiconductor device of claim 19, above.
Noh in view of Hsu in view of Wang does not teach that the first interlayer insulating layer and the second interlayer insulating layer include materials that differ from each other.
Huang teaches:
the first interlayer insulating layer (fig 11,12:90; [para 0051])and the second interlayer insulating layer (fig 11,12:92; [para 0051]) include materials that differ from each other (fig 11,12; [para 0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the first interlayer insulating layer and the second interlayer insulating layer include materials that differ from each other in order to optimize the dielectric separation between conductive features with the stability of the layers.
Response to Arguments
Previously applied claim objection is withdrawn due to amendment
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference combination applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The applicant argues that the amendment overcomes the previously applied rejection over Huang (US 2021/0351299).
However, over Noh (US 2019/0393315) in view of Hsu (US 2019/0172752) anticipates the amended claim (see above).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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