DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous office action: claims 1 through 12 and 14 through 20 rejected.
Present office action: claims 1 through 12 and 14 through 20 rejected
Claim Objections
Claims 1 through 11 are objected to because of the following informalities:
Claim 1 recites “region,,” in line 14. The double comma is improper, the examiner suggests using a single comma.
Claims 2 through 11 depend from and incorporate claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 4, 6, 9, and 11 is/are rejected under 35 U.S.C. 102a2 as being anticipated by Huang (US 2021/0351299)
Regarding claim 1.
Huang teaches:
a semiconductor device (fig 14a,14b:100; [para 0063]), comprising:
a substrate (fig 14a:50; [para 0054]);
an active pattern (fig 14b:64; [para 0019]) disposed on the substrate (fig 14a:50; [para 0019]) and that extends in a first horizontal direction (fig 14a,14c; [para 0062]);
a field insulating layer (fig 14b:62; [para 0023]) disposed on the substrate (fig 14b,c:50; [para 0019]) and that surrounds a sidewall of the active pattern (fig 14c:64; [para 0019]);
a gate electrode (fig 14c:99; [para 0045]) disposed on the field insulating layer (fig 14b:62; [para 0023]) and that extends in a second horizontal direction different from the first horizontal direction (fig 14a,14c);
a source/drain region (fig 14a,14b:80; [para 0040]) disposed on at least one side of the gate electrode (fig 14c:99; [para 0045]);
a first interlayer insulating layer (fig 14b,c:90; [para 0042]) disposed on the field insulating layer (fig 14b:62; [para 0023]) and that surrounds a portion of a sidewall of the source/drain region (fig 14a,14b:80; [para 0040]);
a second interlayer insulating layer (fig 14b,c:92; [para 0051])disposed on the first interlayer insulating layer (fig 14b,c:90; [para 0042]) and that surrounds a sidewall of the gate electrode (fig 14c:99; [para 0045]);
and a source/drain contact (fig 14b:104; [para 0055]) that penetrates through the second interlayer insulating layer (fig 14b,c:92; [para 0051]) in a vertical direction and is electrically connected to the source/drain region (fig 14a,14b:80; [para 0040]),
wherein the source/drain contact (fig 14a,14b:104; [para 0055]) includes a skirt that protrudes from a portion of a lower sidewall of the source/drain contact (fig 14b:104; [para 0055]) toward the second interlayer insulating layer (fig 14b,c:92; [para 0051]) in the second horizontal direction,
the skirt has a sidewall having a slope (fig 14a,14b) with respect to an upper surface of the first interlayer insulating layer (fig 14b,c:90; [para 0042]) that is less than a slope of the portion of the lower sidewall of the source/drain contact (fig 14b:104; [para 0055]) with respect to the upper surface of the first interlayer insulating layer (fig 14b,c:90; [para 0042]),
and the portion of the lower sidewall of the source/drain contact (fig 14b:104; [para 0055]) is disposed below a level of an upper surface of the source/drain region (fig 14a,14b:80; [para 0040]).
PNG
media_image1.png
646
1003
media_image1.png
Greyscale
Regarding claim 3.
Huang teaches the semiconductor device of claim 1, wherein:
the source/drain contact (fig 14a,14b:104; [para 0061]) includes a first portion disposed on the source/drain region (fig 14a,14b:80; [para 0039]) and a second portion disposed on the first portion,
the first portion includes first and second sidewalls that oppose each other in the second horizontal direction (fig 14a,b),
and the second portion includes first and second sidewalls that oppose each other in the second horizontal direction,
and the first sidewall of the first portion is continuous with the first sidewall of the second portion,
and the second sidewall of the first portion is continuous with the second sidewall of the second portion.
PNG
media_image2.png
517
862
media_image2.png
Greyscale
Regarding claim 4.
Huang teaches the semiconductor device of claim 3, wherein:
the skirt includes: a first skirt that protrudes from the first sidewall of the first portion;
and a second skirt that protrudes from the second sidewall of the first portion (annotated fig 14b).
Regarding claim 6.
Huang teaches the semiconductor device of claim 1, wherein:
a portion of the source/drain contact (fig 14b:104; [para 0061])is disposed between the source/drain region (fig 14b:80; [para 0039])and the second interlayer insulating layer (fig 14b:92; [para 0051]).
Regarding claim 9.
Huang teaches the semiconductor device of claim 1, wherein:
the first interlayer insulating layer (fig 11,12:90; [para 0051])and the second interlayer insulating layer (fig 11,12:92; [para 0051]) include materials that differ from each other (fig 11,12; [para 0051]).
Regarding claim 11.
Huang teaches the semiconductor device of claim 1:
a silicide layer (fig 14b:95; [para 0055]) disposed between the source/drain region (fig 14b:80; [para 0039]) and the source/drain contact (fig 14b:104; [para 0062]);
and an etch stop layer (fig 14b:89; [para 0041]) disposed between the first interlayer insulating layer (fig 14b:90; [para 0042]) and the silicide layer (fig 14b:95; [para 0055]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2021/0351299) as applied to claim 1 and further in view of Clark (US 2017/0345904)
Regarding claim 2.
Huang teaches the semiconductor device of claim 1 above.
Huang does not teach the contact lower surface wider than the upper surface.
Clark teaches:
a width of a lower surface of the source/drain contact (fig 2g:222; [para 0021]) in the second horizontal direction is greater than a width of an upper surface of the source/drain contact (fig 2g:222; [para 0021]) in the second horizontal direction.
PNG
media_image3.png
378
368
media_image3.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the lower surface to be wider than the upper surface in order to minimize the contact resistance between the contact and the source and to minimize the parasitic capacitance between the contact and neighboring structures (paragraph 1).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2021/0351299) as applied to claim 1 and further in view of Sherazi (US 2019/0229196)
Regarding claim 5.
Huang teaches the semiconductor device of claim 1 above,
Huang does not teach a capping pattern on the gate electrode and in contact with sidewalls of the source drain contacts.
Sherazi teaches:
a capping pattern (fig 4,13:15; [para 0147]) disposed on the gate electrode (dig 4,13:16; [para 0147]) and that extends in the second horizontal direction,
wherein the capping pattern (fig 4,13:15; [para 0147]) is in contact with a sidewall of the source/drain contact (fig 12,13:134a,b; [para 0167]).
PNG
media_image4.png
402
494
media_image4.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a capping layer in contact with the source drain electrode in order to provide a via landing portion and provide a margin for alignment (paragraph 14).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2021/0351299) as applied to claim 1 and further in view of Clark (US 2017/0345904)
Regarding claim 7.
Huang teaches the semiconductor device of claim 1 above.
Huang does not teach the skirt is in contact with an upper surface of the first interlayer insulating layer.
Clark teaches:
the skirt of the contact (fig 2g:222; [para 0021]) is in contact with an upper surface of the first interlayer insulating layer (fig 2g:200; [para 0010]).
PNG
media_image5.png
421
560
media_image5.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the lower surface to be wider than the upper surface in order to increase contact conductivity and minimize the contact resistance between the contact (paragraph 1).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2021/0351299) as applied to claim 1 and further in view of Wang (US 2022/0270971).
Regarding claim 8.
Huang teaches the semiconductor device of claim 1, above.
Huang does not teach a plurality of nanosheets.
Wang teaches:
a plurality of nanosheets (fig 2,5:14; [para 0014]) stacked and spaced apart from each other in the vertical direction (fig 2,5:Z) on the active pattern (fig 2,5:20; [para 0011]) and surrounded by the gate electrode (fig 3,5:26; [para 0015]).
It would have been obvious o one of ordinary skill in the art before the effective filing date of the claimed invention to provide nanosheets in order to increase the surface area and thereby increase the coupling between the channel and the gate.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2021/0351299) as applied to claim 1 and further in view of Clark (US 2017/0345904)
Regarding claim 10.
Huang teaches the semiconductor device of claim 1 above.
Huang teaches:
the source/drain contact (fig 14b:104; [para 0062]) includes a first portion disposed on the source/drain region (fig 14b:80; [para 0039]) and a second portion disposed on the first portion (fig 14b),
.
Huang does not teach that an upper surface of the contact is in contact with the second interlayer insulating layer.
Clark teaches:
a portion of an upper surface of the first portion of the contact (fig 2g:222; [para 0020]) is in contact with the second interlayer insulating layer (fig 2g:212,202; [para 0010]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the lower portion of the contact to be wider and to be in contact with the second insulating layer in order to minimize the contact resistance between the contact and the source (paragraph 1).
Claim(s) 12, 14, 15, 17, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2021/0351299) in view of Clark (US 2017/0345904)
Regarding claim 12.
Huang teaches:
a semiconductor device (fig 14a:100; [para 0064]), comprising:
a substrate (fig 14b:50; [para 0016]);
an active pattern (fig 14a,14b:64; [para 0014])disposed on the substrate (fig 14b:50; [para 0016]) and that extends in a first horizontal direction;
a field insulating layer (fig 14b:62; [para 0014]) disposed on the substrate (fig 14b:50; [para 0016]) and that surrounds a sidewall of the active pattern (fig 14b:64; [para 0014]);
a gate electrode (fig 14c:99; [para 0045]) disposed on the field insulating layer (fig 14b:62; [para 0014]) and that extends in a second horizontal direction different from the first horizontal direction;
a source/drain region (fig 14a,14b:80; [para 0039]) disposed on at least one side of the gate electrode (fig 14c:99; [para 0045]);
a first interlayer insulating layer (fig 14a,14b:90; [para 0042]) disposed on the field insulating layer (fig 14b:62; [para 0014]) and that surrounds a portion of a sidewall of the source/drain region (fig 14a,14b:80; [para 0039]);
a second interlayer insulating layer (fig 14a,14b:92; [para 0051]) disposed on the first interlayer insulating layer (fig 14b:62; [para 0014]) and that surrounds a sidewall of the gate electrode (fig 14c:99; [para 0045]);
and a source/drain contact (fig 14a,14b:104; [para 0062]) that penetrates through the second interlayer insulating layer (fig 14a,14b:92; [para 0051]) in a vertical direction and is electrically connected to the source/drain region (fig 14a,14b:80; [para 0039]),
wherein the source/drain contact (fig 14a,14b:104; [para 0062]) includes a first portion disposed on the source/drain region (fig 14a,14b:80; [para 0039]) and a second portion disposed on the first portion,
the first portion includes first and second sidewalls that oppose each other in the second horizontal direction,
and the second portion includes first and second sidewalls that oppose each other in the second horizontal direction,
the first sidewall of the first portion is continuous with the first sidewall of the second portion,
and the second sidewall of the first portion is continuous with the second sidewall of the second portion,
,
the source/drain contact (fig 14a,14b:104; [para 0062]) further includes a skirt that protrudes from a portion of a lower sidewall of the first portion toward the second interlayer insulating layer (fig 14b:92; [para 0051]) in the second horizontal direction,
and the skirt has a sidewall having a slope (fig 14a,14b) with respect to an upper surface of the first interlayer insulating layer (fig 14a,14b:90; [para 0042]) that is less than a slope of the portion of the lower sidewall of the first portion of the source/drain contact (fig 14a,14b:104; [para 0062]) with respect to the upper surface of the first interlayer insulating layer (fig 14a,14b:90; [para 0042]),
and the portion of the lower sidewall of the first portion of the source/drain contact (fig 14a,14b:104; [para 0062]) is disposed below a level of an upper surface of the source/drain region (fig 14a,14b:80; [para 0039]).
PNG
media_image6.png
528
884
media_image6.png
Greyscale
Huang does not teach the lower surface is wider than the upper surface.
Clark teaches:
a width of a lower surface of the first portion of the source/drain contact (fig 2g:222; [para 0021]) in the second horizontal direction is greater than a width of a lower surface of the second portion of the source/drain contact (fig 2g:222; [para 0021]) in the second horizontal direction
PNG
media_image3.png
378
368
media_image3.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the lower surface to be wider than the upper surface in order to minimize the contact resistance between the contact and the source and to minimize the parasitic capacitance between the contact and neighboring structures (paragraph 1).
Regarding claim 14.
Huang in view of Clark teaches the semiconductor device of claim 12:
Huang teaches:
the skirt includes: a first skirt that protrudes from the first sidewall of the first portion; and a second skirt that protrudes from the second sidewall of the first portion (annotated fig 14b above).
Regarding claim 15.
Huang in view of Clark teaches the semiconductor device of claim 12:
Clark teaches:
the skirt of the contact (fig 2g:222; [para 0021]) is in contact with an upper surface of the first interlayer insulating layer (fig 2g:200; [para 0010]).
PNG
media_image5.png
421
560
media_image5.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the lower surface to be wider than the upper surface in order to increase contact conductivity and minimize the contact resistance between the contact (paragraph 1).
Regarding claim 17.
Huang in view of Clark teaches the semiconductor device of claim 12 above:
Huang teaches:
the first interlayer insulating layer (fig 11,12:90; [para 0051])and the second interlayer insulating layer (fig 11,12:92; [para 0051]) include materials that differ from each other (fig 11,12; [para 0051]).
Regarding claim 18.
Huang in view of Clark teaches the semiconductor device of claim 12 above.
Clark teaches:
a portion of an upper surface of the first portion of the contact (fig 2g:222; [para 0020]) is in contact with the second interlayer insulating layer (fig 2g:212,202; [para 0010]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the lower portion of the contact to be wider and to be in contact with the second insulating layer in order to minimize the contact resistance between the contact and the source (paragraph 1).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2021/0351299) in view of Clark (US 2017/0345904) as applied to claim 12 and further in view of Sherazi (US 2019/0229196)
Regarding claim 16.
Huang in view of Clark teaches the semiconductor device of claim 12,
Huang in view of Clark does not teach a capping pattern on the gate electrode and in contact with sidewalls of the source drain contacts.
Sherazi teaches:
a capping pattern (fig 4,13:15; [para 0147]) disposed on the gate electrode (dig 4,13:16; [para 0147]) and that extends in the second horizontal direction,
wherein the capping pattern (fig 4,13:15; [para 0147]) is in contact with a sidewall of the source/drain contact (fig 12,13:134a,b; [para 0167]).
PNG
media_image4.png
402
494
media_image4.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a capping layer in contact with the source drain electrode in order to provide a via landing portion and provide a margin for alignment (paragraph 14).
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2021/0351299) in view of Wang (US 2022/0270971) in view of Clark (US 2017/0345904)
Regarding claim 19.
Huang teaches
A semiconductor device (fig 14b:100; [para 0015]), comprising:
a substrate (fig 14b:50; [para 0016]);
an active pattern (fig 14a,14b:64; [para 0020]) disposed on the substrate (fig 14b:50; [para 0016]) and that extends in a first horizontal direction;
a field insulating layer (fig 14b,14c:62; [para 0023]) disposed on the substrate (fig 14b:50; [para 0016]) and that surrounds a sidewall of the active pattern (fig 14a,14b:64; [para 0020]);
a gate electrode (fig 14c:99; [para 0049]) disposed on the field insulating layer (fig 14b,14c:62; [para 0023]) and that extends in a second horizontal direction different from the first horizontal direction;
;
a source/drain region (fig 14b:80; [para 0039]) disposed on at least one side of the gate electrode (fig 14a,14c:99; [para 0049]);
a first interlayer insulating layer (fig 14b:90; [para 0042]) disposed on the field insulating layer (fig 14b,14c:62; [para 0023]) and that surrounds a portion of a sidewall of the source/drain region (fig 14b:80; [para 0039]);
a second interlayer insulating layer (fig 14b:92; [para 0092]) disposed on the first interlayer insulating layer (fig 14b:90; [para 0042]) and that surrounds a sidewall of the gate electrode (fig 14b:104; [para 0062]);
and a source/drain contact (fig 14b:104; [para 0062]) that penetrates through the second interlayer insulating layer (fig 14b:92; [para 0092]) in a vertical direction and is electrically connected to the source/drain region (fig 14b:80; [para 0039]),
wherein the source/drain contact (fig 14b:104; [para 0062])includes a first portion disposed on the source/drain region (fig 14b:80; [para 0039]),
a second portion disposed on the first portion,
the source/drain contact (fig 14b:104; [para 0062]) includes a skirt that protrudes from a portion of a lower sidewall of the source/drain contact (fig 14b:104; [para 0062]) toward the second interlayer insulating layer (fig 14b:92; [para 0092]) in the second horizontal direction,
the first portion includes first and second sidewalls that oppose each other in the second horizontal direction (annotated fig 14b),
and the second portion includes first and second sidewalls that oppose each other in the second horizontal direction,
the first sidewall of the first portion is continuous with the first sidewall of the second portion,
and the second sidewall of the first portion is continuous with the second sidewall of the second portion,
,
the skirt has a sidewall having a slope (fig 14a,14b) with respect to an upper surface of the first interlayer insulating layer (fig 14b:90; [para 0042]) that is less than a slope of the portion of the lower sidewall of the source/drain contact (fig 14b:104; [para 0062]) with respect to the upper surface of the first interlayer insulating layer (fig 14b:90; [para 0042]),
and the portion of the lower sidewall of the source/drain contact (fig 14b:104; [para 0062]) is disposed below a level of an upper surface of the source/drain region (fig 14b:80; [para 0039]).
PNG
media_image6.png
528
884
media_image6.png
Greyscale
Huang does not teach a plurality of nanosheets.
Wang teaches:
a plurality of nanosheets (fig 2,5:14; [para 0014]) stacked and spaced apart from each other in the vertical direction (fig 2,5:Z) on the active pattern (fig 2,5:20; [para 0011]) and surrounded by the gate electrode (fig 3,5:26; [para 0015]).
It would have been obvious o one of ordinary skill in the art before the effective filing date of the claimed invention to provide nanosheets in order to increase the surface area and thereby increase the coupling between the channel and the gate.
Huang does not teach the contact lower surface wider than the upper surface.
Clark teaches:
a width of a lower surface of the source/drain contact (fig 2g:222; [para 0021]) in the second horizontal direction is greater than a width of an upper surface of the source/drain contact (fig 2g:222; [para 0021]) in the second horizontal direction.
PNG
media_image3.png
378
368
media_image3.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the lower surface to be wider than the upper surface in order to minimize the contact resistance between the contact and the source and to minimize the parasitic capacitance between the contact and neighboring structures (paragraph 1).
Regarding claim 20.
Huang in view of Wang in view of Clark teaches the semiconductor device of claim 19, wherein:
Huang teaches
the first interlayer insulating layer (fig 11,12:90; [para 0051])and the second interlayer insulating layer (fig 11,12:92; [para 0051]) include materials that differ from each other (fig 11,12; [para 0051]).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claims are now rejected over Huang (US 2021/0351299)
Previous rejection of claims 1 through 11 under USC 112 2nd paragraph have been overcome.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.J.G/ Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 April 1, 2026