DETAILED ACTION
This correspondence is in response to the communications received 04/29/2026. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The finality of the Office action mailed 02/26/2026 is hereby withdrawn in view of the new ground of rejection set forth below.
Applicant’s arguments, see pages 2-5, filed 04/29/2026, with respect to claim 1 have been fully considered and are persuasive. The rejection of 02/26/2026 has been withdrawn.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a method of forming a device structure, the method comprising:
providing a supporting structure ("supporting structure 100");
depositing a layer of conductive material ("layer 201 of conductive material") on top of the supporting structure (as seen in Fig. 2, 201 is on top of 100);
performing a first etching of the layer of conductive material to form a connection layer (" modified layer 202 is a remaining portion of the layer 201 after the first etching", [0017], 202 is a connection layer); and
performing a second etching of a remaining portion of the layer of conductive material, through a photo-resist pattern formed on top of the remaining portion of the layer of conductive material to form a micro-stud ("a second etching of the modified layer 202, particularly the exposed portion of modified layer 202, to form connection layer 203 and at least one micro-stud 204… Using a lithographic patterning process, a photo-resist pattern of the micro-stud 204 may be formed on a top surface of the modified layer 202", [0020]), the micro-stud being directly above the connection layer (as seen in Fig. 6, 204 is directly above 203) .
Regarding claim 2, The method of claim 1, wherein providing the supporting structure comprises:
providing a source/drain contact ("source/drain contacts 101") of an access transistor ("source/drain contacts 101 of one or more respective access transistors", [0015]);
covering the source/drain contact with a first dielectric layer ("a first dielectric layer 102", as seen in Fig. 2, 101 is covered with 102); and
creating a via opening in the first dielectric layer to form the supporting structure, with the via opening exposing the source/drain contact of the access transistor ("One or more via openings are created in the first dielectric layer 102 to expose at least one of the source/drain contacts 101", [0015]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (US 11,569,443 B2) in view of Dutta et al. (US 20230180618 A1).
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Regarding claim 1, Figs. 1-17 of Chuang disclose a method of forming a device structure, the method (see title) comprising:
providing a supporting structure (together “substrate 110”, col. 3, line 5, “etch stop layer 120 and a dielectric layer 130”, col. 3, line 27 are a supporting structure);
depositing a layer of conductive material on top of the supporting structure (“A bottom electrode layer 150 is then blanketly formed over the BEVAs 140 and over the dielectric layer 130”, col. 4, lines 18-20, “In some embodiments, the bottom electrode layer 150 is titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium (Ru), tungsten (W), aluminum (Al), copper (Cu), TiN, TaN, the like, and/or a combination thereof”, col. 4, lines 23-27, the metals listed are known in the art as conductive materials);
performing a first etching of the layer of conductive material to form a connection layer (“The top electrode layer 170, the resistance switching layer 160, and the bottom electrode layer 150 (referring to FIG. 2) are patterned into top electrodes 172, resistance switching elements 162, and bottom electrodes 152”, col. 5, lines 45-49, where “the patterning may include a directional physical dry etching process, such as IBE process”, col. 5, lines 52-54, as 152 is a pattered layer of a conductive material that connects 140 and 160, it is therefore a connection layer).
Chuang fails to disclose “performing a second etching of a remaining portion of the layer of conductive material, through a photo-resist pattern formed on top of the remaining portion of the layer of conductive material, to form a micro-stud, the micro-stud being directly above the connection layer.”
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However, in a similar field of endeavor, Figs. 1-4 of Dutta teach performing a second etching of a remaining portion of the layer of conductive material (Fig. 4 shows the result of a second etch of “metal layer 104”, [0030], previously etched into “separate metal lines 202 and 204”, [0033], where 204 is a remaining portion of the layer of conductive material), through a photo-resist pattern formed on top of the remaining portion of the layer of conductive material (“lithography mask 302”, [0034], where “Lithography mask 302 may include materials discussed for lithography mask 106”, [0034], Dutta discloses “lithography mask 106 may include a silicon containing anti-reflective coating (SiARC) layer formed on an organic planarization layer (OPL), and a photoresist layer”, [0032], and as seen in Fig. 3, 302 is on 204), to form a micro-stud (as seen in Fig. 4, “extended via 406”, [0035], is a micro-stud) the micro-stud being directly above the connection layer (as seen in Fig. 4, 406 is directly above “metal pad 404”, [0035], which was previously 204, 404 of Dutta is equivalent to 152 of Chuang).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “performing a second etching of a remaining portion of the layer of conductive material, through a photo-resist pattern formed on top of the remaining portion of the layer of conductive material, to form a micro-stud, the micro-stud being directly above the connection layer” as taught by Dutta in the system of Chuang for the purpose of reducing defects in the micro-stud, especially in the junction between the micro-stud and the connection layer (“As such, extended via 406 is the top via that extends from metal pad 404 with no interface or liner or barrier layer between extended via 406 and metal pad 404, because they both are formed of the same block of conductive material … Since formation of extended via 406 does not require metal fill the metal contact can be void free”, Dutta, [0035]).
Regarding claim 2, Figs. 1-17 of Chuang in combination with Figs. 1-4 of Dutta disclose the method of claim 1, Figs. 1-17 of Chuang further disclose wherein providing the supporting structure comprises:
a first dielectric layer (“interlayer dielectric (ILD) layer 114”, col. 3, lines 9-10, 114 is in 110, 110 is the bottommost layer of 110, 120, and 130 and is therefore a first dielectric layer).
Figs. 1-17 of Chuang in combination with Dutta fail to disclose “providing a source/drain contact of an access transistor;
covering the source/drain contact with a first dielectric layer; and
creating a via opening in the first dielectric layer to form the supporting structure, with the via opening exposing the source/drain contact of the access transistor.”
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However, in a similar field of endeavor, Fig. 19 of Chuang teaches providing a source/drain contact of an access transistor (as seen in Fig. 19, SDC is a source drain contact of “transistors 912”, col. 16, line 23, furthermore 912 controls signal access to “memory cells MC1”, col. 16, line 26, and is therefore an access transistor, MC1 of Fig. 19 is equivalent to MC1 of Figs. 1-17 of Chuang);
covering the source/drain contact with a first dielectric layer (as seen in Fig. 19, SDC is covered with ILD0 which is a specific interlayer dielectric layer, ILD0 of Fig. 19 is equivalent to 114 of Figs. 1-17 of Chuang); and
creating a via opening (“metallization vias or interconnects, labeled as V1…”, col. 16, lines 15-16, V1 is formed in an opening, hereinafter the V1 opening) in the first dielectric layer (as seen in Fig. 19, the V1 opening is in ILD0) to form the supporting structure (as ILD0 of Fig. 19 is equivalent to 114 of Figs. 1-17 of Chuang, creating the V1 opening is part of forming 110, 120, and 130), with the via opening exposing the source/drain contact of the access transistor (as seen in Fig. 19, V1 is in contact with SDC, therefore the V1 opening exposes SDC).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “providing a source/drain contact of an access transistor;
covering the source/drain contact with a first dielectric layer; and
creating a via opening in the first dielectric layer to form the supporting structure, with the via opening exposing the source/drain contact of the access transistor” as taught by Fig. 19 of Chuang in the system of Figs. 1-17 of Chuang in combination with Dutta for the purpose of controlling the memory cell with a transistor.
Regarding claim 8, Figs. 1-17 of Chuang in combination with Figs. 1-4 of Dutta disclose the method of claim 1, Figs. 1-17 of Chuang further disclose wherein the conductive material is selected from a group consisting of ruthenium (Ru), cobalt (Co), aluminum (Al), and tungsten (W) (“In some embodiments, the bottom electrode layer 150 is titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium (Ru), tungsten (W), aluminum (Al), copper (Cu), TiN, TaN, the like, and/or a combination thereof”, col. 4, lines 23-27).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (US 11,569,443 B2) in view of Dutta et al. (US 20230180618 A1) in view of Avanzino et al. (US 5,691,238 A) in view of Ito (US 9,583,535 B2).
Regarding claim 3, Figs. 1-17 of Chuang in combination with Figs. 1-4 of Dutta and Fig. 19 of Chuang disclose the method of claim 2.
Chuang in combination with Dutta fails to disclose “wherein depositing the layer of conductive material comprises depositing the conductive material into the via opening to form a via directly contacting the source/drain contact of the access transistor.”
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However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 5a-5i of Avanzino teach wherein depositing the layer of conductive material (“metal 77”, col. 6, lines 2-3, of Avanzino is equivalent to 150 of Chuang) comprises depositing the conductive material into the via opening to form a via (“the via and conductive line openings, 74 and 76 are filled with metal 77, herein Al/1% Cu, to form a conductive via 78 in physical contact with the underlying conductive line 71”, col. 6, lines 1-4, 78 of Avanzino is equivalent to 140 of Chuang).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein depositing the layer of conductive material comprises depositing the conductive material into the via opening to form a via” as taught by Avanzino in the system of Chuang in combination with Dutta for the purpose of depositing metal interconnect elements in a single step and reducing processing steps.
Chuang in combination with Dutta and Avanzino fails to disclose “a via directly contacting the source/drain contact of the access transistor”.
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However, in a similar field of endeavor, Fig. 2 of Ito teaches a via (as seen in Fig. 2, “bottom electrode BEC”, col. 2, line 63, vertically connects multiple elements and therefore functions as a via) directly contacting the source/drain contact of the access transistor (“One of the source/drain regions 104(D2) of the second select transistor is connected to the bottom of the second MTJ element M via a bottom electrode BEC”, col. 3, lines 5-7, and as seen in Fig. 2, BEC is directly contacting 104(D2)).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a via directly contacting the source/drain contact of the access transistor” as taught by Ito in the system of Chuang in combination with Dutta and Avanzino for the purpose of minimizing distance between electrical devices and limiting electrical interference between interconnects.
Regarding claim 4, Figs. 1-17 of Chuang in combination with Figs. 1-4 of Dutta, Fig. 19 of Chuang, Figs. 5a-5i of Avanzino, and Fig. 2 of Ito disclose the method of claim 3, Figs. 5a-5i of Avanzino further disclose wherein the via, the connection layer, and the micro-stud together form a unitary unit of the conductive material (77 comprises 78, “conductive line 80”, col. 6, line 14, and “second conductive via or stud 81”, col. 6, lines 14-15, where 80 and 81 of Ito are equivalent to 152 of Chuang and upper portion of 406 Dutta respectively, and “by combining the standard dual damascene process with the method of the present invention present invention, a triple damascene process and an unitary structure of a section of a conductive line with upper and lower vias results”, col. 6, lines 20-24).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (US 11,569,443 B2) in view of Dutta et al. (US 20230180618 A1) in view of Lee et al. (US 20190013353 A1, hereinafter ‘353) in view of Chen et al. (US 10,170,396 B2) in view of Lee et al. (US 11,276,693 B2, hereinafter ‘693).
Regarding claim 5, Figs. 1-17 of Chuang in combination with Figs. 1-4 of Dutta disclose the method of claim 1.
Chuang in combination with Dutta fails to disclose “further comprising:
covering the connection layer with a second dielectric layer;
covering the micro-stud with a dielectric liner;
covering the dielectric liner with a dielectric cap layer; and
planarizing the dielectric cap layer to expose a top surface of the micro-stud.”
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However, in a similar field of endeavor, Figs. 2A-2P of ‘353 teach covering the connection layer with a second dielectric layer (“Referring to FIG. 2M, an interlayer dielectric (ILD) layer 246 is deposited over the structure of FIG. 2”, [0059], 246 is a second dielectric layer, as “inter-layer dielectric layer 206”, [0047], is a first dielectric layer).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “covering the connection layer with a second dielectric layer” as taught by ‘353 in the system of Chuang in combination with Dutta for the purpose of physically supporting the connection layer and preventing unwanted electrical conductance between adjacent device structures.
Chuang in combination with Dutta and ‘353 fails to disclose covering the micro-stud with a dielectric liner;
covering the dielectric liner with a dielectric cap layer; and
planarizing the dielectric cap layer to expose a top surface of the micro-stud.
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However, in a similar field of endeavor, Figs. 3A-3G of Chen teach covering the micro-stud (“interconnect structure 12”, col. 5, lines 4-5, where 12 of Chen is equivalent to 204 of Dutta) with a dielectric liner (“liner 94 is formed from silicon dioxide or another suitable liner material”, col. 6, lines 3-4, silicon dioxide is known in the art as a dielectric material, as seen in Fig. 3E, 94 is covering 12);
covering the dielectric liner with a cap layer (“a barrier layer 96 may be formed over the liner 94. In an embodiment, the barrier layer 96 is formed from materials including Ta, W, Mo, Ti, TiW, TiN, TaN, WN, TiSiN, or TaSiN”, col. 6, lines 4-8, 96 is also a cap layer as it covers the upper surface of 94 “capping” it); and
planarizing the cap layer (“a chemical mechanical planarization process is performed to remove excess conductive material 88, the stop layer 90, the liner 94, and the barrier layer 96 from an upper surface of the first intermetal dielectric layer 56”, col. 6, lines 10-15) to expose a top surface of the micro-stud (As seen in Fig. 3F, the top surface of 12 is exposed after planarization, Fig. 3F includes “cap layer 98” which “may be selectively formed”, col. 6, lines 28-19, however 98 is only formed after planarization, thus the top surface of 12 is exposed after planarization).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “covering the micro-stud with a dielectric liner;
covering the dielectric liner with a dielectric cap layer; and
planarizing the dielectric cap layer to expose a top surface of the micro-stud” as taught by Chen in the system of Chuang in combination with Dutta and ‘353 for the purpose of providing lateral structural support for the micro-stud and adding a barrier layer to mitigate atomic diffusion.
Chuang in combination with Dutta, ‘353, and Chen fails to disclose “a dielectric cap layer”.
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 4A-11 of ‘693 teach a dielectric cap layer (“operation 214 deposits a barrier layer (e.g., 126a or 128a) on bottom and sidewalls of the contact holes to prevent metal materials of the S/D contacts 126 or 128 from diffusing into adjacent features. The barrier layer includes a dielectric material, such as TaN”, col. 10, lines 40-45, therefore 96 of Chen which could be comprised of TaN is a dielectric cap layer).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a dielectric cap layer” as taught by ‘693 in the system of Chuang in combination with Dutta, ‘353,and Chen for the purpose of providing an additional electrically insulating layer.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (US 11,569,443 B2) in view of Dutta et al. (US 20230180618 A1) in view of Lee et al. (US 20190013353 A1, hereinafter ‘353) in view of Chen et al. (US 10,170,396 B2) in view of Lee et al. (US 11,276,693 B2, hereinafter ‘693) in view of Ito (US 9,583,535 B2).
Regarding claim 6, Figs. 1-17 of Chuang in combination with Figs. 1-4 of Dutta, Figs. 2A-2P of ‘353, Figs. 3A-3G of Chen, and Figs. 4A-11 of ‘693 disclose the method of claim 5, Figs. 1-17 of Chuang further disclose further comprising forming a magnetic-tunnel junction (MTJ) device on top of the micro-stud (“resistance switching layer 160 is formed over the bottom electrode layer 150. In some embodiments, the resistance switching layer 160 may be a magnetic tunnel junction (MTJ) structure.”, col. 4, lines 30-33).
Chuang in combination with Dutta, ‘353, Chen, and ‘693 fails to disclose “forming a bit line in contact with the MTJ device.”
However, in a similar field of endeavor, Fig. 2 of Ito teaches forming a bit line in contact with the MTJ device (“The top of the second MTJ element M is connected to bit line BL2 via a top electrode TEC”, col. 3, lines 7-9, M and TEC of Ito are equivalent to 160 and “top electrodes 172” of Chuang).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “forming a bit line in contact with the MTJ device” as taught by Ito in the system of Chuang in combination with Dutta, ‘353, Chen, and ‘693 for the purpose of accessing the electrical state of the MTJ device.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (US 11,569,443 B2) in view of Dutta et al. (US 20230180618 A1) in view of Lee et al. (US 20190013353 A1, hereinafter ‘353) in view of Chen et al. (US 10,170,396 B2) in view of Lee et al. (US 11,276,693 B2, hereinafter ‘693) in view of Ko et al. (US 11,289,539 B2) in view of Sabuncuoglu et al. (US 12,017,909 B2).
Regarding claim 7, Figs. 1-17 of Chuang in combination with Figs. 1-4 of Dutta, Figs. 2A-2P of ‘353, Figs. 3A-3G of Chen, and Figs. 4A-11 of ‘693 disclose the method of claim 5.
Chuang in combination with Dutta, ‘353, Chen and ‘693 fails to disclose “wherein the dielectric liner is a non-conformal silicon-nitride layer”.
However, in a similar field of endeavor, Fig. 7 of Ko teaches wherein the dielectric liner is a silicon-nitride layer (“continuous dielectric liner 161L includes a dielectric material such as silicon oxide, silicon nitride, silicon carbide nitride (SiCN), or a dielectric metal oxide (such as aluminum oxide of hafnium oxide)”, col. 9, lines 54-58, Ko teaches that SiN and silicon oxide or (silicon dioxide) are functionally equal as liner layers, therefore the silicon dioxide 94 of Chen can be substituted for a SiN liner layer).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the dielectric liner is a silicon-nitride layer” as taught by Ko in the system of Chuang in combination with Dutta, ‘353, Chen, and ‘693 for the purpose of preventing unwanted oxidization by avoiding oxygen containing chemistries in the device forming process.
Chuang in combination with Dutta, ‘353, Chen, ‘693, and Ko fails to disclose “wherein the dielectric liner is a non-conformal silicon-nitride layer”.
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Fig. 9 of Sabuncuoglu teaches a non-conformal silicon-nitride layer (“Step 4 provides a liner deposition 93 and a non-conformal deposition 94 (e.g. a non-conformal silicon nitride deposition)”, col. 10, lines 33-35).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a non-conformal silicon-nitride layer” as taught by Sabuncuoglu in the system of Chuang in combination with Dutta, ‘353, Chen, ‘693, and Ko for the purpose of covering only the desired surface feature faces with the lining material.
Claims 9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (US 11,569,443 B2) in view of Avanzino et al. (US 5,691,238 A) in view of Jin (US 12,096,696 B2).
Regarding claim 9, Fig. 19. of Chuang discloses a method of forming a device structure (see title), the method comprising:
providing a source/drain contact of an access transistor (as seen in Fig. 19, SDC is a source drain contact of “transistors 912”, col. 16, line 14, furthermore 912 controls signal access to “memory cells MC1”, col. 16, line 26, and is therefore an access transistor);
forming a first dielectric layer covering the source/drain contact (as seen in Fig. 19, SDC is covered with “ILD layer ILD0”, col. 16, lines 34-35 which is an interlayer dielectric layer);
creating a via opening (“metallization vias or interconnects, labeled as V1…”, col. 16, lines 15-16, V1 is formed in an opening, hereinafter the V1 opening) in the first dielectric layer (as seen in Fig. 19, the V1 opening is in ILD0) to expose the source/drain contact (as seen in Fig. 19, V1 is in contact with SDC, therefore the V1 opening exposes SDC).
Fig. 19 of Chuang fails to disclose “depositing a layer of conductive material over the first dielectric layer, the conductive material filling the via opening to form a via;
performing a first etching of the layer of conductive material to form a connection layer extended from the via;
performing a second etching of the layer of conductive material to form a micro-stud extended from the connection layer.”
However, in a similar field of endeavor, Figs. 1-17 of Chuang teach depositing a layer of conductive material over the first dielectric layer (“A bottom electrode layer 150 is then blanketly formed over the BEVAs 140 and over the dielectric layer 130”, col. 4, lines 18-20, 130 of Figs. 1-17 is equivalent to ILD0 of Fig. 19);
performing a first etching of the layer of conductive material to form a connection layer (“The top electrode layer 170, the resistance switching layer 160, and the bottom electrode layer 150 (referring to FIG. 2) are patterned into top electrodes 172, resistance switching elements 162, and bottom electrodes 152”, col. 5, lines 45-49, where “the patterning may include a directional physical dry etching process, such as IBE process”, col. 5, lines 52-54, as 152 is a pattered layer of a conductive material that connects 140 and 160, it is therefore a connection layer).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “depositing a layer of conductive material over the first dielectric layer;
performing a first etching of the layer of conductive material to form a connection layer” as taught by Figs. 1-17 of Chuang in the system of Fig. 19 of Chuang for the purpose of creating a bottom electrode for a memory structure.
Chuang fails to disclose “the conductive material filling the via opening to form a via;
performing a first etching of the layer of conductive material to form a connection layer extended from the via;
performing a second etching of the layer of conductive material to form a micro-stud extended from the connection layer.”
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 5a-5i of Avanzino teach the conductive material filling the via opening to form a via (“the via and conductive line openings, 74 and 76 are filled with metal 77, herein Al/1% Cu, to form a conductive via 78 in physical contact with the underlying conductive line 71”, col. 6, lines 1-4, 77 and 78 of Avanzino are equivalent to 150 of Figs. 1-17 of Chuang and V1 of Fig. 19 of Chuang respectively);
performing a first etching of the layer of conductive material to form a connection layer extended from the via (as seen in Fig. 5g, 77 extends from 78).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the conductive material filling the via opening to form a via;
performing a first etching of the layer of conductive material to form a connection layer extended from the via” as taught by Avanzino in the system of Chuang for the purpose of depositing metal interconnect elements in a single step and reducing processing steps.
Chuang in combination with Avanzino fails to disclose “performing a second etching of the layer of conductive material to form a micro-stud extended from the connection layer”.
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However, in a similar field of endeavor, Fig. 5 of Jin teaches performing a second etching of the layer of conductive material (“sequentially etching the top electrode material layer, the magnetic tunnel junction material layer, and the bottom electrode material layer till a surface of the substrate is exposed, thereby forming a top electrode layer, a magnetic tunnel junction layer, and a bottom electrode layer”, col. 2, lines 40-45, “the method further includes, after forming the bottom electrode layer, etching the sidewalls of the bottom electrode layer to form the openings”, col. 3, lines 14-16, therefore the formation of “first type openings 610”, col. 9, line 34, in “bottom electrode layer 310” col. 9, lines 33-34, occur during a second etching process, 310 of Jin is equivalent to 150 of Chuang as both are bottom electrodes) to form a micro-stud extended from the connection layer (as seen in Fig. 5, the upper portion of 310 remaining after the first etch process surrounded horizontally by 610 is a micro-stud as it is a protruding conductive feature, hereinafter “MS”).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to “performing a second etching of the layer of conductive material to form a micro-stud extended from the connection layer” as taught by Jin in the system of Chuang in combination with Avanzino for the purpose of exposing a portion of the lower surface of the magnetic tunnel junction stack (Jin, col. 9, lines 31-38).
Regarding claim 15, Fig. 19 of Chuang in combination with Figs. 1-17 of Chuang, Figs. 5a-5i of Avanzino, and Fig. 5 of Jin disclose the method of claim 9, Figs. 1-17 of Chuang further disclose wherein the layer of conductive material is a layer of ruthenium (Ru), a layer of cobalt (Co), a layer of aluminum (Al), or a layer of tungsten (W) (“In some embodiments, the bottom electrode layer 150 is titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium (Ru), tungsten (W), aluminum (Al), copper (Cu), TiN, TaN, the like, and/or a combination thereof”, col. 4, lines 23-27).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (US 11,569,443 B2) in view of Avanzino et al. (US 5,691,238 A) in view of Jin (US 12,096,696 B2) in view of Ito (US 9,583,535 B2).
Regarding claim 10, Fig. 19 of Chuang in combination with Figs. 1-17 of Chuang, Figs. 5a-5i of Avanzino and Fig. 5 of Jin disclose the method of claim 9, Fig. 5 of Jin further discloses further comprising forming a magnetic-tunnel junction (MTJ) device (“magnetic tunnel junction layer 320”) having a first and a second contact area (“320 may be a three-layer structure, including a fixed layer 321 on the surface of the bottom electrode layer 310, a barrier layer 322 on the surface of the fixed layer 321, and a free layer 323 on the surface of the barrier layer 322”, col. 6, lines 32-36, 321 is a first contact area, 323 is a second contact area), the first contact area of the MTJ device being in contact with the micro-stud (as seen in Fig. 5, 321 is in contact with MS).
Chuang in combination with Avanzino and Jin fails to disclose “forming a bit line in contact with the second contact area of the MTJ device.”
However, in a similar field of endeavor, Fig. 2 of Ito teaches forming a bit line in contact with the second contact area of the MTJ device (“The top of the second MTJ element M is connected to bit line BL2 via a top electrode TEC”, col. 3, lines 7-9, the top of M is equivalent to the top of 323, therefore BL2 of Ito is in contact with 320 of Jin).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “forming a bit line in contact with the second contact area of the MTJ device” as taught by Ito in the system of Chuang in combination with Avanzino and Jin for the purpose of accessing the electrical state of the MTJ device.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (US 11,569,443 B2) in view of Avanzino et al. (US 5,691,238 A) in view of Jin (US 12,096,696 B2) in view of Ito (US 9,583,535 B2) in view of Chen et al. (US 10,170,396 B2).
Regarding claim 11, Fig. 19 of Chuang in combination with Figs. 1-17 of Chuang, Figs. 5a-5i of Avanzino, Fig. 5 of Jin, and Fig. 2 of Ito disclose the method of claim 10.
Chuang in combination with Avanzino, Jin, and Ito fails to disclose “further comprising forming a dielectric liner covering the micro-stud and the connection layer before forming the MTJ device.”
However, in a similar field of endeavor, Figs. 3A-3G of Chen teach further comprising forming a dielectric liner (“liner 94 is formed from silicon dioxide or another suitable liner material”, col. 6, lines 3-4, silicon dioxide is known in the art as a dielectric material) covering the micro-stud and the connection layer (as seen in Fig. 3E, 94 is covering “interconnect structure 12”, (12 of Chen is equivalent to 310 of Jin which includes both MS and a connection layer) and before forming the MTJ device (as seen in Fig. 3F, the top of 12 is still exposed with the exception of “cap layer 98” which “may be selectively formed”, col. 6, lines 28-19, demonstrating that the method steps of Chen occur prior to the formation of 320 of Jin).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “further comprising forming a dielectric liner covering the micro-stud and the connection layer before forming the MTJ device” as taught by Chen in the system of Chuang in combination with Avanzino, Jin, and Ito for the purpose of providing lateral structural support for the micro-stud and adding a barrier layer to mitigate atomic diffusion.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (US 11,569,443 B2) in view of Avanzino et al. (US 5,691,238 A) in view of Jin (US 12,096,696 B2) in view of Ito (US 9,583,535 B2) in view of Chen et al. (US 10,170,396 B2) in view of Ko et al. (US 11,289,539 B2) in view of Sabuncuoglu et al. (US 12,017,909 B2).
Regarding claim 12, Fig. 19 of Chuang in combination with Figs. 1-17 of Chuang, Figs. 5a-5i of Avanzino, Fig. 5 of Jin, Fig. 2 of Ito and Figs. 3A-3G of Chen disclose the method of claim 11.
Chuang in combination with Avanzino, Jin, Ito and Chen fails to disclose “wherein the dielectric liner is a silicon-nitride layer”.
However, in a similar field of endeavor, Fig. 7 of Ko teaches wherein the dielectric liner is a silicon-nitride layer (“continuous dielectric liner 161L includes a dielectric material such as silicon oxide, silicon nitride, silicon carbide nitride (SiCN), or a dielectric metal oxide (such as aluminum oxide of hafnium oxide)”, col. 9, lines 54-58, Ko teaches that SiN and silicon oxide or (silicon dioxide) are functionally equal as liner layers, therefore the silicon dioxide 94 of Chen can be substituted for a SiN liner layer).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the dielectric liner is a silicon-nitride layer” as taught by Ko in the system of Chuang in combination with Avanzino, Jin, Ito, and Chen for the purpose of preventing unwanted oxidization by avoiding oxygen containing chemistries in the device forming process.
Chuang in combination with Avanzino, Jin, Ito, Chen, and Ko fails to disclose “wherein the dielectric liner is a non-conformal silicon-nitride layer”.
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Fig. 9 of Sabuncuoglu teaches a non-conformal silicon-nitride layer (“Step 4 provides a liner deposition 93 and a non-conformal deposition 94 (e.g. a non-conformal silicon nitride deposition)”, col. 10, lines 33-35).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a non-conformal silicon-nitride layer” as taught by Sabuncuoglu in the system of Chuang in combination with Avanzino, Jin, Ito, Chen, and Ko for the purpose of covering only the desired surface feature faces with the lining material.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (US 11,569,443 B2) in view of Avanzino et al. (US 5,691,238 A) in view of Jin (US 12,096,696 B2) in view of Ito (US 9,583,535 B2) in view of Chen et al. (US 10,170,396 B2) ) in view of Lee et al. (US 11,276,693 B2, hereinafter ‘693).
Regarding claim 13, Fig. 19 of Chuang in combination with Figs. 1-17 of Chuang, Figs. 5a-5i of Avanzino, Fig. 5 of Jin, Fig. 2 of Ito and Figs. 3A-3G of Chen disclose the method of claim 11, Figs. 3A-3G of Chen further disclose further comprising covering the connection layer in a second dielectric layer (“intermetal dielectric (IMD) layer 56”, as seen in Fig. 3E, 56 covers 12) before forming the dielectric liner (as seen in Fig. 3E, 56 is below 94, therefore 56 is formed before forming 94) and subsequently covering the dielectric liner with a cap layer (“a barrier layer 96 may be formed over the liner 94. In an embodiment, the barrier layer 96 is formed from materials including Ta, W, Mo, Ti, TiW, TiN, TaN, WN, TiSiN, or TaSiN”, col. 6, lines 4-8, 96 is also a cap layer as it covers the upper surface of 94 “capping” it).
Chuang in combination with Avanzino, Jin, Ito, and Chen fails to disclose “a dielectric cap layer.”
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 4A-11 of ‘693 teach a dielectric cap layer (“operation 214 deposits a barrier layer (e.g., 126a or 128a) on bottom and sidewalls of the contact holes to prevent metal materials of the S/D contacts 126 or 128 from diffusing into adjacent features. The barrier layer includes a dielectric material, such as TaN”, col. 10, lines 40-45, therefore 96 of Chen which could be comprised of TaN is a dielectric cap layer).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a dielectric cap layer” as taught by ‘693 in the system of Chuang in combination with Avanzino, Jin, Ito, and Chen for the purpose of providing an additional electrically insulating layer.
Regarding claim 14, Fig. 19 of Chuang in combination with Figs. 1-17 of Chuang, Figs. 5a-5i of Avanzino, Fig. 5 of Jin, Fig. 2 of Ito, Figs. 3A-3G of Chen, and Figs. 4A-11 of ‘693 disclose the method of claim 13, Figs. 3A-3G of Chen further disclose further comprising planarizing the dielectric cap layer (“a chemical mechanical planarization process is performed to remove excess conductive material 88, the stop layer 90, the liner 94, and the barrier layer 96 from an upper surface of the first intermetal dielectric layer 56”, col. 6, lines 10-15) to expose the micro-stud (As seen in Fig. 3F, the top surface of 12 is exposed after planarization, Fig. 3F includes “cap layer 98” which “may be selectively formed”, col. 6, lines 28-19, however 98 is only formed after planarization, thus the top surface of 12 is exposed after planarization. Furthermore, Fig. 3F only shows 94 and 96 in “through via 14”, however after the incorporation of the second etching process of Jin, portions of 94 and 96 of Chen will remain in 610 of Jin after planarization) before forming the MTJ device, as the planarization step of Chen removes all layers down to the upper surface of 12, the planarization must occur before forming 320 of Jin).
Conclusion
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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