DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Prosecution Application
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on August 31st, 2026 has been entered.
Information Disclosure Statement
The IDS filed on 05/15/2026 and resubmitted in IDS filed on 08/31/2026 has been considered. Note that, the non patent literature documents cited in entry No. 13 and 14 does not include a date or at least a year and thus being lined through and in correct U.S. Pub. document in entry No. 3 has been corrected to 2005-0019980.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 4, 15, 20-24, and 31-33 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kurosawa et al. (U.S. Pub. 2005/0019980).
In re claim 4, Kurosawa discloses a method comprising providing a plurality of semiconductor dies 1 on a dicing tape 24 (see paragraph [0167] and fig. 5), each semiconductor die 1 of the plurality of semiconductor dies having a first bonding surface (rear surface) and a second surface (element formation surface) opposite the first bonding surface, the second surfaces of the plurality of semiconductor dies being attached to the dicing tape 24 (see paragraph [0167] and fig. 5); and securing the first bonding surfaces (rear surfaces that are covered with an adhesive layer 29) of the plurality of semiconductor dies 1 to a chuck 3 (holding table 3 provided with two systems of vacuum pipes 25A and 25B constitutes a vacuum chuck) while the plurality of semiconductor dies 1 are attached to the dicing tape 24 (see paragraph [0169] and fig. 5).
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In re claim 15, as applied to claim 4 above, Kurosawa discloses wherein the method comprising: removing the dicing tape 24 from the plurality of semiconductor dies 1; and selectively releasing one or more semiconductor dies 1 of the plurality of semiconductor dies while the remaining semiconductor dies 1 of the plurality of semiconductor dies are secured to the chuck 3 (see paragraphs [0175]-[0177] and figs. 7-8).
In re claim 20, as applied to claim 4 above, Kurosawa discloses wherein the chuck is a vacuum chuck (including vacuum pipe 25B and 25B), and wherein securing comprises: applying a vacuum force to the plurality of vacuum channels embedded in the vacuum chuck (see paragraph [0169] and fig. 5).
In re claim 21, as applied to claim 20 above, Kurosawa discloses wherein the method further comprising: removing the dicing tape 24 from the plurality of semiconductor dies 1; and selectively releasing one or more semiconductor dies 1 of the plurality of semiconductor dies while the remaining semiconductor dies 1 of the plurality of semiconductor dies are secured to the vacuum chuck 3 (see paragraphs [0175]-[0177] and figs. 7-8).
In re claim 22, as applied to claim 21 above, Kurosawa discloses wherein selectively releasing comprises reducing the vacuum force applied to the one or more semiconductor dies 1 (see paragraphs [0175]-[0177] and figs. 7-8).
In re claim 23, as applied to claim 20 above, Kurosawa discloses wherein a plurality of porous inserts are disposed on top of the plurality of vacuum channels (see paragraph [0186]).
In re claim 24, as applied to claim 23 above, Kurosawa discloses wherein the plurality of semiconductor dies 1 are disposed on top of the plurality of porous inserts (see paragraph [0186])
In re claim 31, as applied to claim 4 above, Kurosawa discloses the method further comprising picking, by a vacuum bonding tool 10, a semiconductor die 1 of the plurality of semiconductor dies from the chuck 3, wherein the vacuum bonding tool 10 is conductive and electrically grounded, and wherein picking comprises removing a charge from the semiconductor die 1 by contacting the semiconductor die 1 with the conductive vacuum bonding tool 10 (see paragraph [0161] and figs. 7-8).
In re claim 32, Kurosawa discloses a method comprising securing a wafer (semiconductor wafer comprises semiconductor chips 1) on a dicing tape 24 (see paragraph [0167] and fig. 5); dicing the wafer into a plurality of semiconductor dies 1 (semiconductor separated into semiconductor chips 1) (see paragraph [167] and fig. 5), each semiconductor die 1 of the plurality of semiconductor dies having a first bonding surface (rear surface) and a second surface (element formation surface) opposite the first bonding surface, the second surfaces of the plurality of semiconductor dies 1 being attached to the dicing tape 24 (see paragraph [0167] and fig. 5); securing the first bonding surfaces of the plurality of semiconductor dies 1 to a chuck 3 (holding table 3 provided with two systems of vacuum pipes 25A and 25B constitutes a vacuum chuck) while the plurality of semiconductor dies 1 are attached to the dicing tape 24 (see paragraph [0169] and fig. 5); removing the dicing tape 24 from the plurality of semiconductor dies 1 (via peeling claw 21) (see paragraph [0170] and fig. 5); and removing a semiconductor die 1 of the plurality of semiconductor dies from the chuck 3 (via suction collet 10) (see paragraph [0174] and figs. 7, 8, 9A-C, 10A-C, and 11A-C).
In re claim 33, as applied to claim 32 above, Kurosawa discloses wherein the method further comprising flipping the plurality dies 1 and the dicing tape 24 (see paragraph [159] and fig. 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kurosawa et al. (U.S. Pub. 2005/0019980) in view of Uzoh (U.S. Pub. 2018/0308819).
In re claim 1, Kurosawa discloses a method comprising providing a first wafer (see paragraph [0167] and fig. 5) and a second wafer (see paragraphs [0178], [0182] and figs. 9A-C, 11A-C); polishing the first wafer (see paragraph [0163]) (grinding the rear surface of the wafer to reach the cut grooves); dicing the first wafer on a dicing tape 24 to form a diced wafer comprising a plurality of dies (see paragraph [0167], and fig. 5) (semiconductor wafer separated into semiconductor chips 1); flipping the diced wafer (see paragraph [0068] and fig. 5) (separated semiconductor chips 1 on dicing tape 24 mounted on holding table 3); securing the diced wafer to a chuck 3 (see paragraph [0169] and fig. 5) (holding table 3 provided with two systems of vacuum pipes 25A and 25B constitutes a vacuum chuck); removing the dicing tape 24 from the diced wafer (via peeling claw 21) (see paragraph [0170] and fig. 5); and bonding at least some of the dies 1 of the plurality of dies to the second wafer (see paragraphs [0174], [0178], [0182]and figs. 7, 8, 9A-C, 10A-C, and 11A-C), (semiconductor chip 1 is picked up via suction collet 10 and placed on a printed circuit board 16).
Kurosawa is silent to the steps of polishing the second wafer and activating at least one of the first wafer, the diced wafer, and the second wafer.
However, Uzoh ‘819 discloses in a same field of endeavor, a method of forming a semiconductor device, including, inter-alia, providing a first wafer 302 and a second wafer 314 (see paragraphs [0034], [0039] and fig. 3); polishing the first wafer and the second wafer (CMP process) (see paragraph [0070]); dicing the first wafer 302 on a dicing tape 306 to form a diced wafer comprising a plurality of dies 310 (see paragraph [0034] and fig. 3), and activating (via nitrogen plasma) at least one of the first wafer, the diced wafer, and the second wafer (see paragraph [0038] and fig. 3); and bonding at least one of the dies 310 of the plurality of dies to the second wafer 314 (see paragraph [0050] and fig. 3).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Uzoh ‘819 into the method of Kurosawa in order to enable the steps of polishing the second wafer and activating at least one of the first wafer, the diced wafer, and the second wafer in Kurosawa to be performed in order to reduce the overall size of the semiconductor device, facilitate operation of the semiconductor device at high speeds (see paragraph [0005] of Uzoh) and furthermore to enhance bonding for stacking semiconductor device (see paragraph [0038] of Uzoh).
In re claim 2, as applied to claim 1 above, Kurosawa in combination with Uzoh ‘819 discloses wherein activating comprises activating the second wafer and one of the first wafer and the diced wafer (see paragraph [0038] and fig. 3 of Uzoh ‘819).
In re claim 3, as applied to claim 1 above, Kurosawa in combination with Uzoh ‘819 discloses wherein activating comprises exposing the at least one of the first wafer, the diced wafer, and the second wafer to a nitrogen plasma (see paragraph [0038] and fig. 3 of Uzoh ‘819).
Claim(s) 8, 11, 12, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kurosawa et al. (U.S. Pub. 2005/0019980), as applied to claim 4 above, and further in view of Uzoh et al. (U.S. Pub. 2017/0338214).
In re claim 8, as applied to claim 4 above, Kurosawa discloses wherein the method further comprising: removing the dicing tape 24 from the plurality of semiconductor dies 1; removing a semiconductor die 1 of the plurality of semiconductor dies from the chuck 3 and bonding the first bonding surface of the semiconductor die to a carrier 13 (see paragraph [0178] and figs. 9A-C) but is silent to directly bonding the first bonding surface of the semiconductor die to a carrier without an intervening adhesive.
However, Uzoh ‘214 discloses in a same field of endeavor, a method of manufacturing a semiconductor device, including, inter-alia, directly bonding the first bonding surface of the semiconductor die 3a to a carrier without an intervening adhesive (see paragraph [0022]).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Uzoh ‘214 into the method of Kurasawa in order to enable the bonding the first bonding surface of the semiconductor die to a carrier without an intervening adhesive in Kurasawa to be performed in order to improve in stacking of integrated device dies (see paragraph [0002] of Uzoh ‘214).
In re claim 11, as applied to claim 8 above, Kurasawa in combination with Uzoh ‘214 discloses wherein the directly bonding comprises directly bonding a non-conductive layer of the semiconductor die to a non-conductive layer of the carrier (see paragraph [0019] of Uzoh ‘214).
In re claim 12, as applied to claim 11 above, Kurasawa in combination with Uzoh ‘214 discloses wherein the directly bonding further comprises directly bonding conductive contacts of the semiconductor die to conductive contracts of the carrier (see paragraphs [0019], [0055] of Uzoh ‘214).
In re claim 14, as applied to claim 8 above, Kurasawa in combination with Uzoh ‘214 discloses wherein the second surface is a second bonding surface, further comprising: after the directly bonding, directly bonding a second semiconductor die to the second bonding surface of the semiconductor die (see paragraphs [0019], [0055] of Uzoh ‘214).
Claim(s) 17, 18, and 34-37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kurosawa et al. (U.S. Pub. 2005/0019980), as applied to claims 4 and 32 above, and further in view of Tischler (U.S. Pub. 2014/0319560).
In re claim 17, as applied to claim 4 above, Kurosawa discloses wherein the chuck is a vacuum chuck (see paragraph [0159] and fig. 5) but is silent to wherein the chuck is an electrostatic chuck, and wherein securing comprises: applying, by the electrostatic chuck, an electrostatic force to the plurality of semiconductor dies, wherein applying the electrostatic force comprises supplying power to a plurality of electrodes embedded in the electrostatic chuck.
However, Tischler disclose in a same field of endeavor, a method for manufacturing a semiconductor device, including, inter-alia, wherein the chuck is an electrostatic chuck, and wherein securing comprises: applying, by the electrostatic chuck, an electrostatic force to the plurality of semiconductor dies 210, wherein applying the electrostatic force comprises supplying power to a plurality of electrodes embedded in the electrostatic chuck (see paragraph [0122] and figs. 4A-E, note that, the electrostatic forces may be activated or deactivated electrically).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Tischer into the method of Kurasawa in order to enable the process of wherein the chuck is an electrostatic chuck, and wherein securing comprises: applying, by the electrostatic chuck, an electrostatic force to the plurality of semiconductor dies, wherein applying the electrostatic force comprises supplying power to a plurality of electrodes embedded in the electrostatic chuck in Kurasawa to be performed in order to hold the semiconductor dies in place.
In re claim 18, as applied to claim 17 above, Kurasawa in combination with Tischer discloses wherein the method further comprising removing the dicing tape from the plurality of semiconductor dies, and selectively releasing one or more semiconductor dies of the plurality of semiconductor dies are secured to the electrostatic chuck, wherein selectively releasing comprises changing the power supplied to one or more electrodes of the plurality of electrodes (see paragraph [0122] and figs. 4A-E of Tischer).
In re claim 34, as applied to claim 32 above, Kurasawa discloses wherein the chuck is a vacuum chuck (see paragraph [0159] and fig. 5) but is silent to wherein the chuck is an electrostatic chuck, the method further comprising: applying an electrostatic force to the plurality of semiconductor dies for securing the plurality of semiconductor dies to the electrostatic chuck.
However, Tischler disclose in a same field of endeavor, a method for manufacturing a semiconductor device, including, inter-alia, wherein the chuck is an electrostatic chuck, the method further comprising: applying an electrostatic force to the plurality of semiconductor dies 210 for securing the plurality of semiconductor dies to the electrostatic chuck (see paragraph [0122] and figs. 4A-E, note that, the electrostatic forces may be activated or deactivated electrically).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Tischer into the method of Kurasawa in order to enable the process of wherein the chuck is an electrostatic chuck, the method further comprising: applying an electrostatic force to the plurality of semiconductor dies for securing the plurality of semiconductor dies to the electrostatic chuck in Kurasawa to be performed in order to hold the semiconductor dies in place.
In re claim 35, as applied to claim 34 above, Kurasawa in combination with Tischer discloses wherein removing the semiconductor die comprises reducing the electrostatic force applied to the semiconductor die by the electrostatic chuck (see paragraph [0122] and figs. 4A-E of Tischer).
In re claim 36, as applied to claim 34 above, Kurasawa in combination with Tischer discloses wherein removing the semiconductor die comprises terminating power supplied to one or more electrodes of the electrostatic chuck associated with the semiconductor die (see paragraph [0122] and figs. 4A-E of Tischer).
In re claim 37, as applied to claim 34 above, Kurasawa in combination with Tischer discloses wherein removing the semiconductor die comprises inverting the electrostatic force applied to the electrostatic chuck to the semiconductor die and reducing the electrostatic force applied by the electrostatic chuck to the semiconductor die (see paragraph [0122[ and figs. 4A-E of Tischer).
Conclusion
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
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