DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2, 5-8, 15 and 17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There appears to be no adequate description in the specification for the claim limitations of “the pair of vertical portions of the interconnection insulating pattern are in physical contact with the adjacent ones of the peripheral circuit interconnection lines”, as recited in claim 2; “each of the pair of vertical portions of the interconnection insulating pattern has a first side surface, which is in physical contact with one of the adjacent ones of the peripheral circuit interconnection lines”, as recited in claims 5 and 15; “… a portion of the etch stop layer, which is in physical contact with the pair of vertical portions of the interconnection insulating pattern”, as recited in claim 6; “the third level is closer to the first level than to the second level”, as recited in claim 7; “the insulating pattern has a width of 80 nm to 100 nm in the first direction”, as recited in claim 8; “a width of the second trench ranges from 80 nm to 100 nm”, as recited in claim 17.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10, 13 and 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitation of "the pair of vertical portions of the interconnection insulating pattern has a first thickness …, and a second thickness …", as recited in claims 1 and 18, is unclear as to whether each, one or total of the pair of vertical portions of the interconnection insulating pattern has a first thickness and a second thickness applicant refers.
The claimed limitation of "one of the adjacent ones", as recited in claims 5 and 15, lines 6-7, is unclear as to whether said limitation is the same as or different from "one of the adjacent ones", as recited in claims 5 and 15, line 3.
The claimed limitation of “bit lines on the cell region of the substrate that extend in a second direction”, as recited in claim 9, is unclear as to which element “that” extend in a second direction applicant refers.
Claim 10 recites the limitation "the top surfaces of the peripheral circuit interconnection lines" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “top surfaces of adjacent ones of the peripheral circuit interconnection lines”, as recited in claim 1.
Claims 13 and 17 recite the limitation "the gate stack". There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “gate stacks”, as recited in claim 11.
Claim 15 recites the limitation "the peripheral circuit interconnection line" in line 3-4. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “peripheral circuit interconnection lines”, as recited in claim 11.
Claim 16 recites the limitation "the top surface" in line 6. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “top”, as recited in claim 16, line 3.
Claim 16 recites the limitation "the bottom surface" in line 6. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “bottom surfaces”, as recited in claim 16, line 3.
The claimed limitation of "a width … in the first direction", as recited in claim 18, is unclear as to whether said limitation is the same as or different from “a first thickness” and/or “a second thickness”, as recited in claim 1.
The claimed limitation of “bit line structures on the word lines that extend in a second direction …”, as recited in claim 18, is unclear as to which element “that” extend in a second direction applicant refers.
The claimed limitation of "a top surface of the landing pad", as recited in claim 18, line 17, is unclear as to whether said limitation is the same as or different from “a top surface of the landing pad”, as recited in claim 18, line 16.
Claim 18 recites the limitation "the peripheral interconnection lines" in lines 28. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “peripheral circuit interconnection lines”, as recited in claim 18, line 27.
The claimed limitation of "a top surface", as recited in claim 19, line 9, is unclear as to whether said limitation is the same as or different from “top”, as recited in claim 19, line 6.
The claimed limitation of "a bottom surface", as recited in claim 19, line 9, is unclear as to whether said limitation is the same as or different from “bottom surfaces”, as recited in claim 19, line 6.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-7, 9-11 and 18-20, as best understood, is/are rejected under 35 U.S.C. 102(a)1(1)/(a)(2) as being anticipated by Lim et al. (2022/0077152).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
As for claims 1, 3, 4, 9, and 18, Lim et al. show in Figs. 26-27 and related text a semiconductor device, comprising:
a substrate 400 including a cell region I and a peripheral region II, the cell region comprising first active regions 405 and a first device isolation layer 410 defining the first active regions, the peripheral region comprising second active regions 408 and a second device isolation layer 410 defining the second active regions ([0094]-[0096]);
word lines 460 that extend in a first direction to cross the first active regions;
bit line(s) structures 605 on (the cell region of the substrate) the word lines that extend in a second direction (, which is parallel to the to surface of the substrate and crosses) perpendicular to the first direction;
spacer structures 615/645/675 on respective side surfaces of each of the bit line structures;
a lower contact 705 (coupled to the substrate,) between (two adjacent ones of the bit lines) the spacer structures and connected to the first active regions;
a landing pad 755 on the lower contact that extends to respective regions on top surfaces of the bit line structures, the landing pad comprising a pad metal pattern and a barrier layer between the pad metal pattern and the lower contact ([0148], lines 1-5);
an insulating pattern 780/790 at least partially enclosing a side surface of the landing pad, (wherein a level of) a top surface of the insulating pattern (is equal to a level of a top surface of the interconnection insulating pattern) being coplanar with a top surface of the landing pad;
a capacitor 840 on a top surface of the landing pad;
gate stacks 1160 on the second active regions;
gate spacer structures 1272/1274 on respective side surfaces of each of the gate stacks;
a peripheral contact 1345 between the gate spacer structures and connected to the second active regions;
a first interlayer insulating layer 1310 on and at least partially covering respective side surfaces of each of the gate spacer structures while respective top surfaces of the gate spacer structures remain free of the first interlayer insulating layer;
a second interlayer insulating layer 1320 on the gate stacks and the first interlayer insulating layer;
peripheral circuit interconnection lines 1345, which are on the first interlayer insulating layer, and each of the peripheral interconnection lines is connected to the peripheral contact; and
an interconnection insulating pattern 780 between the peripheral circuit interconnection lines,
wherein the interconnection insulating pattern comprises a pair of vertical portions, which are spaced apart from each other in the first direction parallel to a top surface of the substrate, and a connecting portion, which connects the pair of vertical portions to each other,
wherein the pair of vertical portions of the interconnection insulating pattern has a first thickness at a same level as top surfaces of adjacent ones of the peripheral circuit interconnection lines, respectively, and a second thickness at a same level as bottom surfaces of the adjacent ones of the peripheral circuit interconnection lines, respectively,
wherein the connecting portion has a third thickness in a direction perpendicular to the top surface of the substrate, and
wherein the third thickness is (uniform in the first direction) equal to or greater than the first thickness and the second thickness.
As for claims 2 and 20, Lim et al. show the pair vertical portions of the interconnection insulating pattern are in physical contact with the adjacent ones of the peripheral circuit interconnection lines, and
wherein top surfaces of the pair vertical portions of the interconnection insulating pattern are coplanar with the top surfaces of the adjacent ones of the peripheral circuit interconnection lines (Fig. 27).
As for claim 4, Lim et al. show the third thickness is equal to or greater than the first thickness and the second thickness (Fig. 27).
As for claim 5, Lim et al. show each of the pair of vertical portions of the first interconnection insulating pattern has a first side surface, which is in physical contact with one of the adjacent ones of the peripheral circuit interconnection lines, and a second side surface, which is spaced apart from the first side surface in the first direction, and
wherein a slope of the second side surface is equal to a slope of a side surface of one of the adjacent ones of the peripheral circuit interconnection lines (Fig. 27).
As for claim 6, Lim et al. show an etch stop layer 790 on the interconnection insulating pattern, wherein a thickness (arbitrarily chosen) of a portion of the etch stop layer, which is in physical contact with the pair of vertical portions of the interconnection insulating pattern, is equal to a thickness (arbitrarily chosen) of another portion of the etch stop layer, which is in physical contact with the connecting portion of the interconnection insulating pattern (Fig. 27).
As for claim 10, Lim et al. show a top surface of the landing pad is located at the same level as the top surfaces of the peripheral circuit interconnection lines (Fig. 27).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 8, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. (2022/0077152).
As for claim 8, Lim et al. disclosed substantially the entire claimed invention, as applied to claim 1 above, including the interconnection insulating pattern has a width in the first direction
Lim et al. do not disclose the width (of the interconnection insulating pattern) of 80 nm to 100 nm.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include the width (of the interconnection insulating pattern) of 80 nm to 100 nm, in order to optimize the performance of the device. Furthermore, it has been held that where then general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Allowable Subject Matter
Claims 11-17 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record does not teach or suggest, singularly or in combination, at least the limitations of “the interlayer insulating layer comprising a first trench; and peripheral circuit interconnection lines on the interlayer insulating layer and a first interconnection insulating pattern between the peripheral circuit interconnection lines, wherein the first interconnection insulating pattern is in a portion of the first trench, wherein the first interconnection insulating pattern overlaps the device isolation layer in a direction perpendicular to a top surface of the substrate”, as recited in claim 11.
Claims 13-17 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed December 5, 2025 have been fully considered but they are not persuasive.
Applicant argues that “with respect to the interconnection insulating pattern has a width of about 80 nm to about 100 nm of Claim 8, paragraph 53 of the Specification provides support”.
The examiner respectfully disagrees because paragraph 53 of the Specification does not provide support for the limitation of “the interconnection insulating pattern has a width of about 80 nm to about 100 nm”, as recited in claim 8.
Applicant argues that “a width … in the first direction”, as recited in claim 8 is clear because “the width recited in Claim 8, this width refers to the entire interconnection insulating pattern. The thicknesses of Claim 1 refer to each of the pair of vertical portions of the interconnection insulating pattern”.
The examiner respectfully disagrees because Fig. 4 shows TS1 and/or TS2 referring to widths of parts of the interconnection insulating pattern. Therefore, an ordinary skill in the art will not know whether “width” as recited in claim 8 is referring to the entire interconnection insulating pattern, a first thickness and/or a second thickness.
Applicant argues that “independent Claims 1 and 18 and all claims depending therefrom are patentable over Lim” because “the present application claims priority to Korean Patent Application No. 10-2021-0103233 filed August 5, 2021. In accordance with MPEP §213, an Applicant may rely on foreign priority to overcome the effects of an intervening reference. To perfect Applicant's priority claim, Applicant submits herewith a certified English translation of the Korean priority patent application”; Lim (has a publication date of March 10, 2022) does not qualify as prior art under 35 U.S.C 102(a)(1).
The English translation of the foreign priority document which was submitted on December 5, 2025, is insufficient to perfect Applicant’s foreign priority claim, at least because of the following deficiencies with respect to the completeness and accuracy of said English translation:
A. Section after paragraph [0089] has been left untranslated; and
B. Claims 1 and 18 are different in the translation.
Therefore, the effective filing date of the instant application remains May 6, 2022.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEIYA LI whose telephone number is (571)270-1572. The examiner can normally be reached Monday-Friday 7AM-3PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LYNNE GURLEY can be reached at (571)272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MEIYA LI/Primary Examiner, Art Unit 2811
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