DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 35 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/03/2026 has been entered.
Remarks
The 03/12/2026 amendments of claims 1, 5, 8, 12, 15 and 17 have been noted and entered.
The 03/12/2026 cancellation of claim 20 has been noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks pages 7-13, filed 03/12/2026, with respect to the rejection of claims 1-7 and 15-20 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. The rejections of record have been withdrawn.
Applicant’s arguments, see Remarks pages 7-13, filed 03/12/2026, with respect to the rejection(s) of claim(s) 8-14 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Xie et al, US 20230345691 A1 (Xie).
New Grounds of Rejection
New grounds of rejection, prior art reference Xie et al, US 20230345691 A1 (Xie) appears below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 8 and 12-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al, US 20230345691 A1 (Xie).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Claims 8 and 12-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al, US 20230345691 A1 (Xie).
Regarding claim 8; Xie teaches a method of fabricating a semiconductor structure, comprising:
forming a first bottom transistor (Xie: Annotated Fig ( 5A) shared in this OA: 310) comprising a first bottom source/drain (S/D) (312);
forming a first top transistor ( 210) directly above the first bottom transistor (310), comprising a first top S/D (212) with only interlayer dielectric (120) between the first top S/D (212) and the first bottom S/D (312);
forming a first interlevel via (Annotated Fig (9A) shared in this OA which is a progression depiction of the construction of the device shown in Fig (5A): 851);
forming a middle dielectric isolation (MDI) (Annotated Fig (5A) shared in this OA: 512) oriented vertically to laterally separate i) the first bottom S/D (312) and the first top S/D (212) on a first side from ii) a gate (510) on a second side;
forming a middle-of-line (MOL) contact (Annotated Fig (9A) shared in this OA: 741) directly above and contacting the first top S/D (212),
wherein the MOL contact (741) connects the first top S/D (212) with the first interlevel via (851);
forming a backside contact (930) connected to a bottom of the first interlevel via (851) passing (in the Y-direction) the first top S/D (212) and the first bottom S/D (312); and
forming a backside power delivery network (BSPDN) connected to the backside contact (930; [0047]: “… More particularly, embodiments of present invention provide further forming a backside power distribution network (BSPDN) 930…”).
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Regarding claim 12; Xie teaches all the limitations of the method of claim 8.
Xie teaches further comprising forming the backside contact (Xie: Annotated Fig (9A) shared in this OA: 930) from a bottom side (Bottom Side) of the semiconductor structure (19) opposite a top side (Top Side).
Regarding claim 13; Xie teaches all the limitations of the method of claim 8
Xie teaches further comprising recessing the MOL contact (Xie: Annotated Fig (9A) shared in this OA: 741; 741 is recessed into the layer 110).
Regarding claim 14; Xie teaches all limitations of the method of claim 8.
Xie teaches further comprising forming a back-end-of-line (BEOL) interconnect network (Xie: Annotated Fig (9B) shared in this OA: 910) before forming the BSPDN (930; by examining the sequence of Figures (6A)-(6C) to Figures (9A)-(9C) it can be seen that the BEOL feature 910 is constructed before the BDSN feature 930).
Allowable Subject Matter
Claims 1-7 and 15-19 are allowable. The following is an examiner’s statement of reasons for allowance:
Prior art does not disclose, alone or in combination along with, the following highlighted limitations of the independent claims 1 and 15.
Regarding claim 1; Rubin in view of Hong in further view of Khaderbad teaches a semiconductor structure, comprising: a first top transistor comprising a first source/drain (S/D) region; a first bottom transistor comprising a second S/D region, wherein the second S/D region is stacked directly below the first S/D region with only an interlayer dielectric (ILD) between the first S/D region and the second S/D region; a backside power delivery network (BSPDN) below the first bottom transistor; a back-end-of-line (BEOL) metal level above the first top transistor.
However, Rubin alone or in combination with other available art does not teach a middle dielectric isolation (MDI) oriented vertically to laterally separate i) the first S/D region and the second S/D region on a first side from ii) a gate on a second side; and a first interlevel via directly contacting a top of the first S/D region, passing the first S/D region and the second S/D region, and electrically connecting the first S/D region to the BSPDN in a way that can be reasonably combined with the limitations listed above.
Claims 2-7 are allowable for their dependence on an allowable claim.
Regarding claim 15; Rubin in view of Khaderbad teaches A semiconductor structure, comprising: a first top transistor comprising a first source/drain (S/D) region; a first bottom transistor comprising a second S/D region stacked directly below the first S/D region with only an interlayer dielectric (ILD) between the first S/D region and the second S/D region; a backside power delivery network (BSPDN) below the bottom transistor; a back-end-of-line (BEOL) interconnect network above the top transistor.
However, Rubin alone or in combination with other available art does not teach a middle dielectric isolation (MDI) oriented vertically to laterally separate i) the first S/D region and the second S/D region on a first side from ii) a gate on a second side; and a first interlevel via directly contacting a backside contact on a bottom of the second S/D region and electrically connecting the second S/D region to the BEOL interconnect network in a manner that can be combined reasonably with the above listed limitations.
Claims 16-19 are allowable for their dependence on an allowable claim.
Claims 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 9; Xie teaches all the limitations of the method of claim 8, and further teaches comprising: forming a second top transistor adjacent to the first top transistor; and forming a second bottom transistor adjacent to the first bottom transistor and directly below the second top transistor.
However, Xie alone or in combination with other available art does not teach wherein the first interlevel via is located between the first top transistor and the second top transistor, and between the first bottom transistor and the second bottom transistor in manner that can be reasonably combined with the above listed limitations.
Claims 10-11 are objected to for their dependence on an objected to base claim.
Conclusion
Prior art made of record but not relied upon is considered pertinent to applicant’s disclosure:
Sarkar et al, US 20250167118 A1 (Sarkar); discloses stacked transistors on top of one another with connections between different components of the two sets of transistors.
Xie et al, US 20230369217 A1 (Xie); discloses stacked transistors with their connections to power lines and to each other.
Hong et al, US 20230275084 A1 (Hong); discloses vias connecting S/D areas of transistors to power supply lines.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
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/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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