DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claims 1, 6-10, and 15-18 filed on 12/15/2025 have been fully considered for examination based on their merits. The previously presented claims 2-5, and 11-14 have been considered. Claims 19-20 are withdrawn.
Response to Arguments
Applicant’s arguments, see Remarks, pages 6-8, filed on 12/15/2025, with respect to the rejection(s) of claim(s) 1-18 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of LIN.
Regarding Independent Claim(s) 1 and 10. The Applicant argues that BOUCHE discloses a liner or a protection layer (3216) that appears to form vertical segments with straight sidewalls, but BOUCHE does not explicitly disclose or suggest that the liner has a “tapper wall”. Additionally, WU does not teach or suggest that a liner extends around the contact. The Applicant further argues that none of the cited references disclose or suggest an amended limitation to claim(s) 1 and 10, now recites, “a contact liner located…angled sidewall…uniformed surface…tapered sidewall of the middle section.” The Examiner reviewed and confirmed that the specification and the drawings support the aforementioned claim limitations and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of LIN. LIN teaches a microelectronic device (Fig. 6, 200, IC device) comprising: a contact liner (Fig. 6, 284, contact barrier layer) located around the bottom section (Fig. 3, 276A, bottom that extends between a sidewall, 272A and sidewall, 274A, [0025]) of the contact (Fig. 6, 286, contact bulk layer), wherein the contact liner (Fig. 6, 284, contact barrier layer) has an angled sidewall (annotated Figure 6), such that the angled sidewall (annotated Figure 6) of the contact liner (Fig. 6, 284, contact barrier layer) forms a uniformed surface (annotated Figure 6) with a tapered sidewall of the middle section (Fig. 3, 302A/304A, sidewalls are tapered, [0033]).
Regarding Claim(s) 2-9, and 11-18. The Claim(s) 2-9, and 11-18 depend on the independent claim(s) 1 and 10 respectively, and are rejected on the similar new grounds mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guillaume Bouche et al, (hereinafter BOUCHE), US 20150311082 A1, in view of Xusheng Wu et al, (hereinafter WU), US 9299608 B2, and further in view of Shih-Che Lin et al, (hereinafter LIN), US 20210098376 A1.
Regarding Claim 1, BOUCHE teaches in Figure 32, a microelectronic device (3200, semiconductor devices) comprising:
a gate region (3214, gate structure) located adjacent to a source/drain region (110); and
a contact (3272 A-C) located above the source/drain region (3206, fins), wherein the contact (3272 A-C) has a bottom section (annotated Figure 32), a middle section (annotated Figure 32) and top section (annotated Figure 32), wherein the sidewalls (annotated Figure 32) of the bottom section (annotated Figure 32), the middle section (annotated Figure 32), and the top section (annotated Figure 32) of the contact (3272 A-C) are tapered ([0070], [0072]) towards a center Y-axis (annotated Figure 32) of the contact (3272 A-C).
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a gate contact (3274) located above the gate region (3214, gate structure), wherein the gate contact (3274) has tapered sidewalls towards a center Y-axis (annotated Figure 32, [0005]) of the gate contact (3274), wherein the gate contact (3274) is adjacent to the contact (3272 A-C), wherein the tapering of the sidewalls (annotated Figure 32, [0005]) of the gate contact (3274) is inverse ([0070]) to the tapering of the sidewalls (annotated Figure 32) of the contact (3272 A-C).
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BOUCHE does not explicitly disclose a microelectronic device comprising: wherein a tapered sidewall of the bottom section is noncontinuous with a tapered sidewall of the middle section.
WU teaches in Figures 7-9, a microelectronic device (Fig. 1, 100, non-planar semiconductor structure) comprising: wherein a tapered sidewall of the bottom section (annotated Figure 9) is noncontinuous (annotated Figure 9) with a tapered sidewall of the middle section (annotated Figure 9).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified BOUCHE to incorporate the teachings of WU, such that a microelectronic device comprising; wherein a tapered sidewall of the bottom section is noncontinuous with a tapered sidewall of the middle section, so that the non-planar semiconductor structure with T-shaped trenches to fill with a conductive material having improved contacts for not only decrease the resistance but also an open connection (WU, [Col. 1, Lines 10-20]).
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BOUCHE as modified by WU does not explicitly disclose a microelectronic device comprising: a contact liner located around the bottom section of the contact, wherein the contact liner has an angled sidewall, such that the angled sidewall of the contact liner forms a uniformed surface with a tapered sidewall of the middle section.
LIN teaches a microelectronic device (Fig. 6, 200, IC device) comprising: a contact liner (Fig. 6, 284, contact barrier layer) located around the bottom section (Fig. 3, 276A, bottom that extends between a sidewall, 272A and sidewall, 274A, [0025]) of the contact (Fig. 6, 286, contact bulk layer), wherein the contact liner (Fig. 6, 284, contact barrier layer) has an angled sidewall (annotated Figure 6), such that the angled sidewall (annotated Figure 6) of the contact liner (Fig. 6, 284, contact barrier layer) forms a uniformed surface (annotated Figure 6) with a tapered sidewall of the middle section (Fig. 3, 302A/304A, sidewalls are tapered, [0033]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified BOUCHE, in view of WU to incorporate the teachings of LIN, such that a microelectronic device comprising; a contact liner located around the bottom section of the contact, wherein the contact liner has an angled sidewall, such that the angled sidewall of the contact liner forms a uniformed surface with a tapered sidewall of the middle section, so that the contact barrier layer disposed on a contact bulk layer thus improve the methods of fabricating interconnects of ICs (LIN, [0002]).
Regarding Claim 2, BOUCHE as modified by WU and LIN teaches the microelectronic device of claim 1.
BOUCHE further teaches in Figure 32, the microelectronic device (3200, semiconductor devices), wherein the bottom section (annotated Figure 32) of the contact (3272 A-C) has a first width (annotated Figure 32), the middle section (annotated Figure 32) of the contact (3272 A-C) has a second width (annotated Figure 32), and top section (annotated Figure 32) of the contact (3272 A-C) has a third width (annotated Figure 32).
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Regarding Claim 3, BOUCHE as modified by WU and LIN teaches the microelectronic device of claim 2.
BOUCHE further teaches in Figure 32, the microelectronic device (3200, semiconductor devices), wherein the first width (annotated Figure 32) is less than the second width (annotated Figure 32).
Regarding Claim 4, BOUCHE as modified by WU and LIN teaches the microelectronic device of claim 3.
BOUCHE further teaches in Figure 32, the microelectronic device (3200, semiconductor devices), wherein the third width (annotated Figure 32) is less than the second width (annotated Figure 32).
Regarding Claim 5, BOUCHE as modified by WU and LIN teaches the microelectronic device of claim 4.
BOUCHE further teaches in Figure 32, the microelectronic device (3200, semiconductor devices), wherein the third width (annotated Figure 32) is less than, equal to, or greater than the first width (annotated Figure 32).
Regarding Claim 6, BOUCHE as modified by WU and LIN teaches the microelectronic device of claim 1.
LIN further teaches, the microelectronic device (Fig. 6, 200, IC device), wherein the contact liner (Fig. 6, 284, contact barrier layer) is located between the source/drain region (Fig. 6, 240A-240D, epitaxial source/drain feature, [0021]) and the contact (Fig. 6, 286, contact bulk layer).
Regarding Claim 7, BOUCHE as modified by WU and LIN teaches the microelectronic device of claim 6.
LIN further teaches, the microelectronic device (Fig. 6, 200, IC device), wherein the contact liner (Fig. 6, 284, contact barrier layer) includes a bottom section (annotated Figure 6) that is located directly on top of the source/region (Fig. 6, 240A-240D, epitaxial source/drain feature, [0021]).
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Regarding Claim 8, BOUCHE as modified by WU and LIN teaches the microelectronic device of claim 7.
LIN further teaches, the microelectronic device (Fig. 6, 200, IC device), wherein the bottom section of the contact (Fig. 6, 286, contact bulk layer) is located within a space between sections of the angled sidewall (annotated Figure 6) of the contact liner (Fig. 6, 284, contact barrier layer) and the bottom section (annotated Figure 6) of the contact liner (Fig. 6, 284, contact barrier layer).
Regarding Claim 9, BOUCHE as modified by WU and LIN teaches the microelectronic device of claim 7.
LIN further teaches the microelectronic device (Fig. 11A, 200, IC device), wherein the middle section (annotated Figure 11A) of the contact (Fig. 11A, 330′, bulk layer) is connected to the bottom section (annotated Figure 11A) of the contact (Fig. 11A, 286, contact bulk layer), and wherein the middle section (annotated Figure 11A) of the contact (Fig. 11A, 330′, bulk layer, [0046]) is in direct contact with a top surface (annotated Figure 11A) of the angled sidewall (annotated Figure 11A) of the contact liner (Fig. 11A, 284, contact barrier layer).
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Claims 10-18 are rejected under 35 U.S.C. 103 as being unpatentable over BOUCHE, in view of WU, further in view of Ruilong Xie et al, (hereinafter XIE), US 20200058757 A1, and further in view of LIN.
Regarding Claim 10, BOUCHE teaches in Figure 32, a microelectronic device (3200, semiconductor devices) comprising:
a gate region (3214, gate structure) located adjacent to a source/drain region (110);
a gate spacer (3249, nitride spacer) located between the gate region (3214, gate structure) and the source drain region (110);
a contact (3272 A-C) located above the source/drain region (3272 A-C), wherein the contact (3272 A-C) has a bottom section (annotated Figure 32), a middle section (annotated Figure 32) and top section (annotated Figure 32), wherein the sidewalls (annotated Figure 32) of the bottom section (annotated Figure 32), middle section (annotated Figure 32), and the top section (annotated Figure 32) of the contact (3272 A-C) are tapered (annotated Figure 32, [0070], [0072]) towards a center Y-axis (annotated Figure 32) of the contact (3272 A-C).
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BOUCHE does not explicitly disclose a microelectronic device comprising: wherein a tapered sidewall of the bottom section is noncontinuous with a tapered sidewall of the middle section.
WU teaches in Figures 7-9, a microelectronic device (Fig. 1, 100, non-planar semiconductor structure) comprising: wherein a tapered sidewall of the bottom section (annotated Figure 9) is noncontinuous (annotated Figure 9) with a tapered sidewall of the middle section (annotated Figure 9).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified BOUCHE to incorporate the teachings of WU, such that a microelectronic device comprising; wherein a tapered sidewall of the bottom section is noncontinuous with a tapered sidewall of the middle section, so that the non-planar semiconductor structure with T-shaped trenches to fill with a conductive material having improved contacts for not only decrease the resistance but also an open connection (WU, [Col. 1, Lines 10-20]).
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BOUCHE as modified by WU does not teach a microelectronic device comprising; a first interlayer dielectric located between the gate spacer and the contact; and a second interlayer dielectric located above the gate spacer and the gate region, wherein the middle section of the contact is directly contact with the first interlayer dielectric and the second interlayer dielectric.
XIE teaches in Figures 5A-5B, a microelectronic device (Contact Structures) comprising;
a first interlayer dielectric (205, annotated Figure 5A) located between the gate spacer (125, sidewall spacers) and the contact (175, D contact); and
a second interlayer dielectric (200, liner, low-k material) located above the gate spacer (125, sidewall spacers) and the gate region (115, gate structures), wherein the middle section (annotated Figure 5A) of the contact (175, D contact) is directly contact with the first interlayer dielectric (205, annotated Figure 5A) and the second interlayer dielectric (200, liner, low-k material).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified BOUCHE as modified by WU to incorporate the teachings of XIE, such that a microelectronic device comprising; a first interlayer dielectric located between the gate spacer and the contact; and a second interlayer dielectric located above the gate spacer and the gate region, wherein the middle section of the contact is directly contact with the first interlayer dielectric and the second interlayer dielectric. The arrangements of first and second interlayer dielectric by means of low-k dielectric liners and ILD layer acts an insulating barrier layers to minimize or nullify the electrical signals and thus protects the gate structures from the neighboring source/drain contacts ([XIE, [0030], [0036]).
BOUCHE as modified by WU and XIE does not explicitly disclose a microelectronic device comprising: a contact liner located around the bottom section of the contact, wherein the contact liner has an angled sidewall, such that the angled sidewall of the contact liner forms a uniformed surface with a tapered sidewall of the middle section.
LIN teaches a microelectronic device (Fig. 6, 200, IC device) comprising: a contact liner (Fig. 6, 284, contact barrier layer) located around the bottom section (Fig. 3, 276A, bottom that extends between a sidewall, 272A and sidewall, 274A, [0025]) of the contact (Fig. 6, 286, contact bulk layer), wherein the contact liner (Fig. 6, 284, contact barrier layer) has an angled sidewall (annotated Figure 6), such that the angled sidewall (annotated Figure 6) of the contact liner (Fig. 6, 284, contact barrier layer) forms a uniformed surface (annotated Figure 6) with a tapered sidewall of the middle section (Fig. 3, 302A/304A, sidewalls are tapered, [0033]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified BOUCHE, in view of WU and XIE to incorporate the teachings of LIN, such that a microelectronic device comprising; a contact liner located around the bottom section of the contact, wherein the contact liner has an angled sidewall, such that the angled sidewall of the contact liner forms a uniformed surface with a tapered sidewall of the middle section, so that the contact barrier layer disposed on a contact bulk layer thus improve the methods of fabricating interconnects of ICs (LIN, [0002]).
Regarding Claim 11, BOUCHE as modified by WU, XIE, and LIN teaches the microelectronic device of claim 10.
BOUCHE further teaches in Figure 32, the microelectronic device (3200, semiconductor devices), wherein the bottom section of the contact (3272 A-C) has a first width (annotated Figure 32), the middle section (3272 A-C) of the contact has a second width (annotated Figure 32) , and top section (3272 A-C) of the contact has a third width (annotated Figure 32) .
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Regarding Claim 12, BOUCHE as modified by WU, XIE, and LIN teaches the microelectronic device of claim 11.
BOUCHE further teaches in Figure 32, the microelectronic device (3200, semiconductor devices), wherein the first width (annotated Figure 32) is less than the second width (annotated Figure 32).
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Regarding Claim 13, BOUCHE as modified by WU, XIE, and LIN teaches the microelectronic device of claim 12.
BOUCHE further teaches in Figure 32, the microelectronic device (3200, semiconductor devices), wherein the third width (annotated Figure 32) is less than the second width (annotated Figure 32).
Regarding Claim 14, BOUCHE as modified by WU, XIE, and LIN teaches the microelectronic device of claim 13.
BOUCHE further teaches in Figure 32, the microelectronic device (3200, semiconductor devices), wherein the third width (annotated Figure 32) is less than, equal to, or greater than the first width (annotated Figure 32).
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Regarding Claim 15, BOUCHE as modified by WU, XIE, and LIN teaches the microelectronic device of claim 10.
LIN further teaches, the microelectronic device (Fig. 6, 200, IC device) of claim 10,
wherein the contact liner (Fig. 6, 284, contact barrier layer) is adjacent to the gate spacer (Fig. 6, 236), and wherein the contact liner (Fig. 6, 284, contact barrier layer) is adjacent to the interlayer dielectric (Fig. 6, 252).
Regarding Claim 16, BOUCHE as modified by WU, XIE, and LIN teaches the microelectronic device of claim 15.
LIN further teaches, the microelectronic device (Fig. 6, 200, IC device), wherein the contact liner (Fig. 6, 284, contact barrier layer) includes a bottom section (annotated Figure 6) that is located directly on top of the source/region (Fig. 6, 240A-240D, epitaxial source/drain feature, [0021]).
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Regarding Claim 17, BOUCHE as modified by WU, XIE, and LIN teaches the microelectronic device of claim 16.
LIN further teaches, the microelectronic device (Fig. 6, 200, IC device), wherein the bottom section of the contact (Fig. 6, 286, contact bulk layer) is located within a space between the angled sidewall (annotated Figure 6) of the contact liner (Fig. 6, 284, contact barrier layer) and the bottom section (annotated Figure 6) of the contact liner (Fig. 6, 284, contact barrier layer).
Regarding Claim 18, BOUCHE as modified by WU and LIN teaches the microelectronic device of claim 17.
LIN further teaches the microelectronic device (Fig. 11A, 200, IC device), wherein the middle section (annotated Figure 11A) of the contact (Fig. 11A, 330′, bulk layer) is connected to the bottom section (annotated Figure 11A) of the contact (Fig. 11A, 286, contact bulk layer), and wherein the middle section (annotated Figure 11A) of the contact (Fig. 11A, 330′, bulk layer, [0046]) is in direct contact with a top surface (annotated Figure 11A) of the angled sidewall (annotated Figure 11A) of the contact liner (Fig. 11A, 284, contact barrier layer).
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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/SESHA SAIRAMAN SRINIVASAN/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812