Prosecution Insights
Last updated: October 02, 2026

Examiner: SRINIVASAN, SESHA SAIRAMAN

Tech Center 2800 • Art Units: 2812 2817

This examiner grants 67% of resolved cases

Analysis

Srinivasan, Sesha Sairaman is a patent examiner assigned to Tech Center 2800 and Art Unit 2812. The examiner has reached a final resolution on 49 cases. The data shows an allowance rate of 67.3 percent, which provides a baseline for applicants to understand the frequency of patent grants in this specific unit. This percentage serves as a primary metric for evaluating the likelihood of success during the examination process.

The prosecution timeline is characterized by a median of 1356 days to allowance. This figure represents the typical duration for an application to move from filing to a successful issuance. Practitioners should incorporate this 1356 day median into their long-term strategic planning and client expectations regarding the speed of prosecution under this examiner.

Direct communication appears to be a productive strategy, as evidenced by an interview lift of 27.4 percent. This metric indicates that the probability of an allowance increases when an interview is conducted. The 27.4 percent lift suggests that verbal engagement is an effective tool for resolving outstanding issues. These combined statistics from Art Unit 2812 offer a data-grounded view of the examiner's historical performance.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

67.3%
Allow Rate
-0.7% vs TC avg
109
Total Applications
+27.4%
Interview Lift
1356
Avg Prosecution Days
Based on 49 resolved cases, 2023–2026

Rejection Statute Breakdown

0%
§101 Eligibility
19.0%
§102 Novelty
74.9%
§103 Obviousness
5.0%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
17965268 IMAGE SENSOR Non-Final OA Samsung Electronics Co., Ltd.
18530291 FRAME STRUCTURES IN SEMICONDUCTOR PACKAGES Final Rejection Apple Inc.
17707294 PAD STRUCTURE, DISPLAY DEVICE, AND MANUFACTURING METHOD THEREOF Final Rejection Samsung Display Co., LTD.
18369278 DISPLAY DEVICE Final Rejection LG DISPLAY CO., LTD.
18394347 VERTICAL FIELD-EFFECT TRANSISTOR STRUCTURE AND METHOD FOR PRODUCING A VERTICAL FIELD-EFFECT TRANSISTOR STRUCTURE Non-Final OA Robert Bosch GmbH
18739185 HIGH-BANDWIDTH MEMORY (HBM) PACKAGE-ON-PACKAGE (POP) DYNAMIC RANDOM-ACCESS MEMORY (DRAM) WITH SEMICONDUCTOR PILLARS Non-Final OA QUALCOMM Incorporated
18091616 TECHNOLOGIES FOR PACKAGE SUBSTRATES WITH ASYMMETRIC PLATING Non-Final OA Intel Corporation
17975654 LIQUID METAL SHIELD FOR FINE PITCH INTERCONNECTS Final Rejection Intel Corporation
18050527 PACKAGE EDGE PASSIVE COMPONENT ARRAY FOR IMPROVED POWER INTEGRITY Final Rejection Intel Corporation
18047033 PACKAGE SUBSTRATE WITH DUAL DAMASCENE BASED SELF-ALIGNED VIAS Non-Final OA Intel Corporation
17848630 HYPER DENSITY PACKAGE SUBSTRATE AND MEMORY COUPLED TO A MODIFIED SEMI-ADDITIVE PROCESS BOARD Final Rejection Intel Corporation
18499383 SEMICONDUCTOR PACKAGE STRUCTURE Non-Final OA MEDIATEK INC.
18228261 STACKED FIELD EFFECT TRANSISTORS Final Rejection International Business Machines Corporation
18290714 POWER SEMICONDUCTOR DEVICE Non-Final OA Hitachi Energy Ltd
18237059 THERMAL SPREADER Final Rejection SK Hynix NAND Product Solutions Corp. (dba Solidigm)
18465759 MAGNETIC MEMORY DEVICE Non-Final OA Kioxia Corporation
18465748 SEMICONDUCTOR DEVICE WITH BOTTOM DIELECTRIC ISOLATOR AND MANUFACTURING METHOD THEREOF Non-Final OA TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
18096389 SEMICONDUCTOR DEVICE STRUCTURE INCLUDING FORKSHEET TRANSISTORS AND METHODS OF FORMING THE SAME Non-Final OA TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
17832443 Passive Device Structure Final Rejection Taiwan Semiconductor Manufacturing Company, Ltd.
18555342 METHODS AND APPLICATIONS OF NOVEL AMORPHOUS HIGH-K METAL-OXIDE DIELECTRICS BY SUPER-CYCLE ATOMIC LAYER DEPOSITION Non-Final OA Applied Materials, Inc.
18147684 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF Non-Final OA NANYA TECHNOLOGY CORPORATION
18435227 METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR CHIP WITH CHIP OUTLINE OF VARIOUS SHAPES AT WAFER LEVEL Non-Final OA SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
18464761 VERTICAL ALUMINUM GALLIUM NITRIDE DEVICES ON CRYSTALLINE METALLIC SUBSTRATES Final Rejection University of South Carolina
17658031 CUTTING METHOD OF WAFER Final Rejection DISCO CORPORATION
18118736 ELECTRONIC PACKAGE STRUCTURE Non-Final OA Advanced Semiconductor Engineering, Inc.
17494689 METHOD OF MANUFACTURING ELECTRICAL PACKAGES USING HALF-CUT AND GRINDING OPERATIONS OF ELECTRONIC UNITS Final Rejection Advanced Semiconductor Engineering, Inc.
18744675 Semiconductor structure including silicon-on-insulator substrate and its manufacturing method Non-Final OA UNITED MICROELECTRONICS CORP.
18473998 POWER MODULE STRUCTURE WITH CLIP SUBSTRATE MEMBER Final Rejection SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

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