DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 04/17/2026 has been entered. Applicant’s amendments to the claim rejections under 35 USC §112 have overcome each and every rejections previously set forth in the Final Office Action mailed on 02/18/2026, so the rejection to the claims have been withdrawn. Claims 11 and 17 have been amended, claims 18-19 have been canceled, and new claims 21-28 have been added. Applicant’s amendments to the claims are noted.
Therefore, claims 11-17 and 20-28 have been fully considered in examination.
Response to Arguments
Applicant's arguments filed on 04/17/2026 have been fully considered but they are not persuasive. Regarding the arguments on pages 7-8, Werkheiser (US20100155956A1) discloses a multilevel interconnect structure in which symmetrical fill patterns are inserted into one or more interconnect levels on a level-by-level basis (Para [0007]-[0008], [0017]-[0020], [0040]-[0047]), and interconnect structure 500 of Fig. 5 is itself a multilevel structure spanning interconnect levels M2-M5, in which the fill patterns of levels M2, M3, and M5 are intentionally omitted from the figure for clarity (Para [0047]). It therefore would have been obvious to provide the recited first and second fill patterns in one interconnect level and the third and fourth fill patterns in a different interconnect level, as set forth below.
Specification
The objection to the specification set forth in the previous Office action is withdrawn in view of Applicant’s amendment to paragraph [0065].
Claim Objections
The objection to claim 11 is withdrawn in view of Applicant’s amendment, which amends the claim to recite “wherein the second fill pattern is a mirror image of the first fill pattern across a line.”
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15-17 and 21-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 11 and 21 recite “a first electronic device” and “a second electronic device,” while claims 15-17, 21, 25-27 refer to “the first device” and “the second device, for which there is insufficient antecedent basis.
Claim 21 recites “wherein the third fill pattern is over the first device or the second direction in the direction.” The limitation “the second direction” lacks antecedent basis, as the claim previously recites only “a direction” and does not introduce “a second direction.”
Furthermore, the phrase “the third fill pattern is over the first device or the second direction in the direction” is unclear and cannot be reconciled with the remainder of the claim, rendering the metes and bounds of the claim indefinite. For purpose of examination, the limitation is interpreted as “wherein the third fill pattern is over the first device or the second device in the direction,” consistent with the first and second devices recited earlier in the claim.
Claim 21 further recites “wherein the third fill pattern are in a second layer.” The plural verb “are” does not agree with the singular subject “the third fill pattern,” rendering it unclear whether the third fill patterns, or some additional element, is intended to be in the second layer.
Claims 22-28 are also rejected being dependent on rejected claim 21.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-17 and 20-28 are rejected under 35 U.S.C. 103 as being unpatentable over Werkheiser (US20100155956A1).
Regarding claim 11, Werkheiser teaches an integrated circuit (IC) device (Para [0009] & Fig. 5, interconnect structure 500), comprising:
a first fill pattern (first symmetrical portion) comprising first fill structures (fill tiles 504);
a second fill pattern (second symmetrical portion) comprising second fill structures (fill tiles 504), wherein the second fill pattern is a mirror image of the first fill pattern across a line (symmetry plane 502-Y);
a third fill pattern comprising third fill structures (Fig. 5 & Para [0040]-[0047], a symmetrical fill pattern of fill tiles 504 in a further interconnect level of the multilevel interconnect structure 500, e.g., one of levels M2, M3, or M5);
a fourth fill pattern comprising fourth fill structures, wherein the fourth fill pattern is a mirror image of the third fill pattern (Fig. 5 & Para [0040]-[0047], a second symmetrical portion of the same further interconnect level, the fill patterns of the two side-sharing symmetrical portions being related by a mirror reflection per Para [0048]);
a first electronic device, the first electronic device at least partially surrounded by the first fill structures and at least partially located at a first side of the line (Para [0026], circuit elements; transistors M1-M7);
a second electronic device, the second electronic device at least partially surrounded by the second fill structures and at least partially located at a second side of the line, wherein the second side is opposite the first side (Para [0026], circuit elements; transistors M1-M7),
wherein the first fill pattern, the second fill pattern, the first electronic device, and the second electronic device are in a first layer, and wherein the third fill pattern and the fourth fill pattern are in a second layer that is different from the first layer (Para [0017-0020] & Fig. 1A-5, ILD layer 126 of level M1 forming the first layer, and ILD layer 130 forming the second layer over and different from the first layer of a multilevel interconnect structure).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to apply third and fourth fill patterns in a second interconnect level different from the first level, as Werkheiser expressly teaches inserting symmetrical fill patterns into each of a plurality of interconnect levels on a level-by-level basis (Para [0017-0020], [0040-0047]); Fig. 5, levels M2-M5). Doing so amounts to applying a known technique to additional levels of the same multilevel structure to predictably meet the per-level DFM density specifications and reduce post-CMP topology variation (Para [0021-0023]). See MPEP 2143(I)(C), (D); KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
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Regarding claim 12, Werkheiser teaches the IC device according to claim 11, further comprising a fill structure, a portion of which is located on the line (Fig. 5, fill tiles 504 are located on the symmetry plane 502-Y).
Regarding claim 13, Werkheiser teaches the IC device according to claim 12, wherein the fill structure has a line symmetry across the line (Para [0048] & Fig. 5, fill tiles 504 located on the symmetry plane 502-Y are symmetrical with respect to the symmetry plane 502-Y).
Regarding claim 14, Werkheiser teaches the IC device according to claim 11, wherein an individual first fill structure or an individual second fill structure comprises a metal that is not connected to any of a signal source, a power source, or a reference potential during operation of the IC device (Para [0020], a plurality of square or rectangular, electrically floating tiles 204 of metal fill placed between the metal tracks).
Regarding claim 15, Werkheiser teaches the IC device according to claim 11, wherein a portion of the first device is a mirror image of a portion of the second device across the line (Para [0048] and Fig. 5, transistors M2-M5 are symmetrical with respect to the symmetry plane 502-Y).
Regarding claim 16, Werkheiser teaches the IC device according to claim 11, wherein a first portion of the first device is a mirror image of a second portion of the first device across the line (Para [0048] and Fig. 5, transistors M2-M5 are symmetrical with respect to the symmetry plane 502-Y).
Regarding claim 17, Werkheiser teaches the IC device according to claim 11, further comprising:
a fifth fill pattern comprising fifth fill structures (Fig. 5, one portion of the two or more symmetrical portions located above the symmetry plane 502-X comprising fill tiles 504); and
a sixth fill pattern comprising sixth fill structures (Fig. 5, one portion of the two or more symmetrical portions located below the symmetry plane 502-X comprising fill tiles 504),
wherein:
the fifth fill pattern is a mirror image of the sixth fill pattern across a different line in the IC device (the symmetry plane 502-X),
the first device is at least partially surrounded by the fifth fill structures (Para [0026], circuit elements; transistors M1-M7), and
the second device is at least partially surrounded by the sixth fill structures (Para [0026], circuit elements; transistors M1-M7).
Regarding claims 18 and 19, these claims have been canceled by Applicant’s amendment; accordingly, the rejections of claims 18 and 19 are moot.
Regarding claim 20, Werkheiser teaches the IC device according to claim 11, wherein the first fill pattern is substantially identical to the second fill pattern (para [0048] & Fig. 5, fill patterns in any two side-sharing quadrants can be superimposed by a mirror reflection).
Regarding claim 21, Werkheiser teaches an integrated circuit (IC) device (Para [0009] & Fig. 5, interconnect structure 500), comprising:
a first fill pattern (first symmetrical portion) comprising first fill structures (fill tiles 504);
a second fill pattern (second symmetrical portion) comprising second fill structures (fill tiles 504), wherein the second fill pattern is a mirror image of the first fill pattern across a line (symmetry plane 502-Y);
a third fill pattern comprising third fill structures (Fig. 5, one portion of the two or more symmetrical portions located above the symmetry plane 502-X comprising fill tiles 504); a first electronic device, the first electronic device at least partially surrounded by the first fill structures and at least partially located at a first side of the line (Para [0026], circuit elements; transistors M1-M7); and
a second electronic device, the second electronic device at least partially surrounded by the second fill structures and at least partially located at a second side of the line, wherein the second side is opposite the first side (Para [0026], circuit elements; transistors M1-M7),
wherein the first fill pattern, the second fill pattern, the first electronic device, and the second electronic device are in a first layer, wherein the third fill pattern is in a second layer that is different from the first layer, wherein the second layer is over the first layer in a direction, and wherein the third fill pattern is over the first device or the second device in the direction (Para [0017-0020] & Fig. 1A-5, ILD layer 126 of level M1 forming the first layer and ILD layer 130 forming the second layer over the first layer of a multilevel interconnect structure, the upper-level fill pattern being disposed over the devices of the lower level).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to arrange the first and second fill patterns in a first interconnect level and the third fill pattern in a second, different interconnect level disposed over the first level, for the same reasons set forth above with respect to claim 11. Werkheiser expressly teaches a multilevel interconnect structure in which symmetrical fill patterns are inserted into each of a plurality of interconnect levels on a level-by-level basis (Para [0017]-[0020], [0040]-[0047], Fig. 4 steps 410 and 416; Fig. 5 spanning levels M2-M5), and doing so would have predictably satisfied the per-level DFM density specifications and reduced post-CMP topology variation across the levels of the structure (Para [0021]-[0023]). See MPEP 2143(I)(C), (D); KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Regarding claim 22, Werkheiser teaches the IC device according to claim 21, further comprising a fill structure, a portion of which is located on the line (Fig. 5, fill tiles 504 are located on the symmetry plane 502-Y).
Regarding claim 23, Werkheiser teaches the IC device according to claim 22, wherein the fill structure has a line symmetry across the line (Para [0048] & Fig. 5, fill tiles 504 located on the symmetry plane 502-Y are symmetrical with respect to the symmetry plane 502-Y).
Regarding claim 24, Werkheiser teaches the IC device according to claim 21, wherein an individual first fill structure or an individual second fill structure comprises a metal that is not connected to any of a signal source, a power source, or a reference potential during operation of the IC device (Para [0020], a plurality of square or rectangular, electrically floating tiles 204 of metal fill placed between the metal tracks).
Regarding claim 25, Werkheiser teaches the IC device according to claim 21, wherein a portion of the first device is a mirror image of a portion of the second device across the line (Para [0048] & Fig. 5, transistors M2-M5 are symmetrical with respect to the symmetry plane 502-Y).
Regarding claim 26, Werkheiser teaches the IC device according to claim 21, wherein a first portion of the first device is a mirror image of a second portion of the first device across the line (Para [0048] & Fig. 5, transistors M2-M5 are symmetrical with respect to the symmetry plane 502-Y).
Regarding claim 27, Werkheiser teaches the IC device according to claim 21, further comprising:
a fourth fill pattern comprising fourth fill structures (Fig. 5, one portion of the two or more symmetrical portions located above the symmetry plane 502-X comprising fill tiles 504); and
a fifth fill pattern comprising fifth fill structures (Fig. 5, one portion of the two or more symmetrical portions located below the symmetry plane 502-X comprising fill tiles 504),
wherein:
the fourth fill pattern is a mirror image of the fifth fill pattern across a different line in the IC device (the symmetry plane 502-X),
the first device is at least partially surrounded by the fourth fill structures (Para [0026], circuit elements; transistors M1-M7), and
the second device is at least partially surrounded by the fifth fill structures (Para [0026], circuit elements; transistors M1-M7).
Regarding claim 28, Werkheiser teaches the IC device according to claim 21, wherein the first fill pattern is substantially identical to the second fill pattern (Para [0048] & Fig. 5, fill patterns in any two side-sharing quadrants can be superimposed by a mirror reflection).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAHAE KIM whose telephone number is (571)270-1844. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at (571) 272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JAHAE KIM/Examiner, Art Unit 2897
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