DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 10/20/2025 has been entered. Applicant’s amendments to the claim rejections under 35 USC §112 have overcome each and every rejections previously set forth in the Non-Final Office Action mailed on 07/18/2025, so the rejection to the claims have been withdrawn. Claims 11 and 13 have been amended. Applicant’s amendments to the claims are noted. Therefore, claims 11-20 have been fully considered in examination.
Response to Arguments
Applicant's arguments filed on 10/20/2025 have been fully considered but they are not persuasive. Regarding the arguments on pages 5-6, Werkheiser (US20100155956A1) teaches the first device comprising one or more electronic components a first device, at least partially surrounded by the first fill structures and at least partially located at a first side of the line, the first device comprising one or more electronic components (Para [0026], circuit elements, transistors M1-M7, are surrounded by the fill tiles in the area of the first and second symmetrical portions).
Specification
The disclosure is objected to because of the following informalities: Paragraph [0065] contains a typographical error in the phrase “devices 170 are minimized,” which should read “devices 270 are minimized.”
Appropriate correction is required.
Claim Objections
Claim 11 is objected to because of the following informalities: Claim 11 recites, “wherein the second fill pattern a mirror image of the first fill pattern across a line,” which fails to clearly define the relationship between the first fill pattern and the second fill pattern. For example, the phrase may be written in a grammatically correct form as “wherein the second fill pattern is a mirror image of the first fill pattern across a line.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ),
second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject
matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the
applicant), regards as the invention.
Claim 11 recites “the line is a symmetric axis” is unclear because it does not clearly define the role of the line with respect to the claimed mirror symmetry, whereas “symmetry axis” does.
Claims 12-20 are also rejected being dependent on rejected claim 11.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Werkheiser (US20100155956A1).
Regarding claim 11, Werkheiser teaches an integrated circuit (IC) device (Para [0009] & Fig. 5, interconnect structure 500), comprising:
a first fill pattern (first symmetrical portion) comprising first fill structures (fill tiles 504);
a second fill pattern (second symmetrical portion) comprising second fill structures (fill tiles 504), wherein the second fill pattern a mirror image of the first fill pattern across a line, wherein the line is a symmetric axis of at least part of the IC device (symmetry plane 502-Y);
a first device, at least partially surrounded by the first fill structures and at least partially located at a first side of the line, the first device comprising one or more electronic components (Para [0026], circuit elements; transistors M1-M7);
a second device, at least partially surrounded by the second fill structures and at least partially located at a second side of the line, wherein the second side is opposite the first side (Para [0026], circuit elements; transistors M1-M7).
PNG
media_image1.png
734
895
media_image1.png
Greyscale
Regarding claim 12, Werkheiser teaches the IC device according to claim 11, further comprising a fill structure, a portion of which is located on the line (Fig. 5, fill tiles 504 are located on the symmetry plane 502-Y).
Regarding claim 13, Werkheiser teaches the IC device according to claim 12, wherein the fill structure has a line symmetry across the line (Para [0048] & Fig. 5, fill tiles 504 located on the symmetry plane 502-Y is a symmetrical with respect to the symmetry plane 502-Y).
Regarding claim 14, Werkheiser teaches the IC device according to claim 11, wherein an individual first fill structure or an individual second fill structure comprises a metal that is not connected to any of a signal source, a power source, or a reference potential during operation of the IC device (Para [0020], a plurality of square or rectangular, electrically floating tiles 204 of metal fill placed between the metal tracks).
Regarding claim 15, Werkheiser teaches the IC device according to claim 11, wherein a portion of the first device is a mirror image of a portion of the second device across the line (Para [0048] and Fig. 5, transistors M2-M5 are symmetrical with respect to the symmetry plane 502-Y).
Regarding claim 16, Werkheiser teaches the IC device according to claim 11, wherein a first portion of the first device is a mirror image of a second portion of the first device across the line (Para [0048] and Fig. 5, transistors M2-M5 are symmetrical with respect to the symmetry plane 502-Y).
Regarding claim 17, Werkheiser teaches the IC device according to claim 11, further comprising:
a third fill pattern comprising third fill structures (Fig. 5, one portion of the two or more symmetrical portions located above the symmetry plane 502-X comprising fill tiles 504); and
a fourth fill pattern comprising fourth fill structures (Fig. 5, one portion of the two or more symmetrical portions located below the symmetry plane 502-X comprising fill tiles 504),
wherein:
the third fill pattern is a mirror image of the fourth fill pattern across a different line in the IC device (the symmetry plane 502-X),
the first device is at least partially surrounded by the third fill structures (Para [0026], circuit elements; transistors M1-M7), and
the second device is at least partially surrounded by the fourth fill structures (Para [0026], circuit elements; transistors M1-M7).
Regarding claim 18, Werkheiser teaches the IC device according to claim 11, further comprising:
a first layer comprising the first device, the second device, the first fill pattern, and the second fill pattern (Para [0017-0020] & Fig. 1A-5, ILD layer 126 of level M1); and
a second layer over the first layer, the second layer comprising a third fill pattern and a fourth fill pattern (Para [0017-0020] & Fig. 1A-5, ILD layer 130 of level M1), wherein the third fill pattern is a mirror image of the fourth fill pattern across an additional line in the second layer (Fig. 1A-5,), wherein the additional line is over the line (Para [0020], a multilevel interconnect structure that can be used to replace interconnect structure 120 in IC 100).
Regarding claim 19, Werkheiser teaches the IC device according to claim 11, further comprising a first layer comprising the first device, the second device, the first fill pattern, and the second fill pattern (Para [0017-0020] & Fig. 1A-5, ILD layer 126 of level M1); and
a second layer over the first layer, the second layer comprising a fill structure over the first device or the second device (Para [0017-0020] & Fig. 1A-5, ILD layer 130 of level M1).
Regarding claim 20, Werkheiser teaches the IC device according to claim 11, wherein the first fill pattern is substantially identical to the second fill pattern (para [0048] & Fig. 5, fill patterns in any two side-sharing quadrants can be superimposed by a mirror reflection).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAHAE KIM whose telephone number is (571)270-1844. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at (571) 271-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JAHAE KIM/ Examiner, Art Unit 2897