DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-18 and 20 are pending in this office action and presented for examination. Claims 1-8, 13-17, and 20 are newly amended, and claim 19 is newly cancelled, by the response received April 2, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-16, 18, and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites the limitation “at least one of a register file and a level-one cache” in line 5. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0077]) does not provide support for the recited processor core having just a register file (but not a level-one cache), which is a scenario encompassed by the claim language in view of the “at least one” language. For example, the original disclosure (e.g., paragraph [0077]) does not provide support for the recited processor core having just a level-one cache (but not a register file), which is a scenario encompassed by the claim language in view of the “at least one” language.
Claim 1 recites the limitation “issue one or more element operations generated from the micro-operation to each of one or more lanes of the backend pipeline” in lines 10-11. However, the original disclosure does not provide support for this limitation. For example, the original disclosure does not provide support for generating, from a [same] micro-operation, one or more element operations, and issuing these one of more element operations to “each of” one or more lanes of the backend pipeline (such that the one or more element operations are issued to a first lane, the [same] one or more element operations are issued to a second lane, and so forth).
For example, while paragraph [0051] of the original disclosure conveys that “For the SIMD unit, a single uOP has multiple element operations each having a width of a lane”, the original disclosure does not provide support for one or more element operations (which each have a width of a lane), from a single uOP, collectively being issued to a first lane, the aforementioned one or more element operations also collectively being issued to a second lane, and so forth.
For example, while paragraph [0055] of the original disclosure conveys that “element operations generated from different uOPs are issued from the element operation issuing unit to the lanes #1 and #2, and two element operations generated from one uOP are issued to the lanes #3 and #4”, the original disclosure does not provide support for one or more element operations, generated from the one uOP, being issued to “each of” lanes #1 and #2 (such that the one or more element operations are issued to lane #1, and the aforementioned one or more element operations are also issued to lane #2). (Similarly, the original disclosure does not provide support for one or more element operations, generated from the one uOP, being issued to “each of” lanes #3 and #4 (such that the one or more element operations are issued to lane #3, and the aforementioned one or more element operations are also issued to lane #4.)
Claim 1 recites the limitation “process the one or more element operations in each of the one or more lanes” in lines 15-16. However, the original disclosure does not provide support for this limitation. For example, the original disclosure does not provide support for processing, from a [same] micro-operation, one or more element operations, in “each of” the one or more lanes (such that the one or more element operations are processed in a first lane, the [same] one or more element operations are processed in a second lane, and so forth).
For example, while paragraph [0051] of the original disclosure conveys that “For the SIMD unit, a single uOP has multiple element operations each having a width of a lane”, the original disclosure does not provide support for one or more element operations (which each have a width of a lane), from a single uOP, collectively being issued to a first lane to be processed, the aforementioned one or more element operations also collectively being issued to a second lane to be processed, and so forth.
For example, while paragraph [0055] of the original disclosure conveys that “element operations generated from different uOPs are issued from the element operation issuing unit to the lanes #1 and #2, and two element operations generated from one uOP are issued to the lanes #3 and #4”, the original disclosure does not provide support for one or more element operations, generated from the one uOP, being issued to “each of” lanes #1 and #2 (such that the one or more element operations are issued to lane #1, and the aforementioned one or more element operations are also issued to lane #2) to be processed. Similarly, the original disclosure does not provide support for one or more element operations, generated from the one uOP, being issued to “each of” lanes #3 and #4 (such that the one or more element operations are issued to lane #3 to be processed, and the aforementioned one or more element operations are also issued to lane #4 to be processed.
Claim 1 recites the limitation “stop the processing of the corresponding section while allowing others in the sections to continue processing to absorb a processing speed difference between the sections” in lines 23-25. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0073]) does not appear to provide support for stopping the processing of the corresponding section while allowing others in the sections to continue processing “to absorb a processing speed difference between the sections”.
Claims 2-16, 18, and 20 are rejected for failing to alleviate the rejections of claim 1 above.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-16, 18, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the multi-bank configuration” in lines 22-23. However, this limitation is indefinite as to whether this limitation is intended to have antecedent basis to a multi-bank configuration of a register file as conveyed in claim 1, line 5; a multi-bank configuration of a level-one cache as conveyed in claim 1, line 5; or something else.
Claim 1 recites the limitation “others in the sections” in line 24. However, the metes and bounds of “others” are indefinite; for example, it is indefinite as to what entities in the sections are being referring to by this limitation.
Claim 1 recites the limitation “stop the processing of the corresponding section while allowing others in the sections to continue processing to absorb a processing speed difference between the sections” in lines 23-25. However, the metes and bounds of this limitation are indefinite; for example, it is indefinite as to what it generally means to “absorb a processing speed difference”, and also indefinite as to how the recited continuing processing embodies the aforementioned absorbing.
Claims 2-16, 18, and 20 are rejected for failing to alleviate the rejections of claim 1 above.
Allowable Subject Matter
Claim 17 is allowed.
Response to Arguments
Applicant on page 11 argues: ‘Claims 1-20 are rejected under 35 U.S.C. § 112(b) as being indefinite. The Examiner's suggested corrections were much appreciated, many of which are made above. With regard to the antecedent basis issue for the various recitations of "the sections" and "the buffers," amended claim 1 now recites "an entirety of the backend pipeline is separated into a plurality of sections by buffers including a plurality of entries" which provides clear antecedent basis support for "the sections" and "the buffers." Accordingly, withdrawal of these rejections is respectfully requested.’
In view of the amendments to the claims, the previously presented indefinite rejections are withdrawn.
Applicant on page 11 argues: “The Examiner's reminder that claim 17 was not rejected over the prior art and is otherwise allowable (with these 112(b) rejections having been overcome) was much appreciated. Accordingly, claim 17 is now in condition for allowance.”
In view of the overcome indefinite rejections, claim 17 is now allowed.
Applicant on page 12 argues: “This combination of features (i) circuitry that individually stops a specific section, (ii) triggered specifically by a bank conflict in a multi-bank memory, and (iii) allowing all other sections to continue processing by absorbing the speed difference through downstream buffers not taught, disclosed, or suggested by any of the cited references, alone or in combination. For at least these reasons, withdrawal of these rejections is respectfully requested.”
Examiner generally notes for the purposes of compact prosecution—while no prior art rejection is presented in the instant office action in view of the newly amended claims, these newly amended claims are subject to various issues under 35 USC 112, and the prior art rejection presented in the previous office action may be relevant to further amended claims that address the aforementioned issues under 35 USC 112—that Bhamidipati as cited in the previous office action appears to teach the concept of a section being stopped while other sections continue processing, and Olson as cited in the previous office action appears to render obvious bank conflicts in particular causing stopping.
Applicant across pages 12-13 argues: ‘Bhamidipati discloses a decoupling queue interposed between a high-frequency core pipeline and a lower-frequency functional unit for the purpose of handling clock-domain differences. As depicted in Applicant's annotated FIG. 2, Bhamidipati's queue (reference A32) is essentially a passive data relay — it accepts data on one side and releases it on the other, but it does not comprise any circuitry configured to individually stop the processing of a specific section of a backend pipeline in response to a bank conflict. As noted in Applicant's annotation to FIG. 2: "Bank conflict occurs at Bank #2; only Bank #2 is stopped — the entire pipeline is NOT stopped. " This selective, section-level stop control distinguishes over Bhamidipati. Bhamidipati's queue simply lacks any circuitry or logic configured to achieve the above-noted features. Bhamidipati's teachings have no awareness of bank conflicts and no mechanism to isolate a conflicting section while allowing others to proceed.’
Examiner generally notes that Bhamidipati as cited in the previous office action appears to teach the concept of a section being stopped while other sections continue processing, and Olson as cited in the previous office action appears to render obvious bank conflicts causing stopping.
Applicant across pages 13-14 argues: ‘Zaidi discloses a dependency matrix technique, and Potter and Olson disclose operand caching techniques, all designed to optimize pipeline performance. Much like Fig. 5 of the present application illustrating an In-Step backend pipeline for comparative purposes, these references operate on the fundamental premise that the backend pipeline moves in-step (synchronously) i.e., all lanes and all sections advance together in lock-step. In FIG. 5, the In-Step backend pipeline (reference C8) runs across all lanes simultaneously, so if one point stops, the entire pipeline stops under unified control. In contrast, amended claim 1 with the above-noted features is directed to an Out-of-Step backend pipeline (see, e.g., Fig. 6) in which the pipeline registers (e.g., reference 102) within each section (Sections A, B, and C) operate independently. The specification at paragraph [0073] expressly states that these sections are configured to "operate independently in units of sections." The independent operation depicted in FIG. 6 with each section capable of stopping individually without affecting adjacent sections is structurally and functionally distinct from anything taught in Zaidi, Potter, or Olson.’
Examiner generally submits that while the overall inventive concept of the instant application may be distinct from the overall inventive concept of each of the aforementioned references, the manner in which the references were used in the previously presented rejection (e.g., to render obvious particular limitations), as explained in the previously presented rejection, was valid.
Applicant on page 14 argues: “Even if a skilled artisan were to attempt to combine the teachings of Bhamidipati with those of Zaidi and Potter, such a combination would not yield the claimed invention and would, in fact, require a fundamental reversal of the basic design philosophy of each reference. Zaidi's dependency matrix and Potter's operand caching are premised on the entire pipeline moving synchronously. Incorporating these techniques into the Out-of-Step architecture of the present invention in which individual sections stop and restart independently based on local bank conflict events would destroy the synchronization assumptions on which Zaidi and Potter rely. Any attempt to graft the present invention's Out-of-Step control logic onto these In-Step references would require rebuilding the synchronization logic from the ground up, which is not a matter of routine optimization but a fundamental architectural reversal. If the proposed modification or combination of the prior art would change the principle of operation of the prior art invention being modified, then the teachings of the references are not sufficient to render the claims prima facie obvious. See, MPEP 2143.01(VI); In re Ratti, 270 F.2d 810, 123 USPQ 349 (CCPA 1959).”
Examiner generally submits that incorporating the particular teachings of Zaidi and Potter relied upon in the previously presented rejection into Bhamidipati, as explained in the previous office action, would not require a fundamental reversal of the basic design philosophy of each reference. For example, Potter, in the independent claim, was merely relied upon to explicitly teach the concept of SIMD instructions, rather than, for example, operand caching, and Examiner submits that modifying Bhamidipati to support the capability of performing a single instruction on multiple pieces of data would not require a fundamental reversal of the basic design philosophy of Bhamidipati. (Also note that while such a modification may entail additional power, such does not mean that a designer would necessarily not accept such a trade-off in exchange for increased performance.)
Applicant on page 15 argues: “The combination proposed by the Examiner would require deploying advanced cache control logic (Potter/Olson) and complex dependency matrix circuitry (Zaidi) across all sections of a decoupling-queue-based pipeline (Bhamidipati). The resulting circuit area and power consumption would increase dramatically, running counter to the design objectives of each individual reference. A skilled artisan would recognize that such a combination would produce an inefficient design that defeats the purpose of the individual references. Amended claim 1, in contrast, achieves efficiency by narrowly targeting the bank conflict as the specific triggering event, thereby avoiding unnecessary complexity.”
Examiner generally submits that the rationales for obviousness of the previously presented rejection were valid, and generally submits that increased complexity or power consumption does not necessarily preclude a prior art combination, as a designer may prioritize other design factors such as performance.
Applicant on page 15 argues: “Bhamidipati's high-frequency pipeline architecture requires tight timing constraints. Introducing Zaidi's complex matrix operations or Potter's cache look-up logic into the dynamically decoupled sections of the present invention would critically lengthen the timing path, potentially reducing the achievable clock frequency. The combination would thus undermine the high-frequency operation that Bhamidipati itself is designed to achieve — an additional reason why the combination is not suggested and would not be undertaken by a skilled artisan with a reasonable expectation of success.”
Examiner generally submits that a prior art combination is not precluded merely because the achievable clock frequency of an architecture may be reduced, as a designer may accept a trade-off of lower clock frequency in exchange for other common design goals (e.g., overall throughput).
Applicant on page 16 argues: “The present invention produces an unexpected result that would not be predicted by one of ordinary skill in the art from the teachings of the cited references. As illustrated in FIG. 12 of the application, when the SIMD width (v) is increased, the throughput improvement ratio of the present invention (Curve M3) scales linearly, even under conditions of frequent bank conflicts such as those arising during Gather/Scatter operations. In contrast, in conventional In-Step (synchronous) pipelines representative of the architecture underlying Bhamidipati, Zaidi, and Potter a single bank conflict stops all lanes simultaneously. As the SIMD width increases, the probability of a bank conflict rises, causing throughput to saturate (Curves M1 and M2 in FIG. 12). Amended claim 1 breaks through this physical throughput ceiling by stopping only the specific lane that encountered the bank conflict, while all other lanes continue processing (with the above-noted claimed features). This linear scalability at wide SIMD widths is an unexpected result that cannot be predicted from the individual references or their combination.”
However, amended claim 1 does not appear to specifically reflect the capability described above. For example, Examiner notes that claim 1 does not appear to require more than one lane.
Applicant across pages 16-17 argues: “In conventional processor architectures, a runtime hazard such as a bank conflict typically triggers one of two high-cost penalties: (a) a pipeline-wide stall, or (b) cancellation and re- execution (flush/re-issue) of in-flight instructions. Both penalties impose substantial throughput costs. Amended claim 1 avoids both penalties entirely. When a bank conflict occurs in a corresponding section, the "circuitry configured to individually stop" that section acts as a local circuit breaker, temporarily buffering the affected element operations in the immediately downstream buffer while allowing all other sections to continue processing uninterrupted. As stated in the specification at paragraph [0117], the circuitry selectively stops the conflicting section while continuing the remainder with no pipeline flush and no re-execution penalty. Bhamidipati's decoupling queue is designed for clock-domain bridging and does not contemplate, teach, or suggest this type of hazard-triggered, section-specific isolation. The complete avoidance of pipeline-wide stalls and re-execution is a further unexpected benefit of the present invention.”
Examiner generally notes that Bhamidipati as cited in the previous office action nevertheless appears to teach the concept of a section being stopped while other sections continue processing.
Applicant across pages 17-18 argues: ‘The combination of the "circuitry" of amended claim 1 with the dependent-element- operation issuing timing of claim 2 produces an additional synergistic effect not achievable by the cited references individually or in combination. Specifically, when the circuitry stops a section due to a bank conflict, the dependency matrix (as recited in claim 13) determines the bypass path for execution results. Once the bypass path is established, the multi-bank register file access that originally caused the conflict can be omitted entirely. The present invention thus achieves not merely "not stopping" the overall pipeline, but also reducing the very register accesses that are the source of bank conflicts. This is a holistic optimization a synergistic efficiency gain that cannot be obtained by simply patching together Bhamidipati, Zaidi, and Potter. See In re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986) (unexpected synergistic effects support non-obviousness).’
Examiner generally submits that the combination of references explained in the previous office action nevertheless rendered obvious the specific relevant claim language.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH E VICARY whose telephone number is (571)270-1314. The examiner can normally be reached Monday to Friday, 9:00 AM to 5:00 PM.
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/KEITH E VICARY/Primary Examiner, Art Unit 2183
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