DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention 2, drawn to claims 9-20, in the reply filed on 05/28/2024 is acknowledged.
Claims 1-8 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group I, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/28/2024.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being taught by Kub et al (US-20180315820-A1, pub date 11/01/2018, hereinafter “Kub”).
Regarding claim 16, figs. 1-3A of Kub teach:
providing a semiconductor structure including a substrate (308, para. [0063]), a first semiconductor layer (306, para. [0063]), and a second semiconductor layer (302, para. [0063]);
forming a plurality of fins (the combination of channels 306A and 302) having sidewall surfaces (the sidewalls of the fins are made up of 306 material and 302 material) in a portion of the first semiconductor layer (306) and the second semiconductor layer (302), wherein the plurality of fins (combination of channels 306A and 302) are separated by trenches (filled with material 1304A);
providing a third semiconductor layer (304A, para. [0063] and [0064]) coupled to the sidewall surfaces of the plurality of fins (304A is on the sidewalls of the fins, which are the combination of 306A and 302), wherein the third semiconductor layer includes a dopant (304A is p-type and therefore doped) and comprises a recessed gate region (304A forms a gate region that is recessed in form); and
forming a source metal (see fig. 11, step 1116, where additional sources and metal contacts are patterned on top of the channels), a gate metal (304A), and a drain contact (310).
Regarding claim 18, figs. 1-3A of Kub teach the third semiconductor layer (304A, para. [0063] and [0064]) extends along a portion of the sidewall surfaces of the plurality of fins (304A is on the sidewalls of the fins, which are the combination of 306A and 302).
Regarding claim 19, figs. 1-3A of Kub teach forming an edge termination for the recessed gate region (304A forms a gate region that is recessed in form) (1006) overlaying a top surface of the first semiconductor layer (the 304B elements form a termination towards the edge of the fin component of the device).
Regarding claim 20, fig. 1-3A of Kub teaches the third semiconductor layer (304A, para. [0063] and [0064]) comprises a conformal layer (304A is conformal to the fins).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kub in view of Adekore et al. (US-20130043468-A1, pub 08/18/2015, hereinafter “Adekore”).
Regarding claim 17, Kub teaches the limitations of claim 16 as provided above. Kub does not teach performing a thermal treatment to activate the dopant in the recessed gate region.
However, in a similar field of endeavor, Adekore teaches performing a thermal treatment to activate the dopant in the recessed gate region (para. [0095], "the implanted layers can be further subjected to rapid thermal annealing processes in activated ambient of, for example, nitrogen or argon at temperatures of about 200° C. to 1050° C.").
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Adekore into the vertical FET device of Kub to form a vertical FET device formed using a method step of thermally treating particular regions of the device.
One would have been motivated to do so as Adekore teaches that thermally treating a layer can be “used to prepare a metal substrate” (para. [0096]) as needed for different embodiments. This preparation could allow the substrate to bond better to subsequent layers, or on the reverse allow only certain layers to bond well to the substrate in particular regions, for example.
Allowable Subject Matter
Claims 9-15 are allowed.
The following is an examiner’s statement of reasons for allowance: The closest prior art of record, Kub, does not teach “forming a patterned hard mask coupled to the second semiconductor layer; … applying a sacrificial planarization layer on the diffusion dopant layer; selectively etching the sacrificial planarization layer to expose the diffusion dopant layer; … removing the diffusion dopant layer and the patterned hard mask;” of independent claim 9. Similarly, Adekore does not teach these features. Claim 9 is therefore allowable over the prior art of record. Claims 10-16, since they depend from claim 9, are therefore also allowable.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TESSA E MCNAMEE whose telephone number is (703)756-1079. The examiner can normally be reached Mon-Fri 8:00-5:00 PST.
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/TESSA ELIZABETH MCNAMEE/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
