Prosecution Insights
Last updated: October 23, 2026
Application No. 17/669,381

HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME

Final Rejection §102
Filed
Feb 11, 2022
Priority
Jan 14, 2022 — CN 202210041542.8
Examiner
LOKE, STEVEN HO YIN
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
United Microelectronics Corp.
OA Round
4 (Final)
40%
Grant Probability
At Risk
5-6
OA Rounds
0m
Est. Remaining
74%
With Interview

Examiner Intelligence

Grants only 40% of cases
40%
Career Allowance Rate
31 granted / 78 resolved
-28.3% vs TC avg
Strong +35% interview lift
Without
With
+34.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
9 currently pending
Career history
94
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
52.8%
+12.8% vs TC avg
§102
29.3%
-10.7% vs TC avg
§112
16.7%
-23.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 78 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 10, 11 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shimizu et al. (US 2018/0204916 A1). Regarding to claim 10, Shimizu et al. show all the elements of the claimed invention in figs. 1 and 9. It is a high electron mobility transistor (HEMT) ([0044]), comprising: a buffer layer [12] ([0045]) on a substrate [10] ([0045]); a barrier layer [16] ([0045]) on the buffer layer [12]; a p- type semiconductor layer [22] ([0045]) on the barrier layer [16]; a first layer ([0095], "the silicon oxide layer [30] side is negative" which means the silicon oxide layer [30] has a negative charge) adjacent to and directly contacting one sidewall of the p-type semiconductor layer [22] (the right side sidewall of the p-type semiconductor layer [22]); wherein the first layer [30] is a single layer made of a single material (silicon oxide); and a second layer (a composite layer [28, 30, 32]) ([0045]) having a first positive charge region ([0095], "the second aluminum oxide layer [32] side is positive" which means the second aluminum oxide layer [32] has a positive charge) adjacent to another sidewall of the p-type semiconductor layer [22] (the left side sidewall of the p-type semiconductor layer [22]). Regarding to claim 11, Shimizu et al. further disclose a passivation layer [34] ([0045]) on the p-type semiconductor layer [22]; a gate electrode [24] ([0045]) on the passivation layer [34]; and a source electrode [18] ([0045]) and a drain electrode [20] ([0045]) adjacent to two sides of the gate electrode [24]. Regarding to claim 21, Shimizu et al. further disclose the second layer [28, 30, 32] directly contacts another sidewall of the p-type semiconductor layer [22] ([28, 30, 32] is in direct contact with the left side sidewall of the p-type semiconductor layer [22]). Response to Arguments Applicant's arguments filed 2/4/26 have been fully considered but they are not persuasive. It is urged, in page 6 of the remarks, that Shimizu fails to disclose that the first layer is a single layer made of a single material. However, Shimizu does disclose that the first layer [30] is a single layer made of a single material (silicon oxide). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN HO YIN LOKE whose telephone number is (571)272-1657. The examiner can normally be reached 10 am to 6:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Fristoe can be reached at (571)272-4926. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Show 1 earlier event
Apr 08, 2025
Non-Final Rejection mailed — §102
Jun 04, 2025
Response Filed
Sep 12, 2025
Final Rejection mailed — §102
Oct 07, 2025
Request for Continued Examination
Oct 11, 2025
Response after Non-Final Action
Dec 30, 2025
Non-Final Rejection mailed — §102
Feb 04, 2026
Response Filed
Oct 02, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12660388
SEMICONDUCTOR DEVICE WITH TRANSMISSIVE LAYER AND MANUFACTURING METHOD THEREOF
2y 2m to grant Granted Jun 16, 2026
Patent 12550428
SEMICONDUCTOR DEVICE
2y 12m to grant Granted Feb 10, 2026
Patent 12364077
MICRO LIGHT EMITTING DEVICE, DISPLAY APPARATUS INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE MICRO LIGHT EMITTING DEVICE
4y 4m to grant Granted Jul 15, 2025
Patent 12302695
DISPLAY DEVICE
3y 9m to grant Granted May 13, 2025
Patent 12094824
SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE
1y 5m to grant Granted Sep 17, 2024
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
40%
Grant Probability
74%
With Interview (+34.6%)
3y 1m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 78 resolved cases by this examiner. Grant probability derived from career allowance rate.

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