DETAILED ACTION
In view of the appeal brief filed on 12/04/2025, PROSECUTION IS HEREBY REOPENED. A new ground of rejection is set forth with a new reference set forth below.
To avoid abandonment of the application, appellant must exercise one of the following two options:
(1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or,
(2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid.
A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below:
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, more detail of how element 108 (metal pad) connects to the backside of the semiconductor device and the leadframe, as well as drawings showing the die pad connecting to said lead frame as claimed in claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, in the preamble a semiconductor device is claimed to comprise certain elements, of which one of the limitations is the connection of the metal pad to the backside of said semiconductor device. One cannot have a semiconductor device comprising certain elements where one of the claimed elements is the device itself. Additionally, it is unclear what is meant by “backside” of the semiconductor device as no reference is made. Additionally, the same issue arises where the semiconductor device comprises certain elements, one of which connects to the backside of the semiconductor device, where the semiconductor device is an element making up the claimed device, rendering the claim unclear. It is recommended to the applicant that such language as “a semiconductor package comprises” and if there is a die attached to the die pad, the applicant claim said die such that a semiconductor device is separate from the claimed invention. Or claim as part of the semiconductor device “a bottom conductive layer under all other elements of the semiconductor device” [then claim the connections as desired].
Claims 2-13 include all the elements of claim 1, and are rejected for the same reasons as above.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gong et al (US 9437528 B1).
Gong et al teaches
[claim 1] A semiconductor device comprising: a lead frame (col 5 lines 50-57, figure 9, element 2 is the lead frame and the semiconductor device is the entire device pictured in figures 9 and 10);
a metal pad on a top surface of the lead frame, wherein the metal pad is connected to a back side of the semiconductor device via the lead frame (figures 9 and 10, col 5 lines 29-57, where element 5 [metal clip] is the metal pad [and includes vertical elements 502] and it situated on a top surface of the lead frame [element 2, the lead frame, is situated below the device shown in figure 10 and connects to elements 211, 212, 213], and thus element 5 connects to the back side [bottom] of the semiconductor device via the lead frame);
a die pad on the top surface of the lead frame, wherein the die pad is attached to the lead frame via a die attach material (figures 9 and 10, col 5 lines 29-57, where element 101 is the die attach and element 211 is the die pad and is situated on the lead frame [element 2 is situated below the entire device pictured in figure 10, which can also be seen in figure 9]),
and an encapsulant disposed on the top surface of the lead frame; wherein the encapsulant isolates the metal pad on the top surface of the lead frame from the die pad on the top surface of the lead frame (figures 9 and 10, col 5 lines 29-57, where element 6 is the encapsulant and is situated on a top surface of the leadframe [figure 10, element 6 on element 2], and separates the metal pad [element 5/502] from the die pad [element 211]).
[claims 6] the semiconductor device wherein the semiconductor device is a device selected from the group consisting of a diode, a MOSFET transistor, a bipolar transistor, and a semiconductor device with more than three I/Os (col 4 lines 20-38).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Gong et al (US 9437528 B1) in view of Blansaer (US 20210118778 A1).
Gong et al teaches the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 2] the semiconductor device as claimed in claim 1, wherein the lead frame acts as a heat sink.
However, Blansaer does teach
[claim 2] the semiconductor device as claimed in claim 1, wherein the lead frame acts as a heat sink (abstract, where “heat-sink lead frame” is understood to be a lead frame acting as a heat-sink).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Gong et al to incorporate the teachings of Blansaer in order to reduce the overall thermal resistance of the semiconductor package, hence allowing higher heat dissipation. Additionally, it would have been obvious to have the semiconductor device be a MOSFET in order to create the building block for numerous circuits and applications which is widely known in the art, for example to build an RF amplifier a MOSFET is a required basic component of said circuit.
Regarding claim 9, Gong et al additionally teaches
[claims 9] the semiconductor device wherein the semiconductor device is a device selected from the group consisting of a diode, a MOSFET transistor, a bipolar transistor, and a semiconductor device with more than three I/Os (col 4 lines 20-38).
Claim(s) 3, 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Gong et al (US 9437528 B1) in view of David et al (US 20210057314 A1).
Gong et al teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 3] the semiconductor device as claimed in claim 1, wherein the lead frame is pre-plated with a surface finish.
[claim 5] the semiconductor device as claimed in claim 1, wherein the surface finish is NlPdAu.
However, David et al does teach
[claim 3, 5] the semiconductor device as claimed in claim 1, wherein the lead frame is pre- plated with a surface finish that is NlPdAu (paragraph 0051).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Gong et al with the teachings of David et al in order to put a specific finish on the lead frame, in this case NiPdAu, in order to enhance solderability and the semiconductor device to be a diode in order to create a functional device for sensing or other means.
Regarding claim 10, Gong et al further teaches
[claim 10] the semiconductor device as claimed in claim 3, wherein the semiconductor device is a device selected from the group consisting of a diode, a MOSFET transistor, a bipolar transistor, and a semiconductor device with more than three I/Os (col 4 lines 20-38).
Claim(s) 4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Gong et al (US 9437528 B1) in view of Xiaochun et al (US 20080164590 A1).
Gong et al teaches all of the limitation of the parent claim, claim 1, but do not specifically disclose
[claim 4] the semiconductor device as claimed in claim 1, wherein the die attach material is a conductive die attach film, a silver epoxy or a sintering material.
However Xioachun et al does teach
[claim 4] the semiconductor device as claimed in claim 1, wherein the die attach material is a conductive die attach film, a silver epoxy or a sintering material (paragraph 0045).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gong et al with Xiaochun et al in order to allow a conductive connecting material between the die and the lead frame, and use a transistor as the die in order to make and use a transistor device which is widely known in the art to be the basic building block of many circuits, so that one could use, for example, an RF amplification circuit in the device.
[claim 12] the semiconductor device as claimed in claim 4, wherein the semiconductor device is a device selected from the group consisting of a diode, a MOSFET transistor, a bipolar transistor, and a semiconductor device with more than three I/Os (col 4 lines 20-38).
Claim(s) 7 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Gong et al (US 9437528 B1) and Blansaer (US 20210118778 A1) in further view of David et al (US 20210057314 A1).
Gong et al as modified teaches all of the limitation of the parent claim, claim 2, but do not specifically disclose
[claim 7] the semiconductor device as claimed in claim 2, wherein the lead frame is pre- plated with a surface finish.
[claim 13] the semiconductor device as claimed in claim 7, wherein the surface finish is NiPdAu.
However, David et al does teach
[claim 7] the semiconductor device as claimed in claim 2, wherein the lead frame is pre- plated with a surface finish, such as NiPdAu (paragraph 0051).
[claim 13] the semiconductor device as claimed in claim 7, wherein the surface finish is NiPdAu (paragraph 0051).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Gong et al as modified with the teachings of David et al in order to put a specific finish on the lead frame, in this case NiPdAu, in order to enhance solderability.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable Gong et al (US 9437528 B1), and Blansaer (US 20210118778 A1) in further view of Xiaochun et al (US 20080164590 A1).
Gong et al as modified teaches all of the limitation of the parent claim, claim 2, but do not specifically disclose:
[claim 8] wherein the die attach material is a conductive die attach film, a silver epoxy or a sintering material.
However, Xiaochun et al does teach
[claim 8] the semiconductor device as claimed in claim 2, wherein the die attach material is a conductive die attach film, a silver epoxy or a sintering material (paragraph 0045).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gong et al as modified with Xiaochun et al in order to allow a conductive connecting material between the die and the lead frame so that the die can connect to other periphery circuits outside the constrains of the die.
Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Gong et al (US 9437528 B1), and David et al (US 20210057314 A1) in further view of Xiaochun et al (US 20080164590 A1).
Gong et al as modified teaches all of the limitation of the parent claim, claim 3, but does not specifically disclose
[claim 11] the semiconductor device as claimed in claim 3, wherein the die attach material is a conductive die attach film, a silver epoxy or a sintering material.
However, Xiaochun et al does teach
[claim 11] the semiconductor device as claimed in claim 3, wherein the die attach material is a conductive die attach film, a silver epoxy or a sintering material (paragraph 0045).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gong et al as modified with Xiaochun et al in order to allow a conductive connecting material between the die and the lead frame so that the die can connect to other periphery circuits outside the constrains of the die.
Conclusion
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 572-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANDREW ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818