DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 09/17/2025 is in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Response to Amendment
The amendment with respect to claims 19-20 filed on 09/17//2025 have been fully considered for examination based on their merits. The previously presented claim 20 has been considered. New claims 30-47 have been fully considered for examination based on their merits. Claims 22-29 are withdrawn. Claims 1-18 are canceled.
Response to Arguments
Applicant’s arguments, see Remarks, pages 8-10, filed 09/17/2025, with respect to the rejection(s) of claim(s) 19-21 under U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of CHIU in view of CHANG.
Regarding Independent Claim 19. The Applicant argues (see Remarks, page 9) that the Office has not shown how WU, CHANG, LEGALLY and CAO, alone or in combination, disclose or suggest obvious the features of amended claim 19. The Examiner agrees to the arguments and therefore, the rejection has been withdrawn, however upon further consideration of amended Claim 19, a new grounds of rejection is made in view of CHIU in view of CHANG.
Regarding dependent Claims 20-21. The claims 20-21 depends on the independent claim 19, and are rejected on the similar reasons mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 19-21, 30-35, 39, and 47 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsin-Ying Chiu et al, (hereinafter CHIU), US 20120286244 A1, in view of Josephine Chang et al, (hereinafter CHANG), US 20110309334 A1.
Regarding Claim 19, CHIU teaches an electronic device (Fig. 1, 100, semiconductor FET device) comprising:
a gate structure (Fig. 1, 140);
a source electrode (Fig. 1, 180);
a drain electrode (Fig. 1, 180); and
a channel (Fig. 130) between the source electrode and the drain electrode (Fig. 1, 180),
wherein the gate structure (Fig. 1, 140) comprises a substrate (Fig. 1, 110);
a gate electrode (Fig. 1, 150) on the substrate (Fig. 1, 110);
a gate insulating layer (Fig. 1, 170, insulating spacer) configured to face at least three different surfaces (annotated Figure 1) of the gate electrode (Fig. 1, 150); and
a carbon layer (Fig. 1, 160, charged monolayer, may be formed of any suitable organic material, [0027]) between (Fig. 1, [0026]) the gate electrode (Fig. 1, 150) and the gate insulating layer (Fig. 1, 170, insulating spacer).
PNG
media_image1.png
718
924
media_image1.png
Greyscale
Though CHIU teaches an electronic device, wherein the gate structure comprises, the charged monolayer, such as organic thiols as carbon-based layer, between the gate electrode and the gate insulating layer, CHIU does not explicitly disclose an electronic device, wherein the gate structure comprises, the carbon layer between the gate electrode and the gate insulating layer.
CHANG teaches an electronic device (Fig. 5, 500, device), wherein the gate structure (annotated Figure 5) comprises, the carbon layer (Fig. 5, 401, may include carbon, [0027]) between the gate electrode (Fig. 5, 301, gate, [0026]) and the gate insulating layer (Fig. 5, 501, dielectric material, [0028]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHIU to incorporate the teachings of CHANG, such that an electronic device, wherein the gate structure comprises, the carbon layer between the gate electrode and the gate insulating layer, so that the contact material comprises carbon or silicon, the contact material may be converted to a metal carbide or a metal silicide in order to reduce the contact resistance of contact material, 401 (CHANG, [0030]).
PNG
media_image2.png
765
823
media_image2.png
Greyscale
Regarding Claim 20, CHIU as modified by CHANG teaches the electronic device (Fig. 1, 100, semiconductor FET device) of claim 19.
CHIU further teaches the electronic device (Fig. 1, 100, semiconductor FET device),
wherein the gate insulating layer (Fig. 1, 170, insulating spacer), the carbon layer (Fig. 1, 160, charged monolayer, may be formed of any suitable organic material, [0027]), and the gate electrode (Fig. 1, 150) are sequentially stacked (Figures 2D-2G; method for constructing a carbon nanostructure transistor device, [0012]) on a side surface of the channel (Fig. 130) corresponding to the source electrode (Fig. 1, 180) and the drain electrode (Fig. 1, 180).
CHANG further teaches an electronic device (Fig. 5, 500, device), wherein the gate insulating layer (Fig. 5, 501, dielectric material, [0028]), the carbon layer (Fig. 5, 401, may include carbon, [0027]), and the gate electrode (Fig. 5, 301, gate, [0026]) are sequentially stacked (annotated Figure 5) on a side surface of the channel (Fig. 5, 203, channel)
PNG
media_image2.png
765
823
media_image2.png
Greyscale
Regarding Claim 21, CHIU as modified by CHANG teaches an electronic apparatus comprising: the electronic device of claim 19.
CHIU further teaches an electronic apparatus (Si CMOS devices/carbon nanostructure transistor, [0004], [0009]) comprising:
the electronic device (Fig. 1, 100, semiconductor FET device), wherein
the electronic device (Fig. 1, 100, semiconductor FET device) is configured to regulate a flow of an electrical signal (Fig. 1, gate electrode, 150, can be used to tune the threshold voltage, [0032]).
Regarding Claim 30, CHIU teaches a gate structure (Fig. 1, 140) comprising:
a substrate (Fig. 1, 110);
a gate electrode (Fig. 1, 150) on the substrate (Fig. 1, 110);
a gate insulating layer (Fig. 1, 170, insulating spacer) configured to face at least three different surfaces (annotated Figure 1) of the gate electrode (Fig. 1, 150); and
a carbon layer (Fig. 1, 160, charged monolayer, may be formed of any suitable organic material, [0027]) between (Fig. 1, [0026]) the gate electrode (Fig. 1, 150) and the gate insulating layer (Fig. 1, 170, insulating spacer).
PNG
media_image1.png
718
924
media_image1.png
Greyscale
Though CHIU teaches the gate structure comprising, the charged monolayer, such as organic thiols as carbon-based layer, between the gate electrode and the gate insulating layer, CHIU does not explicitly disclose an electronic device, wherein the gate structure comprises, the carbon layer between the gate electrode and the gate insulating layer.
CHANG teaches an electronic device (Fig. 5, 500, device), wherein the gate structure (annotated Figure 5) comprises, the carbon layer (Fig. 5, 401, may include carbon, [0027]) between the gate electrode (Fig. 5, 301, gate, [0026]) and the gate insulating layer (Fig. 5, 501, dielectric material, [0028]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHIU to incorporate the teachings of CHANG, such that an electronic device, wherein the gate structure comprises, the carbon layer between the gate electrode and the gate insulating layer, so that the contact material comprises carbon or silicon, the contact material may be converted to a metal carbide or a metal silicide in order to reduce the contact resistance of contact material, 401 (CHANG, [0030]).
PNG
media_image2.png
765
823
media_image2.png
Greyscale
Regarding Claim 31, CHIU as modified by CHANG teaches the gate structure of claim 30.
CHIU further teaches the gate structure (Fig. 1, 140),
wherein the carbon layer (Fig. 1, 160, charged monolayer, may be formed of any suitable organic material, [0027]) is configured to cover the at least three different surfaces (annotated Figure 1) of the gate electrode (Fig. 1, 150).
PNG
media_image1.png
718
924
media_image1.png
Greyscale
CHANG further teaches the gate structure (annotated Figure 5),
wherein the carbon layer (Fig. 5, 401, may include carbon, [0027]) is configured to cover the at least three different surfaces (annotated Figure 5) of the gate electrode (Fig. 5, 301, gate, [0026]).
PNG
media_image3.png
791
823
media_image3.png
Greyscale
Regarding Claim 32, CHIU as modified by CHANG teaches the gate structure of claim 31.
CHIU further teaches the gate structure (Fig. 1, 140),
wherein the carbon layer (Figs. 1, 160, charged monolayer, may be formed of any suitable organic material, [0027]) is configured to cover four different surfaces (annotated Figure 1) of the gate electrode (Fig. 1, 150).
PNG
media_image4.png
718
924
media_image4.png
Greyscale
CHANG further teaches the gate structure (annotated Figure 5),
wherein the carbon layer (Fig. 5, 401, may include carbon, [0027]) is configured to cover the at least four different surfaces (annotated Figure 5) of the gate electrode (Fig. 5, 301, gate, [0026]).
(NOTE: For the broadest reasonable interpretation and after considering the plain meaning of “cover” which is interpreted as “overlap” (https://www.onelook.com/thesaurus/?s=overlap; and further with respect to the top view, the carbon layer appears to cover all four different surfaces of the gate electrode. For the sake of arguendo, Examiner consider the fourth surface of the gate electrode is covered by additional carbon layer, for CHIU’s art, the additional carbon layer is the channel layer, 130 may be formed of carbon nanostructure, such as carbon nanotubes or a graphene [0025] and for the CHANG’s art, the additional carbon layer is the channel layer, 203, may be one or more sheets of graphene, or may include nanostructures such as carbon nanotubes or semiconductor nanowires, [0025]).
PNG
media_image5.png
791
823
media_image5.png
Greyscale
Regarding Claim 33, CHIU as modified by CHANG teaches the gate structure of claim 30.
CHIU further teaches the gate structure (Fig. 1, 140),
wherein the gate electrode (Fig. 1, 150), the carbon layer (Fig. 1, 160, charged monolayer, may be formed of any suitable organic material, [0027]), and the gate insulating layer (Fig. 1, 170, insulating spacer) are stacked in a direction perpendicular (annotated Figure 1) to an upper surface of the substrate (Fig. 1, 110).
PNG
media_image6.png
821
1025
media_image6.png
Greyscale
CHANG further teaches the gate structure (annotated Figure 5),
wherein the gate electrode (Fig. 5, 301, gate, [0026]), the carbon layer (Fig. 5, 401, may include carbon, [0027]), and the gate insulating layer (Fig. 5, 501, dielectric material, [0028]) are stacked in a direction perpendicular (annotated Figure 5) to an upper surface of the substrate (Fig. 5, 201, silicon substrate).
PNG
media_image7.png
791
939
media_image7.png
Greyscale
Regarding Claim 34, CHIU as modified by CHANG teaches the gate structure of claim 33.
CHIU further teaches the gate structure (Fig. 1, 140),
wherein the gate electrode (Fig. 1, 150), the carbon layer (Fig. 1, 160, charged monolayer, may be formed of any suitable organic material, [0027]), and the gate insulating layer (Fig. 1, 170, insulating spacer) are stacked in a direction parallel (annotated Figure 1) to the upper surface of the substrate (Fig. 1, 110).
PNG
media_image8.png
780
1028
media_image8.png
Greyscale
Regarding Claim 35, CHIU as modified by CHANG teaches the gate structure of claim 30.
CHIU further teaches the gate structure (Fig. 1, 140),
wherein the carbon layer (Fig. 1, 160, charged monolayer, may be formed of any suitable organic material, [0027]) is configured to cover an upper surface and a side surface (annotated Figure 1) of the gate electrode (Fig. 1, 150).
PNG
media_image9.png
792
924
media_image9.png
Greyscale
CHANG further teaches the gate structure (annotated Figure 5),
wherein the carbon layer (Fig. 5, 401, may include carbon, [0027]) is configured to cover an upper surface and a side surface (annotated Figure 5) of the gate electrode (Fig. 5, 301, gate, [0026]).
PNG
media_image10.png
791
867
media_image10.png
Greyscale
Regarding Claim 39, CHIU as modified by CHANG teaches the gate structure of claim 30, further comprising:
CHIU further teaches the gate structure (Fig. 1, 140), further comprising:
a channel layer (Fig. 1, 130) configured to face (annotated Figure 1) the gate insulating layer (Fig. 1, 170, insulating spacer).
PNG
media_image11.png
799
1046
media_image11.png
Greyscale
Regarding Claim 47, CHIU as modified by CHANG teaches the gate structure of claim 30.
CHIU further teaches the gate structure (Fig. 1, 140),
wherein the gate electrode (Fig. 2A, 155, gate electrode material, [0032]) includes a one-component metal or a two-component metal (one or more types of metallic material, [0032]).
Claim(s) 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHIU, in view of CHANG and further in view of Huaping Li, (hereinafter LI), US 20180323387 A1.
Regarding Claim 36, CHIU as modified by CHANG teaches the gate structure of claim 30.
CHIU as modified by CHANG does not explicitly disclose the gate structure, wherein the carbon layer is provided under the gate electrode and configured to cover an upper surface and a side surface of the gate insulating layer.
LI teaches the gate structure (annotated Figure 9, step 5), wherein the carbon layer (Figs. 5A/9, step 3, CNT thin film, [0102]) is provided under the gate electrode (Fig. 5A, Gate) and configured to cover an upper surface and a side surface (annotated Figure 9, step 3, [0102]) of the gate insulating layer (Fig. 9, step 5, SiNx/SiO2, gate dielectric, [0102]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHIU to incorporate the teachings of LI, such that the gate structure, wherein the carbon layer is provided under the gate electrode and configured to cover an upper surface and a side surface of the gate insulating layer, so that to convert an ambipolar carbon nanotube transistor to a unipolar carbon nanotube transistor by using gate structure engineering for improvements to the switching behavior of carbon nanotube FETs (Li, [0004-0005]).
PNG
media_image12.png
1031
1327
media_image12.png
Greyscale
Claim(s) 37-38, and 40-41 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHIU, in view of CHANG and further in view of Kuo-Cheng Ching et al, (hereinafter CHING), US 20200105902 A1.
Regarding Claim 37, CHIU as modified by CHANG teaches the gate structure of claim 30.
CHIU further teaches the gate structure (Fig. 1, 140),
CHIU as modified by CHANG does not teach the gate structure, wherein the gate electrode includes vertical portions that are perpendicular to an upper surface of the substrate and spaced apart from each other.
CHING teaches the gate structure (Fig. 11D, 510), wherein the gate electrode (Figs. 11B/11D, metal gate structure, 510 includes a metal gate electrode, [0035]) includes vertical portions (annotated Figure 11B) that are perpendicular (annotated Figure 11B) to an upper surface of the substrate (Fig. 11A, 105) and spaced apart from each other (annotated Figure 11B).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHIU to incorporate the teachings of CHING, such that the gate structure, wherein the gate electrode includes vertical portions that are perpendicular to an upper surface of the substrate and spaced apart from each other, so that the bridge formed by the spacer layer, 390 effectively increases a thickness of a dielectric material in a parasitic capacitor, which then helps to lower the parasitic capacitance of the semiconductor device, 100 (CHING, [0033]).
PNG
media_image13.png
1066
1294
media_image13.png
Greyscale
Regarding Claim 38, CHIU as modified by CHANG and CHING teaches the gate structure of claim 37,
CHING further teaches the gate structure (Fig. 11D, 510), wherein the gate electrode (Figs. 11B/11D, metal gate structure, 510 includes a metal gate electrode, [0035]) includes a plurality of bridges (Figs. 11B/11D, 390, spacer layer may for a “bridge”, [0033]) that are parallel each other and spaced apart from each other (annotated Figure 11B), and each of the plurality of bridges (Figs. 11B/11D, 390, spacer layer may for a “bridge”, [0033]) being is connected to the vertical portions (annotated Figure 11B).
Regarding Claim 40, CHIU as modified by CHANG teaches the gate structure of claim 39,
CHIU as modified by CHANG does not teach gate structure further comprising: wherein the channel layer includes a vertical portion that is perpendicular to an upper surface of the substrate and a horizontal portion that is parallel to the upper surface of the substrate.
CHING teaches the gate structure (Fig. 11D, 510) further comprising: wherein the channel layer (Fig. 11B, 120, wires) includes a vertical portion that is perpendicular to an upper surface (annotated Figure 11B) of the substrate (Fig. 11A, 105) and a horizontal portion that is parallel to the upper surface (annotated Figure 11B) of the substrate (Fig. 11A, 105).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHIU to incorporate the teachings of CHING, such that the gate structure further comprising: wherein the channel layer includes a vertical portion that is perpendicular to an upper surface of the substrate and a horizontal portion that is parallel to the upper surface of the substrate, so that the bridge formed by the spacer layer, 390 effectively increases a thickness of a dielectric material in a parasitic capacitor, which then helps to lower the parasitic capacitance of the semiconductor device, 100 (CHING, [0033]).
Regarding Claim 41, CHIU as modified by CHANG and CHING teaches the gate structure of claim 40,
CHING further teaches the gate structure (Fig. 11D, 510) further comprising:
wherein the gate insulating layer (Fig. 11B/11D, 370, a spacer layer), the carbon layer (Figs. 11B/11D, 390, spacer layer may for a “bridge”, [0033]), and the gate electrode (Figs. 11B/11D, metal gate structure, 510 includes a metal gate electrode, [0035]) are sequentially stacked on a side surface of the vertical portion (annotated Figure 11B) of the channel layer (Fig. 11B, 120, wires).
Claim(s) 42 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHIU, in view of CHANG, in view of Sandip Niyogi, (hereinafter NIYOGI), US 20150179743 A1, and further in view of NPL: J.C. Lascovich, R. Giorgi, S. Scaglione, (hereinafter LASCOVICH), Evaluation of the sp2/sp3 ratio in amorphous carbon structure by XPS and XAES, Applied Surface Science, Volume 47, Issue 1, 1991, Pages 17-21, ISSN 0169-4332, https://doi.org/10.1016/0169-4332(91)90098-5.
Regarding Claim 42, CHIU as modified by CHANG teaches the gate structure of claim 30.
CHIU as modified by CHANG does not explicitly disclose the gate structure, wherein the carbon layer includes an sp2 bond and an sp3 bond, and a ratio of sp3 bonding to sp2 bonding in the carbon layer is about 0 to 1.
SANDIP teaches the gate structure (annotated Figure 4), wherein the carbon layer (Fig. 4, 410, amorphous carbon, [0039]) includes an sp2 bond and an sp3 bond, and a ratio of sp3 bonding to sp2 bonding in the carbon layer is about 0 to 1 (Fig. 4, 410, amorphous carbon refers to carbon having a maximum ratio to sp3 to sp2 bonds of 50% and hydrogen may be bonded to the sp3 carbons, [0046]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHIU as modified by CHANG to incorporate the teachings of SANDIP, such that the gate structure, wherein the carbon layer includes an sp2 bond and an sp3 bond, and a ratio of sp3 bonding to sp2 bonding in the carbon layer is about 0 to 1, so that by optimizing the process conditions, the amorphous carbon can be modified by ratio of sp3 to sp2 bonding for obtaining single or multiple graphene layers for the device fabrication, (SANDIP, [0047]).
PNG
media_image14.png
943
1084
media_image14.png
Greyscale
Though SANDIP teaches the gate structure, wherein the carbon layer includes an sp2 bond and sp3 bond and a ratio of sp3 bonding to sp2 bonding in the carbon layer is 50%, CHIU as modified by CHANG and SANDIP does not explicitly disclose the gate structure, wherein the carbon layer includes an sp2 bond and an sp3 bond, and a ratio of sp3 bonding to sp2 bonding in the carbon layer is about 0 to 1.
LASCOVICH teaches the gate structure (feature as discussed in the Abstract), wherein the carbon layer (hydrogenated samples of amorphous carbon (i-C:H), [Abstract]) includes an sp2 bond and an sp3 bond, and a ratio of sp3 bonding to sp2 bonding in the carbon layer is about 0 to 1 (values of the sp2/sp3 ratio between 0.5 and 1.5 have been found for hydrogen samples, whereas for amorphous carbon a value of 3 has been obtained, [Abstract]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHIU as modified by CHANG, SANDIP to incorporate the teachings of LASCOVICH, such that the gate structure, wherein the carbon layer includes an sp2 bond and an sp3 bond, and a ratio of sp3 bonding to sp2 bonding in the carbon layer is about 0 to 1, so that hydrogen amorphous carbon samples (i-C:H) show a fine structure (275-280 eV) which is assigned to KVV transitions involving pπ electrons (LASCOVICH, [Abstract]).
Claim(s) 43-44 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHIU, in view of CHANG and further in view of AliReza Alian et al, (hereinafter ALIAN), US 20180182849 A1.
Regarding Claim 43, CHIU as modified by CHANG teaches the gate structure of claim 30.
CHIU as modified by CHANG does not explicitly disclose the gate structure, wherein the carbon layer includes a graphene layer.
ALIAN teaches the gate structure (Fig. 1, 201, gate electrodes), wherein the carbon layer includes a graphene layer (Fig. 1, 103, the thin layer may comprise any suitable 2D conductive material, for example, the thin layer may comprise carbon, forming e.g. a graphene layer, [0059]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHIU to incorporate the teachings of ALIAN, such that the gate structure, wherein the carbon layer includes a graphene layer, so that some crystalline carbon layers such as graphene show semimetal properties, and with the graphene as 2D material in FET, the technology enables the control of atomic layers and nanotransistors can be obtained (ALIAN, [0003]).
Regarding Claim 44, CHIU as modified by CHANG and ALIAN teaches the gate structure of claim 43,
ALIAN further teaches the gate structure (Fig. 1, 201, gate electrodes), wherein the graphene layer Fig. 1, 103, the thin layer may comprise any suitable 2D conductive material, for example, the thin layer may comprise carbon, forming e.g. a graphene layer, [0059]) includes a nanocrystalline graphene layer (Fig. 1, 130, predetermined filed in different areas of the nanostructure, more particularly, in the layer of 2D material such as graphene, [0064]).
Claim(s) 45 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHIU, in view of CHANG, in view of ALIAN, and further in view of LI.
Regarding Claim 45, CHIU as modified by CHANG and ALIAN teaches the gate structure of claim 44,
ALIAN further teaches the gate structure (Fig. 1, 201, gate electrodes), wherein a size of the nanocrystalline graphene layer (Fig. 1, 130, predetermined filed in different areas of the nanostructure, more particularly, in the layer of 2D material such as graphene, [0064]) is in a range from about 0.5 nm to about 150 nm (the reference is made to “2D materials,” reference is made to crystalline materials with a thickness corresponding to a few atomic layers, e.g., not more than 20 atomic layers, not more than 10 atomic layers, not more than 5 atomic layers, one atomic layer (monolayer), or a thickness corresponding to a number of atomic layers in a range defined by any of these values, [0049]; (ALIAN further teaches the nanostructure FinFET comprising nanostructures such as nanowires, [0078]).
(NOTE 1: According to Wikipedia: one atomic layer of graphene is equivalent to 3.35 Å or 0.34 nm; 20 atomic layers is equivalent to 20 x 0.34 nm = 6.8 nm).
(NOTE 2: CHANG further teaches the gate structure (annotated Figure 5), wherein the nanocrystalline graphene layer are equated to nanostructures such as carbon nanotubes or semiconductor nanowires ([0024]; CHANG further teaches the bi-layer graphene sheets are stacked on each other with a normal staking distance roughly 3.35 angstrom which is equivalent to 0.34 nm [0007]).
PNG
media_image15.png
765
823
media_image15.png
Greyscale
CHIU as modified by CHANG and ALIAN does not explicitly disclose the gate structure, wherein a size of the nanocrystalline graphene layer is in a range from about 0.5 nm to about 150 nm.
LI teaches the gate structure (annotated Figure 9, step 5), wherein a size of the nanocrystalline graphene layer (Figs. 5A/9, step 3, CNT thin film, [0102]) is in a range from about 0.5 nm to about 150 nm (CNT TFT, intrinsic layer can remain thin (e.g. less than ~200 nm, [0093], [0121]).
PNG
media_image12.png
1031
1327
media_image12.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHIU as modified by CHANG and ALIAN to incorporate the teachings of LI, such that the gate structure, wherein a size of the nanocrystalline graphene layer is in a range from about 0.5 nm to about 150 nm, so that the intrinsic layer of the CNT TFT remain thin, and useful in a unipolar nanotube TFTs (LI, [0121]).
Claim(s) 46 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHIU, in view of CHANG and further in view of Chun-Hao Kung et al, (hereinafter KUNG), US 20200043777 A1.
Regarding Claim 46, CHIU as modified by CHANG teaches the gate structure of claim 30.
CHIU as modified by CHANG does not explicitly disclose the gate structure, wherein a water contact angle of the carbon layer is in a range from about 80°to about 110°.
KUNG teaches the gate structure (Fig. 8D, 740), wherein a water contact angle of the carbon layer is in a range from about 80°to about 110° (Fig. 8D, 780, hydrophobic layer, has a water contact angle in the range from about 50 degrees to about 180 degrees [0099]; the hydrophobic layer, 130/780, is more hydrophobic, the carbon (C) is detected as element present in the sample, [0055]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHIU as modified by CHANG to incorporate the teachings of KUNG, such that the gate structure, wherein a water contact angle of the carbon layer is in a range from about 80°to about 110°, so that the water contact angle range of the hydrophobic layer (containing carbon element), 130 represents that the surfaces of the hydrophobic layer, 130 is more hydrophobic than the second dielectric layer, 126. Thus the hydrophobic layer, 130 is used to reduce slurry from leaking into under layer due to capillary phenomenon (KUNG, [0055], [0067]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20080268582 A1 – Figure 8B
STATEMENT OF RELEVANCE – Sectional view showing manufacturing step of the transistor.
US 20200098564 A1 – Figure 14B
STATEMENT OF RELEVANCE – Various stages of a sequential process for manufacturing a FET using a single crystalline TMD layer.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812
/CHRISTINE S. KIM/
Supervisory Patent Examiner, Art Unit 2812