Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. (US 9,099,556).
Regarding claim 1, Chu et al. discloses a method of manufacturing a semiconductor device in figs. 4A-4C, the method comprising: forming an active area bounded by an isolation region [401] and including a source [405] and a drain [403] in the active area, wherein the active area has a channel [407] direction that extends between the source [405] and the drain [403] and a transverse direction that is transverse to the channel [407] direction and the active area has first and second active area edges (edges along [407]) on opposite sides of the active area that extend along the channel direction between the source and the drain, the first and second active area edges having respective first and second active area edge extensions [409, 411] that increase a width in the transverse direction of the active area at the edge extensions to a width greater than a minimum width of the active area in the transverse direction; forming a gate oxide [482] on a portion of the active area disposed between the source and the drain; and forming a gate [484] over the gate oxide [482].
Figs. 4A-4C of Chu et al. differs from the claimed invention by not showing the first and second active area edge extensions comprise respective first and second sawtooth, circle-tooth, or square-tooth areas that are at least partially covered by the gate.
Fig. 3E of Chu et al. shows showing the first and second active area edge extensions [316] comprise respective first and second sawtooth edge extensions.
Since both Figs. 4A-4C and Fig. 3E of Chu et al. disclose a MOSFET with edge extensions, It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the first and second sawtooth edge extensions of Fig. 3E of Chu et al. in Figs. 4A-4C of Chu et al. because they further reduce the electric field away from the current channel.
The combined structure shows the respective first and second sawtooth edge extensions are at least partially covered by the gate.
Regarding claim 16, Chu et al. discloses a semiconductor device in figs. 4A-4C, comprising: an active area bounded by an isolation region [401] and including a source [405] and a drain [403] in the active area, wherein the active area has a channel [407] direction that extends between the source [405] and the drain [403] and a transverse direction that is transverse to the channel direction and the active area has first and second active area edges (edges along [407]) on opposite sides of the active area that extend along the channel direction between the source and the drain; a gate oxide [482] disposed on a portion of the active area between the source and the drain; a gate [484] disposed over the gate oxide [482]; and a noise suppressing structure including first and second active area edge extensions [409, 411] of the respective first and second active area edges that increase a width in the transverse direction of the active area at the edge extensions to a width greater than a minimum width of the active area in the transverse direction.
Figs. 4A-4C of Chu et al. differs from the claimed invention by not showing the first and second active area edge extensions comprise respective first and second sawtooth, circle-tooth, or square-tooth areas that are at least partially covered by the gate.
Fig. 3E of Chu et al. shows showing the first and second active area edge extensions [316] comprise respective first and second sawtooth edge extensions.
Since both Figs. 4A-4C and Fig. 3E of Chu et al. disclose a MOSFET with edge extensions, It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the first and second sawtooth edge extensions of Fig. 3E of Chu et al. in Figs. 4A-4C of Chu et al. because they further reduce the electric field away from the current channel.
The combined structure shows the respective first and second sawtooth edge extensions are at least partially covered by the gate.
Claims 2, 3, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. (US 9,099,556) in view of McElheny et al. (US 6,740,944).
Regarding claim 2, Chu et al. differs from the claimed invention by not showing the method of after forming the gate oxide and before forming the gate, forming first and second edge oxide regions on the gate oxide with edges of the respective first and second edge oxide regions coinciding with the respective first and second active area edges, the first and second edge oxide regions not extending over a central area of the gate oxide; wherein the gate completely covers the first and second edge oxide regions.
McElheny et al. show further comprising: after forming the gate oxide and before forming the gate, forming first and second edge oxide regions (The composite oxide layer can be formed by forming a uniform first oxide layer followed by a non-uniform second oxide layer. The non-uniform second oxide layer is formed by placing a mask over the first oxide layer so that portions near the ends of the gate region are exposed to oxidation ambient, and further oxidized to form the non-uniform composite oxide layer; Process 400 further comprises processing steps associated with formation of a gate, LDD regions, spacers, and source and drain regions. Thus, the first and second edge oxide regions are formed after the gate oxide but before the forming the gate structure; see McElheny Fig. 4, [col. 7, lines 8-10], and [col. 7, lines 29- 38]) on the gate oxide with edges of the respective first and second edge oxide regions coinciding with the respective first and second active area edges (the oxide layers 205 and 206 have edges that coincide with the respective first and second active area edges defined by the isolation regions 230 and 240; see McElheny Fig. 3B), the first and second edge oxide regions not extending over a central area of the gate oxide (oxide layers 205 and 206 do not extend over a central area of oxide layer 210; see McElheny Fig. 3B); wherein the gate completely covers the first and second edge oxide regions (gate structure comprising of gate electrode 220 and spacers 290 and 295, completely covers the top surface of edge oxide regions 205 and 206; see McElheny Fig. 3C).
Since both Chu et al. and McElheny et al. disclose a MOSFET formed on an active region, It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the method of after forming the gate oxide and before forming the gate, forming first and second edge oxide regions on the gate oxide with edges of the respective first and second edge oxide regions coinciding with the respective first and second active area edges, the first and second edge oxide regions not extending over a central area of the gate oxide; wherein the gate completely covers the top surface of the first and second edge oxide regions because the first and second edge oxides regions increases the distance between the gate and source or drain near the ends of the gate, resulting in lower fringe capacitance and higher device speed. Thicker edge oxides also help to minimize leakage currents without adversely impacting the device threshold voltage since leakage currents are usually strongest at parts of the channel near the ends of the gate. The thicker oxides at the ends actually increases the threshold voltage required for turning on portions of the channel at the ends of the gate where leakage effects are strongest. The higher threshold voltage at the ends of the active area near the ends of the gate reduces the energy of any hot electrons produced there, and thereby enhances the reliability of the region (see McElheny [col. 5, lines 47-66]).
Regarding claim 3, the combination of Chu et al. and McElheny discloses the method of claim 2, wherein: the forming of the gate oxide uses a first photolithography mask (the first oxide layer is formed by placing a mask over the substrate, so that the mask covers most part of the active area of the device 200, leaving portions of the active area near ends of the gate region 225 exposed to an oxidation ambient; see McElheny Fig. 3F and [col. 7, lines 19-24]); and the forming of the first and second edge oxide regions on the gate oxide uses a second photolithography mask different from the first photolithography mask (the nonuniform second oxide layer is formed by placing a mask over the first oxide layer so that the mask covers most part of the active area of device 200, leaving portions of the active area near ends of the gate region 225 exposed to an oxidation ambient, and the substrate is then further oxidized in the oxidation ambient to form the nonuniform composite oxidation layer; see McElheny Fig. 3F and [col. 7, lines 32-38]).
Regarding claim 17, Chu et al. and McElheny et al. differ from the claimed invention by not showing the noise suppressing structure further comprises includes said first and second edge oxide regions disposed on the gate oxide with edges of the respective first and second edge oxide regions coinciding with the respective first and second active area edges, the first and second edge oxide regions not extending over a central area of the gate oxide and the gate disposed over the first and second edge oxide regions.
McElheny et al. disclose a noise suppressing structure further comprises includes said first and second edge oxide regions [205, 206] disposed on the gate oxide [210] with edges of the respective first and second edge oxide regions coinciding with the respective first and second active area edges (edges of [255] adjacent to regions [230, 240]), the first and second edge oxide regions not extending over a central area of the gate oxide [210] and the gate [220] disposed over the first and second edge oxide regions [205, 206].
Since both Chu et al. and McElheny et al. disclose a a MOSFET formed on an active region, It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the first and second edge oxide of McElheny et al. in Chu et al. because the first and second edge oxides regions increases the distance between the gate and source or drain near the ends of the gate, resulting in lower fringe capacitance and higher device speed. Thicker edge oxides also help to minimize leakage currents without adversely impacting the device threshold voltage since leakage currents are usually strongest at parts of the channel near the ends of the gate. The thicker oxides at the ends actually increases the threshold voltage required for turning on portions of the channel at the ends of the gate where leakage effects are strongest. The higher threshold voltage at the ends of the active area near the ends of the gate reduces the energy of any hot electrons produced there, and thereby enhances the reliability of the region (see McElheny [col. 5, lines 47-66]).
Regarding claim 18, Chu et al. and McElheny et al. disclose the gate [220] completely covers a top surface of the first and second edge oxide regions [205, 206] (see McElheny et al. figs, 3A and 3B).
10. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. in view of McElheny et al., further in view of Anderson et al. (US 20100044801).
Regarding claim 4, the combination of Chu et al. and McElheny discloses the method of claim 2, but fails to disclose wherein the method does not include forming ion implantation regions in the active area underneath the first and second edge oxide regions.
Anderson et al. discloses a semiconductor device (field effect transistor in Fig. 12), wherein the method does not include forming ion implantation regions in the active area underneath the first and second edge oxide regions (the method of forming the field effect transistor in Fig. 12 does not include forming ion implantation regions in the center portion 151 underneath the two second gate dielectric layers 412 that are formed on the edges of the first gate dielectric layer 411; see Fig. 12).
The teachings of Chu et al. and McElheny et al. are incorporated with the teachings of Anderson et al. by substituting the channel formation method of the combined teachings of Chu et al. and McElheny et al. in which low doped drain (LDD) regions are formed underneath the gate oxide layer, in the active region of the semiconductor substrate (LDD regions 270 and 275 are formed underneath the oxide layer 210 in an active region 255 in a semiconductor substrate 250; see McElheny et al. Fig. 3C, Fig. 4, [col. 5, lines 12-26], and [col.7, lines 8-13]) with the channel formation method of Anderson in which the center portion underneath the gate dielectric layer does not have any doped regions (see Anderson Fig. 12), so that the edge oxides of the combined device (edge oxide layers 205 and 206; see McElheny et al. Fig. 3B) do not have any doped regions beneath them.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of the combination of Chu et al. and McElheny et al. with the teachings of Anderson et al. wherein the combination discloses the method does not include forming ion implantation regions in the active area underneath the first and second edge oxide regions, because not doping the area underneath the edge oxide regions improves gate control and reduces undesirable effects such as band-to-band tunneling, current leakage, and short channel effects; and the combination is a simple substitution of one known element for another to obtain predictable results — substitution of the channel layer of Chu et al. and McElheny et al. which includes the LDD regions, with the channel region and center portion of Anderson, which has no doped regions formed
Claims 5, 21 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. in view of McElheny et al., further in view of Zhou (Pub. No.: US 20210074547 A1).
Regarding claim 5, the combination of Chu et al. and McElheny et al. discloses the method of claim 1, but fails to disclose wherein the gate oxide has a thickness of 4.0 nanometers or less.
Zhou discloses a semiconductor device (semiconductor device in Fig. 19), wherein the gate oxide (gate oxide 210; see Fig. 19) has a thickness that is greater than or equal to 2 nm and less than or equal to 5 nm (The gate oxide 210 has a thickness that is greater than or equal to 2 nm and less than or equal to 5 nm; see Fig. 19 and [0123)).
Zhou does not directly disclose with sufficient specificity wherein the gate oxide has a thickness of 4.0 nanometers or less. However, Zhou does teach a gate oxide layer 210 with a thickness that is greater than or equal to 2 nm and less than or equal to 5 nm (see Fig. 19 and [0123]). MEPEP 2144.05 | states “In the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists.” In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
The teachings of the combination of Chu et al. and McElheny et al. are incorporated with the teachings of Zhou by substituting the gate oxide layer in the combination of Chu et al. and McElheny et al. (oxide layer 210; see McElheny et al. Fig. 3B) with the gate oxide from the device of Zhou (gate oxide 210; see Zhou Fig. 19).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of the combination of Chu et al. and McElheny et al. with the teachings of Zhou, wherein the combination discloses wherein the gate oxide has a thickness that is greater than or equal to 2 nm and less than or equal to 5 nm, because a reduced oxide thickness allows for effective scaling of low voltage operation devices; and the combination is a simple substitution of one known element for another to obtain predictable results — substitution of the gate oxide layer of the combination of Chu et al. and McElheny et al., with the gate oxide layer of the device of Zhou.
Regarding claim 21, the combination of Chu et al. and McElheny et al. discloses the method of claim 1, but fails to disclose wherein the gate oxide has a thickness of 15.0 nanometers or less.
Zhou discloses a semiconductor device (semiconductor device in Fig. 19), wherein the gate oxide (gate oxide 210; see Fig. 19) has a thickness that is greater than or equal to 2 nm and less than or equal to 5 nm (The gate oxide 210 has a thickness that is greater than or equal to 2 nm and less than or equal to 5 nm; see Fig. 19 and [0123)).
Zhou does not directly disclose with sufficient specificity wherein the gate oxide has a thickness of 15.0 nanometers or less. However, Zhou does teach a gate oxide layer 210 with a thickness that is greater than or equal to 2 nm and less than or equal to 5 nm (see Fig. 19 and [0123]). MEPEP 2144.05 | states “In the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists.” In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
The teachings of the combination of Chu et al. and McElheny et al. are incorporated with the teachings of Zhou by substituting the gate oxide layer in the combination of Chu et al. and McElheny et al. (oxide layer 210; see McElheny et al. Fig. 3B) with the gate oxide from the device of Zhou (gate oxide 210; see Zhou Fig. 19).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of the combination of Chu et al. and McElheny et al. with the teachings of Zhou, wherein the combination discloses wherein the gate oxide has a thickness that is greater than or equal to 2 nm and less than or equal to 5 nm, because a reduced oxide thickness allows for effective scaling of low voltage operation devices; and the combination is a simple substitution of one known element for another to obtain predictable results — substitution of the gate oxide layer of the combination of Chu et al. and McElheny et al., with the gate oxide layer of the device of Zhou.
Regarding claim 29, the combination of Chu et al. and McElheny et al. discloses the method of claim 16, but fails to disclose wherein the gate oxide has a thickness of 4.0 nanometers or less.
Zhou discloses a semiconductor device (semiconductor device in Fig. 19), wherein the gate oxide (gate oxide 210; see Fig. 19) has a thickness that is greater than or equal to 2 nm and less than or equal to 5 nm (The gate oxide 210 has a thickness that is greater than or equal to 2 nm and less than or equal to 5 nm; see Fig. 19 and [0123)).
Zhou does not directly disclose with sufficient specificity wherein the gate oxide has a thickness of 4.0 nanometers or less. However, Zhou does teach a gate oxide layer 210 with a thickness that is greater than or equal to 2 nm and less than or equal to 5 nm (see Fig. 19 and [0123]). MEPEP 2144.05 | states “In the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists.” In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
The teachings of the combination of Chu et al. and McElheny et al. are incorporated with the teachings of Zhou by substituting the gate oxide layer in the combination of Chu et al. and McElheny et al. (oxide layer 210; see McElheny et al. Fig. 3B) with the gate oxide from the device of Zhou (gate oxide 210; see Zhou Fig. 19).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of the combination of Chu et al. and McElheny et al. with the teachings of Zhou, wherein the combination discloses wherein the gate oxide has a thickness that is greater than or equal to 2 nm and less than or equal to 5 nm, because a reduced oxide thickness allows for effective scaling of low voltage operation devices; and the combination is a simple substitution of one known element for another to obtain predictable results — substitution of the gate oxide layer of the combination of Chu et al. and McElheny et al., with the gate oxide layer of the device of Zhou.
Claims 6 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. in view of McElheny et al., further in view of Liu et al. (Pub. No.: US 20210367064 A1).
Regarding claim 6, the combination of Chu et al. and McElheny et al. discloses the method of claim 1, but fails to disclose further comprising forming a self-aligned silicide over the gate.
Liu et al. discloses a method of manufacturing a semiconductor device (LDMOS device shown in Fig. 1), further comprising forming a self-aligned silicide over the gate (salicides 21 are separately formed on the tops of the drain region 15, the source region 16, and the gate structure; see Fig. 1 and [0024)).
The teachings of the combination of Chu et al. and McElheny et al. are incorporated with the teachings of Liu et al. by combining the salicide of the device of Liu et al. (salicide 21; see Liu Fig. 1) with the combined device of Chu et al. and McElheny et al. so that the salicide layer is formed over the gate.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of the combination of Chu et al. and McElheny et al. with the teachings of Liu et al., wherein the combination discloses further comprising forming a self-aligned silicide over the gate, because the salicide layer reduces the resistivity of the gate electrode, thereby improving switching speed; and the combination is combining prior art elements according to known methods to yield predictable results — combining the salicide layer in the device of Liu to yield the results of reduced gate electrode resistivity.
Regarding claim 28, the combination of Chu et al. and McElheny et al. discloses the method of claim 16, but fails to disclose further comprising forming a self-aligned silicide over the gate.
Liu et al. discloses a method of manufacturing a semiconductor device (LDMOS device shown in Fig. 1), further comprising forming a self-aligned silicide over the gate (salicides 21 are separately formed on the tops of the drain region 15, the source region 16, and the gate structure; see Fig. 1 and [0024)).
The teachings of the combination of Chu et al. and McElheny et al. are incorporated with the teachings of Liu et al. by combining the salicide of the device of Liu et al. (salicide 21; see Liu Fig. 1) with the combined device of Chu et al. and McElheny et al. so that the salicide layer is formed over the gate.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of the combination of Chu et al. and McElheny et al. with the teachings of Liu et al., wherein the combination discloses further comprising forming a self-aligned silicide over the gate, because the salicide layer reduces the resistivity of the gate electrode, thereby improving switching speed; and the combination is combining prior art elements according to known methods to yield predictable results — combining the salicide layer in the device of Liu to yield the results of reduced gate electrode resistivity.
Allowable Subject Matter
Claims 8, 9 and 12-15 are allowed.
Claims 26 and 27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: None of the prior art discloses the first and second active area edge extensions comprise respective first and second sawtooth, circle-tooth, or square-tooth areas that are not completely covered by the gate as claimed in claim 8. None of the prior art discloses the first and second active area edge extensions extend beyond the gate toward the source along the channel direction; and the first and second active area edge extensions extend beyond the gate toward the drain along the channel direction as claimed in claims 26 and 27.
Conclusion
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/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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