Prosecution Insights
Last updated: August 18, 2026
Application No. 17/672,750

SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Feb 16, 2022
Priority
Sep 06, 2021 — JP 2021-144980
Examiner
KARIMY, TIMOR
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
KIOXIA Corporation
OA Round
3 (Non-Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
854 granted / 1039 resolved
+14.2% vs TC avg
Moderate +10% lift
Without
With
+9.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
41 currently pending
Career history
1084
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
50.0%
+10.0% vs TC avg
§102
20.1%
-19.9% vs TC avg
§112
22.1%
-17.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1039 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/09/2026 has been entered. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3, 5-6, 8, 10-15 & 20 are rejected under 35 U.S.C. 103 as being unpatentable over KAWAGUCHI et al. (JP2020088101) in view of YAMAWAKI et al. (JP 2021015832 – cited in the IDS submitted on April 09,2026). Regarding claim 1, KAWAGUCHI teaches a semiconductor manufacturing apparatus comprising: a reformed layer former 60 configured to partially reform a first substrate W to form a reformed layer (M1, C1) between a first portion (Wc) and a second portion (We) in the first substrate W (see Fig. 1-4, Fig. 6-8, Fig. 16-18, 19-20, Fig. 26 and associated texts), the second portion We having a shape that surrounds the first portion Wc in a ring manner (e.g. see Fig. 8); a peeling layer former configured to form a peeling layer F between the second portion We and a second substrate S provided on a surface of the first substrate W (see Fig. 1-4, Fig. 6-8, Fig. 16-18, 19-20, Fig. 26 and associated texts); and a remover 61 configured to remove the second portion (We) from a surface of the second substrate S while causing the first portion (Wc) to remain on the surface of the second substrate S, wherein the remover comprises: a heater (e.g. 153/341) configured to heat the first portion (Wc) or the second portion We, to peel the second portion (We) from the second substrate S at the peeling layer F and divide the first portion Wc and the second portion (We) from each other (see Fig. 1-4, Fig. 6-8, Fig. 16-18, 19-22, Fig. 26 and associated texts) and a mover 70 configured to move the second substrate S and the first portion Wc relative to the second portion We, by raising the second substrate S and the first portion (Wc) (see Fig. 24, where the mover 71 has raised the second substrate S and the first portion Wc), to remove the second portion (We) from the surface of the second substrate S while causing the first portion (Wc) to remain on the surface of the second substrate S (Fig. 27 & Fig. 26-Fig. 28, wherein the second portion We is removed from the second substrate S while the first portion Wc remains on the surface of the second substrate S). KAWAGUCHI is silent on the peeling layer being formed in the second portion and not formed in the first portion. However, YAMAWAKI teaches a semiconductor manufacturing apparatus, wherein a peeling layer De is formed in a second portion and not formed in a first portion (see Fig. 11- Fig. 12 and associated texts). This has the advantage of decreasing the bonding strength at the peeling layer to smoothly trim an edge of the wafer. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of KAWAGUCHI with the peeling layer, as taught by YAMAWAKI, so as to efficiently trim a desired area of a wafer. Regarding claim 3, the combination of KAWAGUCHI and YAMAWAKI teaches the apparatus of Claim 1, wherein the reformed layer former partially reforms the first substrate W by a laser (KAWAGUCHI’s Fig. 1-4, Fig. 6-8, Fig. 16-18, 19-22, Fig. 26 and YAMAWAKI’s Fig. 1-24 and associated texts). Regarding claim 5, the combination of KAWAGUCHI and YAMAWAKI teaches the apparatus of Claim 1, wherein the peeling layer former forms the peeling layer by a laser (KAWAGUCHI’s Fig. 1-4, Fig. 6-8, Fig. 16-18, 19-22, Fig. 26 and YAMAWAKI’s Fig. 1-24 and associated texts). Regarding claim 6, the combination of KAWAGUCHI and YAMAWAKI teaches the apparatus of Claim 1, wherein the heater heats the first portion or the second portion such that a temperature of the second portion becomes higher than a temperature of the first portion (KAWAGUCHI’s Fig. 1-4, Fig. 6-8, Fig. 16-22, Fig. 26 and associated texts (e.g. Para [0097) and YAMAWAKI’s Fig. 1-24 and associated texts). Regarding claim 8, the combination of KAWAGUCHI and YAMAWAKI teaches he apparatus of Claim 1, wherein the heater has a ring shape in planar view (KAWAGUCHI’s Fig. 1-4, Fig. 6-8, Fig. 16-18, 19-22, Fig. 26 and YAMAWAKI’s Fig. 1-24 and associated texts). Regarding claim 10, the combination of KAWAGUCHI and YAMAWAKI teaches the apparatus of Claim 1, wherein the mover comprises a first holder 200 configured to hold the second substrate S, a second holder 321/322 configured to hold the first portion Wc, and a third holder 210 configured to hold the second portion (e.g. KAWAGUCHI’s Fig. 19-20). Regarding claim 11, the combination of KAWAGUCHI and YAMAWAKI teaches the apparatus of Claim 10, wherein the first holder comprises a mechanism that cools the second substrate (e.g. KAWAGUCHI’s Para [0097]). Regarding claim 12, the combination of KAWAGUCHI and YAMAWAKI teaches the apparatus of Claim 10, wherein the second holder comprises a mechanism that cools the first portion (KAWAGUCHI’s Para [0097]). Regarding claim 13, the combination of KAWAGUCHI and YAMAWAKI teaches the apparatus of Claim 10, wherein the third holder comprises the heater that heats the second portion (KAWAGUCHI’s Para [0096]). Regarding claim 14, the combination of KAWAGUCHI and YAMAWAKI teaches the apparatus of Claim 10, wherein the third holder has a ring shape that surrounds the second holder (note the ring shaped components in KAWAGUCHI’s Fig. 1-4, Fig. 6-14, Fig. 15-18, 19-22, Fig. 26 and YAMAWAKI’s Fig. 6, 13 & 15 and associated texts). Regarding claim 15, the combination of KAWAGUCHI and YAMAWAKI teaches the apparatus of Claim 1, further comprising a carrying mechanism (e.g. 210-212) that carries the second portion We peeled from the second substrate (e.g. KAWAGUCHI’s Fig. 11-14). Regarding claim 20, the combination of KAWAGUCHI and YAMAWAKI teaches the apparatus of claim 1, wherein the mover removes the second portion from the surface of the second substrate in a state where the second portion has a ring shape (e.g. YAMAWAKI’s Fig. 11-12 and associated text). Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over KAWAGUCHI and YAMAWAKI as applied to claim 1 above, and in further view of TACHIOKIA et al. (US PUB. 2015/0380292). Regarding claim 7, while KAWAGUCHI teaches the apparatus of Claim 1, wherein the heater heats the first portion (Wc) or the second portion (We); however, perhaps in the interest of brevity, the combination of KAWAGUCHI and YAMAWAKI is silent on that a difference between a temperature of the first portion and a temperature of the second portion becomes 200 ºC to 400 ºC. Nonetheless, the Examiner understands that said claim feature would have been obvious in the semiconductor art. For instance, TACHIOKIA teaches a temperature of approximately 200 ºC to separate/divide semiconductor device components (Para [0029]). As such, said claim dimension would have been obvious and within the ordinary skill in the art. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. And it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Response to Arguments Applicant's arguments filed 10/10/2025 have been fully considered but they are not moot in light of new grounds of rejection. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TIMOR KARIMY/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Show 1 earlier event
Jul 10, 2025
Non-Final Rejection mailed — §103
Oct 10, 2025
Response Filed
Jan 30, 2026
Final Rejection mailed — §103
Mar 17, 2026
Applicant Interview (Telephonic)
Mar 17, 2026
Examiner Interview Summary
Apr 09, 2026
Request for Continued Examination
Apr 17, 2026
Response after Non-Final Action
Jul 28, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
92%
With Interview (+9.5%)
2y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1039 resolved cases by this examiner. Grant probability derived from career allowance rate.

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