DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/14/25 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, and 4-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US PGPub 2013/0020720, hereinafter referred to as “Kim”, IDS reference).
Kim discloses the semiconductor device as claimed. See figures 1-28, with emphases in figures 1-3B, and corresponding text, where Kim teaches, in claim 1, semiconductor device comprising:
a first semiconductor die 10a having a top planar surface;
a second semiconductor die 10b having a bottom planar surface and a top planar surface;
a protective layer (30) including a bottom planar surface, a top planar surface, and a plurality of apertures (7) extending from the top planar surface of the protective layer to the bottom planar surface of the protective layer thereof, the protective layer (30) positioned on the top planar surface of the first semiconductor die (10a) between the first semiconductor die and the second semiconductor die (10b); and
an adhesive layer (9) having a top planar surface and a bottom planar surface, the adhesive layer positioned on the top planar surface of the protective layer (30) between the protective layer (30) and the second semiconductor die (10b), a portion of the adhesive layer (9) extending through the plurality of apertures (7) in the protective layer (30) and directly contacting the first semiconductor die (10a), wherein a periphery of the top planar surface of the first semiconductor die (10a) is covered by a periphery of the bottom planar surface of the protective layer (30) (figure 2; [0069-0077]).
Kim teaches, in claim 4, wherein the plurality of apertures are positioned proximate the periphery of the protective layer (figure 2; [0069-0077]).
Kim teaches, in claim 5, wherein a periphery of the protective layer is substantially planar with the periphery of the first semiconductor die (figure 2; [0069-0077]).
Kim teaches, in claim 6, wherein the protective layer is configured to reduce the occurrence of peeling of the adhesive layer from the protective layer (figure 2; [0069-0077]).
Kim teaches, in claim 7, wherein a periphery of the bottom planar surface of the adhesive layer contacts the periphery of the top planar surface of the protective layer (figure 2; [0069-0077]).
Kim teaches, in claim 8, wherein the protective layer includes one of a polymer and a polyimide (figure 2; [0069-0077]).
Allowable Subject Matter
Claims 17-20 are allowed over the prior art of record.
The following is an examiner’s statement of reasons for allowance: the closest prior art of record based on applicant’s persuasive arguments does not suggest or render obvious to the claimed invention.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 January 24, 2026