DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/2/2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/2/26 was filed after the mailing date of the final action on 4/2/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Status
Previous action: claims 1 through 10 and 13 through 17 rejected, claims 18 through 20 withdrawn.
Present action: claims 1 through 10 and 13 through 17 rejected, claims 18 through 20 withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13 through 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation "the conductive pad" in line 33. There is insufficient antecedent basis for this limitation in the claim. The antecedent is assumed to be “a copper pad”.
Claims 14 through 17 depend from and incorporate claim 13.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1, 2, 3, 4, 5, 6, 8, 9, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2022/0139851) in view of Kuang (US 2015/0108644) in view of Shibata (US 2024/0170447) in view of Uzoh (US 2023/0343734).
Regarding claim 1.
Chang teaches:
A semiconductor die, comprising: a semiconductor substrate (fig 2:210; [para 0028])including integrated circuitry (fig 2:220; [para 0028]);
a dielectric structure (fig 2:400; [para 0032])over the semiconductor substrate (fig 2:210; [para 0028]), the dielectric structure (fig 2:400; [para 0032]) including an bonding layer (fig 2:410; [para 0032]) located at a first side of the dielectric structure (fig 2:410; [para 0032]) facing away from the semiconductor substrate (fig 2:210; [para 0028]), the dielectric structure (fig 2:400; [para 0032]) including a recess (fig 2; [para 0032]) extending from a top surface of the bonding layer (fig 2:400; [para 0032]);
;
a conductive pad (fig 2,3a:420; [para 0032]) included in the recess of the dielectric structure (fig 2:400; [para 0032]) , the conductive pad (fig 2,3a:420; [para 0032]) having (1) a lateral bottom surface, (2) a pad top surface, and (3) opposing planar sidewalls that extend from the pad top surface to the lateral bottom surface and through the bonding layer (fig 2:410; [para 0032]) and the dielectric structure (fig 2:400; [para 0032]), wherein: the conductive pad (fig 2,3a:420; [para 0032]) is operatively coupled (fig 2:241; [para 0028]) to the integrated circuitry (fig 2:220; [para 0028]), the conductive pad (fig 2,3:420; [para 0032]) has at least two lateral dimensions (fig 3a:a,b; [para 0036]), wherein one (fig 3a:b; [para 0036]) of the two lateral dimensions (fig 3a:a,b; [para 0036]) extends between the opposing planar sidewalls and is longer than remaining one or more lateral dimensions (fig 3a:a; [para 0036]), a thickness of the bonding layer (fig 2:410; [para 0032]) is predetermined based, at least in part, on the longer one (fig 3a:b; [para 0036]) of the at least two lateral dimensions (fig 3a:a,b; [para 0036]) of the conductive pad (fig 2,3a:420; [para 0032]), the at least two lateral dimensions (fig 3a:a,b; [para 0036]) being generally perpendicular to the thickness (fig 2,3a; [para 0007,0034]), ; and a through-substrate via (TSV) (fig 2:230,242; [para 0028]) in contact with the lateral bottom surface of the conductive pad (fig 2,3:420; [para 0032]) and operatively coupling the conductive pad (fig 2,3:420; [para 0032]) to the semiconductor substrate (fig 2:210; [para 0028]).
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Chang does not teach an elastic bonding layer material or a pad barrier layer.
Kuang teaches:
A semiconductor die (fig 5:100; [para 0010]), comprising: a semiconductor substrate (fig 5:102; [para 0010])including integrated circuitry (fig 5:104; [para 0010]);
a dielectric structure (fig 5:116,118; [para 0022]) over the semiconductor substrate (fig 5:102; [para 0010]), the dielectric structure (fig 5:116,118; [para 0022]) including an elastic bonding layer (siloxane an elastic polymer, fig 5:120; [para 0022]) located at a first side of the dielectric structure (fig 5:116,118; [para 0022]) facing away from the semiconductor substrate (fig 5:102; [para 0010]), the dielectric structure (fig 5:116,118; [para 0022]) including a recess (fig 3:122; [para 0018]) extending from a top surface of the elastic bonding layer (fig 5:120; [para 0022]) and below a bottom surface of the elastic bonding layer (fig 5:120; [para 0022]);
a barrier layer (fig 4:126; [para 0019]) in the recess (fig 3:122; [para 0018]), wherein the barrier layer (fig 4:126; [para 0019]) includes a barrier top edge that is coplanar (fig 5) with the top surface of the elastic bonding layer (fig 5:120; [para 0022]);
a conductive pad (fig 5:128; [para 0021]) included in the recess (fig 3:122; [para 0018]) of the dielectric structure (fig 5:116,118; [para 0022]) and directly contacting the barrier layer (fig 4:126; [para 0019]), the conductive pad (fig 5:128; [para 0021])having (1) a lateral bottom surface, (2) a pad top surface (fig 5:128; [para 0021])above the first side bottom surface of elastic bonding layer (fig 5:120; [para 0022]), and (3) opposing planar sidewalls that extend from the pad top surface to the lateral bottom surface and through the elastic bonding layer (fig 5:120; [para 0022]) and the dielectric structure (fig 5:116,118; [para 0022]),a thickness of the elastic bonding layer (fig 5:120; [para 0022]) is predetermined based, at least in part, on the lateral dimensions of the conductive pad (fig 5:128; [para 0021]), the lateral dimensions being generally perpendicular to the thickness, wherein the thickness of the elastic bonding layer (fig 5:120; [para 0022]) is less than one lateral dimensions (fig 5), and wherein the elastic bonding layer (fig 5:120; [para 0022]) includes a modulus of elasticity, and wherein the elastic bonding layer (fig 5:120; [para 0022]) includes at least one of polysiloxane-based material ([para 0022]) or a sol-gel material;
and a via (fig 5:112; [para 0020]) in contact with the lateral bottom surface of the conductive pad (fig 5:128; [para 0020]) and operatively coupling the conductive pad (fig 5:128; [para 0020]) to the semiconductor substrate (fig 5:102; [para 0010]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a barrier layer for the conductive contact pad in order to prevent metal contamination of the surrounding dielectric, further providing an elastic bonding layer in the dielectric structure enable bonding stresses or particle contamination to be compensated for. Further, Note, there is inherently a relationship between the thickness of the elastic layer and the dimensions of the bonding layer. The applicant is claiming the device, not the process of making the device, therefore the method of determining the thickness of the layers does not limit the claim. Additionally, the applicant has not suggested what the relationship is, only that a relationship exists.
Chang does not teach the elastic modulus of the elastic bonding layer.
Shibata teaches:
the elastic bonding layer (fig 4:14; [para 0052]) has a modulus of elasticity of 2GPa or less ([para 0052])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a modulus of elasticity of less than 2GPa in order that the layer has the appropriate levels of compliance and resilience to accommodate the bonding process and relieving stressing that can occur at the interface.
Chang does not teach that the top surface of the pad is recessed below the top surface of the adjacent barrier layer.
Uzoh teaches:
a barrier layer (fig 3a:26; [para 0039]) in the recess (fig 3a:28; [para 0040]), wherein the barrier layer (fig 3a:26; [para 0039]) includes a barrier top edge that is coplanar with the top surface of the bonding layer (fig 3a:22; [para 0040]); a conductive pad (fig 3a:24; [para 0039]) included in the recess (fig 3a:28; [para 0040]) of the dielectric structure and directly contacting the barrier layer (fig 3a:26; [para 0039]), the conductive pad (fig 3a:24; [para 0039]) having (1) a lateral bottom surface, (2) a pad top surface (fig 3a:32a,30a; [para 0042]) that is located below (recessed 30nm; [para 0042]) the top surface (fig 3a:22a; [para 0041]) of the bonding layer (fig 3a:22; [para 0040]), below the barrier top edge, and above the first side bottom surface of bonding layer (fig 3a:22; [para 0040]), and (3) opposing planar sidewalls that extend from the pad top surface to the lateral bottom surface
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention in order to compensate for the expansion of the pad during the fusion process (paragraph 43])
Regarding claim 2.
Chang in view of Kuang in view of Shibata in view of Uzoh teaches the semiconductor die of claim 1, further:
Kuang teaches:
the elastic bonding layer (fig 5:120; [para 0022]) has a first surface facing away from the semiconductor substrate (fig 5:102; [para 0010]);
and the conductive pad (fig 5:128; [para 0030]) has a second surface facing away from the semiconductor substrate (fig 5:102; [para 0010]),
Uzoh teaches:
the second surface (fig 3a:32a,30a; [para 0042]) being recessed by a depth (recessed 30nm; [para 0042]) with respect to the first surface (fig 3a:22a; [para 0042]).
Regarding claim 3.
Chang in view of Kuang in view of Shibata in view of Uzoh teaches the semiconductor die of claim 2, further:
Kuang teaches:
the width of the conductive pad (fig 5:128; [para 0030]) such that the thickness of the elastic bonding layer (fig 5:120; [para 0022]) is predetermined (1 micron; [para 0022]),
Uzoh teaches:
wherein the depth (recessed 30nm; [para 0042]) is proportional to the width of the conductive pad (fig 3a:24; [para 0042])such that the thickness of the bonding layer is predetermined based, at least in part, on the depth.
Note, there is inherently a relationship between the thickness of the elastic layer and the dimensions of the pad. The applicant is claiming the device, not the process of making the device, therefore the method of determining the thickness of the layers does not limit the claim. Additionally, the applicant has not suggested what the relationship is, only that a relationship exists.
Regarding claim 4.
Chang in view of Kuang in view of Shibata in view of Uzoh teaches the semiconductor die of claim 2, further:
Kuang teaches:
the thickness (1 micron; [para 0022]) of the elastic bonding layer (fig 5:120; [para 0022])
Uzoh teaches:
the depth (recessed 30nm; [para 0042])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recess that pad less than one tenth the thickness in order to compensate for the expansion of the pad during the fusion process (paragraph 43)
Regarding claim 5.
Chang in view of Kuang in view of Shibata in view of Uzoh teaches the semiconductor die of claim 1, further:
Shibata teaches:
the elastic bonding layer (fig 4,5a:24; [para 0034]) includes a polymer material ([para 0034]) configured to accommodate stress ([para 0008]) generated by an irregularity at the first side (fig 5a:24a; [para 0060]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that an irregularity can cause stress due to differences in polishing rates (paragraph 60)
Regarding claim 6.
Chang in view of Kuang in view of Shibata in view of Uzoh teaches the semiconductor die of claim 5, further:
Shibata teaches:
the polymer material is flexible to deform in response to the stress generated by the irregularity at the first side ([para 0034]).
Regarding claim 8.
Chang in view of Kuang in view of Shibata in view of Uzoh teaches the semiconductor die of claim 5, further:
Shibata teaches:
the irregularity corresponds to the conductive pad (fig 5a:26; [para 0060]),
wherein: the elastic bonding layer (fig 5a:24; [para 0060]) has a first surface (fig 5a:24a; [para 0060]) facing away from the semiconductor substrate (fig 4:21; [para 0031]);
the conductive pad (fig 5a:26; [para 0060]) has a second surface (fig 5a:26a; [para 0060]) facing away from the semiconductor substrate (fig 4:21; [para 0031]),
the second surface (fig 5a:26a; [para 0060]) being protruded above the first surface (fig 5a:24a; [para 0060]).
Regarding claim 9.
Chang in view of Kuang in view of Shibata in view of Uzoh teaches the semiconductor die of claim 5, further:
Shibata teaches:
the irregularity originates from the conductive pad (fig 5a:26; [para 0060]), wherein: the elastic bonding layer (fig 5a:24; [para 0060])has a first surface facing away from the semiconductor substrate (fig 4:21; [para 0031]); the conductive pad (fig 5a:26; [para 0060]) has a second surface facing away from the semiconductor substrate (fig 4:21; [para 0031]),
Uzoh teaches:
the second surface (fig 3a:32a,30a; [para 0042]) being recessed by a depth (recessed 30nm; [para 0042]) with respect to the first surface (fig 3a:22a; [para 0042]), wherein the depth (recessed 30nm; [para 0042]) is less than an increase in a thickness of the conductive pad (fig 3a,7a:24; [para 0044,0062]) in response to receiving thermal energy ([para 0044,0062]), the thickness being generally perpendicular to the width.
Regarding claim 10.
Chang in view of Kuang in view of Shibata in view of Uzoh teaches the semiconductor die of claim 1, further:
Chang teaches:
the conductive pad (fig 2:420; [para 0038]) includes copper ([para 0038]).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2022/0139851) in view of Kuang (US 2015/0108644) in view of Shibata (US 2024/0170447) in view Uzoh (US 2023/0343734) as applied to claim 6 and further in view of Suh (US 2021/0125955).
Regarding claim 7.
Chang in view of Kuang in view of Shibata in view of Uzoh teaches the semiconductor die of claim 6, further:
Chang in view of Kuang in view of Shibata in view of Uzoh does not teach a particle generating stress
Suh teaches:
the irregularity corresponds to a particle (fig 15:PC; [para 0099]) present at the first side.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a particle be present at the bonding interface because the manufacturing processes have the chance of generating particulate matter that may become entrapped during bonding.
Claim(s) 13 through 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2022/0139851) in view of Kuang (US 2015/0108644) in view of Shibata (US 2024/0170447) in view of Uzoh (US 2023/0343734) in view of Shih (US 2022/0238487).
Regarding claim 13.
Chang teaches:
A semiconductor die assembly, comprising: ;
and a semiconductor die (fig 2:200; [para 0028]), the semiconductor die (fig 2:200; [para 0028]) including: a semiconductor substrate (fig 2:210; [para 0028]) having integrated circuitry (fig 2:220; [para 0028]);
a dielectric structure (fig 2:400; [para 0032]) over the semiconductor substrate (fig 2:210; [para 0028]), the dielectric structure (fig 2:400; [para 0032])including an bonding layer (fig 2:410; [para 0032]) located at a first side of the dielectric structure (fig 2:400; [para 0032]) facing away from the semiconductor substrate (fig 2:210; [para 0028]), the dielectric structure (fig 2:400; [para 0032]) ;
;
a copper pad (fig 2:420; [para 0038]) included in the recess of the dielectric structure (fig 2:400; [para 0032]) , the copper pad (fig 2:420; [para 0038]) having (1) a lateral bottom surface, (2) a pad top surface (3) opposing planar sidewalls that extend from the pad top surface to the lateral bottom surface and through the bonding layer (fig 2:410; [para 0032]) and the dielectric structure (fig 2:400; [para 0032]), wherein: the copper pad (fig 2:420; [para 0038]) is operatively coupled to the integrated circuitry (fig 2:220; [para 0028]) and has at least two lateral dimensions (fig 3a:a,b; [para 0036]), wherein one (fig 3a:b; [para 0036]) of the two lateral dimensions (fig 3a:a,b; [para 0036]) extends between the opposing planar sidewalls and is longer than remaining one or more lateral dimensions (fig 3a:a,b; [para 0036]), a thickness of the bonding layer (fig 2:410; [para 0032]) is predetermined based, at least in part, on the longer one of the at least two lateral dimensions (fig 3a:a,b; [para 0036]) of the copper pad (fig 2:420; [para 0038]), the at least two lateral dimensions (fig 3a:a,b; [para 0036]) being generally perpendicular to the thickness (fig 2,3a), ,
and a through-substrate via (TSV) (fig 2:230,242; [para 0028]) in contact with the lateral bottom surface of the copper pad (fig 2:420; [para 0038]) and operatively coupling the conductive pad (fig 2:420; [para 0038]) to the semiconductor substrate (fig 2:210; [para 0028]).
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Chang does not teach an elastic bonding layer material or a pad barrier layer.
Kuang teaches:
A semiconductor die assembly (fig 11:300; [para 0029]), comprising:
and a semiconductor die (fig 11:100; [para 0027])
a dielectric structure (fig 5:116,118; [para 0022]) over the semiconductor substrate (fig 5:102; [para 0010]), the dielectric structure (fig 5:116,118; [para 0022])including an elastic bonding layer (siloxane) (fig 5:120; [para 0022]) located at a first side of the dielectric structure (fig 5:116,118; [para 0022])facing away from the semiconductor substrate (fig 5:102; [para 0010]), the dielectric structure including a recess (fig 3:122; [para 0018])extending from a top surface of the elastic bonding layer (fig 5:120; [para 0022]) and below a bottom surface of the elastic bonding layer (fig 5:120; [para 0022]);
a barrier layer (fig 5:126; [para 0019]) in the recess (fig 3:122; [para 0018]), wherein the barrier layer (fig 5:126; [para 0019]) includes a barrier top edge that is coplanar with the top surface of the elastic bonding layer (fig 5:120; [para 0022]);
a copper pad (fig 5:128; [para 0019]) included in the recess (fig 3:122; [para 0018]) of the dielectric structure (fig 5:116,118; [para 0022]) and directly contacting the barrier layer (fig 5:126; [para 0019]), the copper pad (fig 5:128; [para 0019]) having (1) a lateral bottom surface, (2) a pad top surface above the bottom surface of the elastic bonding layer (fig 5:120; [para 0022]), and (3) opposing planar sidewalls that extend from the pad top surface to the lateral bottom surface and through the elastic bonding layer (fig 5:120; [para 0022]) and the dielectric structure (fig 5:116,118; [para 0022]), wherein: the copper pad (fig 5:128; [para 0019]) and has at least lateral dimensions, wherein one lateral dimensions extends between the opposing planar sidewalls a thickness of the elastic bonding layer (fig 5:120; [para 0022]) is predetermined based at least in part, on the one lateral dimensions of the copper pad (fig 5:128; [para 0019]) [there is inherently a ratio between the lateral dimension of the pad and the vertical dimension of the pad, due to the fact that the dimensions are rational numbers, the thickness of the pad being a rational number and the width of the pad being a rational number will inherently mean that the thickness is based on (a function of) the width], the lateral dimensions being generally perpendicular to the thickness, wherein the thickness of the elastic bonding layer (fig 5:120; [para 0022]) is less than the one lateral dimensions, and wherein the elastic bonding layer (fig 5:120; [para 0022]) includes a modulus of elasticity, wherein the elastic bonding layer (fig 5:120; [para 0022]) includes at least one of polysiloxane-based material ([para 0021]) or a sol-gel material;
and a via (fig 5:112; [para 0020]) in contact with the lateral bottom surface of the copper pad (fig 5:128; [para 0019]) and operatively coupling the conductive pad (fig 5:128; [para 0019]) to the semiconductor substrate (fig 5:102; [para 0010]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a barrier layer for the conductive contact pad in order to prevent metal contamination of the surrounding dielectric, further providing an elastic bonding layer in the dielectric structure enable bonding stresses or particle contamination to be compensated for. Further, Note, there is inherently a relationship between the thickness of the elastic layer and the dimensions of the bonding layer. The applicant is claiming the device, not the process of making the device, therefore the method of determining the thickness of the layers does not limit the claim. Additionally, the applicant has not suggested what the relationship is, only that a relationship exists.
Chang does not teach the elastic modulus of the elastic bonding layer.
Shibata teaches:
the elastic bonding layer (fig 4:14; [para 0052]) has a modulus of elasticity of 2GPa or less ([para 0052])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a modulus of elasticity of less than 2GPa in order that the layer has the appropriate levels of compliance and resilience to accommodate the bonding process and relieving stress that can occur at the interface.
Chang does not teach that the top surface of the pad is recessed below the top surface of the adjacent barrier layer.
Uzoh teaches:
a barrier layer (fig 3a:26; [para 0039]) in the recess (fig 3a:28; [para 0040]), wherein the barrier layer (fig 3a:26; [para 0039]) includes a barrier top edge that is coplanar with the top surface of the bonding layer (fig 3a:22; [para 0040]);
a copper pad (fig 3a:24; [para 0039,0043]) included in the recess (fig 3a:28; [para 0040]) of the dielectric structure and directly contacting the barrier layer (fig 3a:26; [para 0039]), the copper pad (fig 3a:24; [para 0039,0043]) having (1) a lateral bottom surface, (2) a pad top surface (fig 3a:32a,30a; [para 0042]) located below (recessed 30nm; [para 0042]) the top surface (fig 3a:22a; [para 0041]) of the bonding layer (fig 3a:22; [para 0040]), below the barrier top edge, and above the bottom surface of the bonding layer (fig 3a:22; [para 0040]), and (3) opposing planar sidewalls that extend from the pad top surface (fig 3a:32a,30a; [para 0042]) to the lateral bottom surface
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention in order to compensate for the expansion of the pad during the fusion process (paragraph 43])
Chang does not teach a substrate die.
Shih teaches:
substrate die (fig 14:100; [para 0100])
bonding a semiconductor die (fig 14:200; [para 0100]) to the substrate die (fig 14:100; [para 0100])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach the semiconductor die to a substrate die in order form a stack of die that combines logic and memory functions into a package in order to scale down the size of the semiconductor device (Shih paragraph 2)
Regarding claim 14.
Chang in view of Kuang in view of Shibata in view of Uzoh in view of Shih teaches the semiconductor die of claim 13, further:
Shibata teaches:
the elastic bonding layer (fig 4,5a:24; [para 0034]) includes a polymer material ([para 0034]) configured to accommodate stress ([para 0008]) generated by an irregularity at the first side (fig 5a:24a; [para 0060]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that an irregularity can cause stress due to differences in polishing rates (paragraph 60)
Regarding claim 15.
Chang in view of Kuang in view of Shibata in view of Uzoh in view of Shih teaches the semiconductor die of claim 13, further:
Chang teaches:
the semiconductor die (fig 2:200; [para 0028])is a first semiconductor die (fig 2:200; [para 0028]) and the copper pad (fig 2,3a:420; [para 0038]) is a first copper pad (fig 2,3a:420; [para 0038]), and the semiconductor die assembly further comprises: a second semiconductor die (fig 2:100; [para 0024]) directly bonded to the first semiconductor die (fig 2:200; [para 0028]) at the first side, wherein the second semiconductor die (fig 2:100; [para 0024]) includes a second copper pad (fig 2,3a:320; [para 0038]) directly bonded to the first copper pad (fig 2,3a:420; [para 0038]).
Regarding claim 16.
Chang in view of Kuang in view of Shibata in view of Uzoh in view of Shih teaches the semiconductor die of claim 13, further:
Kuang teaches:
the semiconductor die (fig 11:100; [para 0027]) is a first semiconductor die (fig 11:100; [para 0027])
and the elastic bonding layer (fig 11:120; [para 0022]) is a first elastic bonding layer (fig 11:120; [para 0027]),
and the semiconductor die assembly (fig 11:300; [para 0029]) further comprises:
a second semiconductor die (fig 11:200; [para 0027]) directly bonded to the first semiconductor die (fig 11:100; [para 0027]) at the first side, wherein the second semiconductor die (fig 11:200; [para 0027]) includes a second elastic bonding layer (fig 11:220; [para 0027]) directly bonded to the first elastic bonding layer (fig 11:120; [para 0027]).
Regarding claim 17.
Chang in view of Kuang in view of Shibata in view of Uzoh in view of Shih teaches the semiconductor die of claim 16, further:
Shih teaches:
the substrate die (fig 14:100; [para 0100]) corresponds to an interposer die or a logic die ([para 0100]);
and the first (fig 14:200; [para 0100]) and second (fig 14:300; [para 0100]) semiconductor dies correspond to memory dies ([para 0100]).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference combination applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The newly applied reference Uzoh (US 2023/0343734) in combination with Kuang (US 2015/0108644), Shibata (US 2024/0170447), and Chang (US 2022/0139851) anticipates the claims
Conclusion
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
