DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: claims 1 through 9 and 13 through 17 rejected, claims 18 through 20 withdrawn.
Present action: claims 1 through 9 and 13 through 17 rejected, claims 18 through 20 withdrawn.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
Reference numbers “110a” and “110b” shown in figures 2 and 4 are not included in the specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 through 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “the bottom surface” in line 9. There is insufficient antecedent basis for this limitation in the claim.
Claims 2 through 9 depend from and incorporate claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s)
Claim(s) 1, 5, 6, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuang (US 2015/0108644) in view of Shibata (US 2024/0170447) in view of Chang (US 2022/0139851).
Regarding claim 1.
Kuang teaches:
A semiconductor die, comprising:
a semiconductor substrate (fig 5:102; [para 0010]) including integrated circuitry (fig 5:104; [para 0010]);
a dielectric structure (fig 5:116,118; [para 0022]) over the semiconductor substrate (fig 5:102; [para 0010]),
the dielectric structure (fig 5:116,118; [para 0021]) including an elastic bonding layer (siloxane an elastic polymer) (fig 5:120; [para 0022]) located at a first side of the dielectric structure (fig 5:116,118 ; [para 0021]) facing away from the semiconductor substrate (fig 5:102; [para 0010]);
a conductive pad (fig 5:130; [para 0021])included in the dielectric structure (fig 5:116,118; [para 0021]),
the conductive pad (fig 5:130; [para 0021]) having (1) a lateral bottom surface,
(2) a top portion located between a top surface of the elastic bonding layer (fig 5:120; [para 0022]) and above the first side of the dielectric structure (fig 5:116,118 ; [para 0021]),
and (3) opposing planar sidewalls that extend from the top portion to the bottom surface (fig 5) and through the elastic bonding layer (fig 5:120; [para 0022]) and the dielectric structure (fig 5:116,118 ; [para 0021]),
wherein: the conductive pad (fig 5:130; [para 0021]) is operatively coupled to the integrated circuitry (fig 5:104; [para 0010]),
the conductive pad has at least two lateral dimensions, wherein one of the two lateral dimensions extends between the opposing planar sidewalls
a thickness of the elastic bonding layer (fig 5:120; [para 0022]) is predetermined based, at least in part, on(fig 5:130; [para 0021]),
the at least two lateral dimensions being generally perpendicular to the thickness,
wherein the thickness of the elastic bonding layer (fig 5:120; [para 0022]) is less than one of the at least two lateral dimensions (fig 5),
and wherein the elastic bonding layer (fig 5:120; [para 0022]) includes at least one of polysiloxane-based material or a sol-gel material;
and a via (fig 5:112; [para 0020]) in contact with the lateral bottom surface of the conductive pad (fig 5:130; [para 0020]) and operatively coupling the conductive pad (fig 5:130; [para 0020]) to the semiconductor substrate (fig 5:102; [para 0010]).
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Note, the pads inherently have two dimensions, further there is inherently a relationship between the thickness of the elastic layer and the dimensions of the bonding layer. The applicant is claiming the device, not the process of making the device, therefore the method of determining the thickness of the layers does not limit the claim. Additionally, the applicant has not suggested what the relationship is, only that a relationship exists.
Kuang does not teach the elastic modulus of the elastic bonding layer.
Shibata teaches:
the elastic bonding layer (fig 4:14; [para 0052]) has a modulus of elasticity of 2GPa or less ([para 0052])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a modulus of elasticity of less than 2GPa in order that the layer has the appropriate levels of compliance and resilience to accommodate the bonding process and relieving stressing that can occur at the interface.
Kuang does not teach the pad has one lateral dimension that is longer than another lateral dimension
Chang teaches
the conductive pad (fig 1:420; [para 0032]) has at least two lateral dimensions (fig 3a:a,b; [para 0036]), wherein one (fig 3a:b; [para 0036]) of the two lateral dimensions extends between the opposing planar sidewalls and is longer than remaining one (fig 3a:a; [para 0036]) or more lateral dimensions,
and a through-substrate via (TSV) (fig 1:230; [para 0028]) in contact with the lateral bottom surface of the conductive pad (fig 1:420; [para 0032]) and operatively coupling the conductive pad (fig 1:420; [para 0032]) to the semiconductor substrate (fig 1:210; [para 0028]).
It would have been obvious to one of ordinary skill in the before the effective filing date of the claimed invention for the bonding pad to comprise a longer dimension in order to accommodate for overlay errors (paragraph 34) and further the inclusion of through silicon vias facilitates the stacking of additional die enabling greater package functionality.
Regarding claim 5.
Kuang in view of Shibata in view of Chang teaches the semiconductor die of claim 1, further:
Shibata teaches:
the elastic bonding layer (fig 4,5a:24; [para 0034]) includes a polymer material ([para 0034]) configured to accommodate stress ([para 0008]) generated by an irregularity at the first side (fig 5a:24a; [para 0060]).
Regarding claim 6.
Kuang in view of Shibata in view of Chang teaches the semiconductor die of claim 5, further:
Shibata teaches:
the polymer material is flexible to deform in response to the stress generated by the irregularity at the first side ([para 0034]).
Regarding claim 8.
Kuang in view of Shibata in view of Chang teaches the semiconductor die of claim 5, further:
Shibata teaches:
the irregularity corresponds to the conductive pad (fig 5a:26; [para 0060]),
wherein: the elastic bonding layer (fig 5a:24; [para 0060]) has a first surface (fig 5a:24a; [para 0060]) facing away from the semiconductor substrate (fig 4:21; [para 0031]);
the conductive pad (fig 5a:26; [para 0060]) has a second surface (fig 5a:26a; [para 0060]) facing away from the semiconductor substrate (fig 4:21; [para 0031]),
the second surface (fig 5a:26a; [para 0060]) being protruded above the first surface (fig 5a:24a; [para 0060]).
Regarding claim 10.
Kuang in view of Shibata in view of Chang teaches the semiconductor die of claim 5, further:
Kuang teaches:
the conductive pad (fig 5:130; [para 0020]) includes copper (fig 5:126; [para 0019]).
Claim(s) 2, 3, and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuang (US 2015/0108644) in view of Shibata (US 2024/0170447) in view of Chang (US 2022/0139851) as applied to claim 1 and further in view of Gao (US 2020/0075534)
Regarding claim 2.
Kuang in view of Shibata in view of Chang teaches the semiconductor die of claim 1 above.
Kuang teaches:
the elastic bonding layer (fig 5:120; [para 0022]) has a first surface facing away from the semiconductor substrate (fig 5:102; [para 0010]);
and the conductive pad (fig 5:130; [para 0030]) has a second surface facing away from the semiconductor substrate (fig 5:102; [para 0010]),
Kuang in view of Shibata in view of Chang does not teach the second surface is recessed.
Gao teaches:
the bonding layer (fig 1:108; [para 0041]) has a first surface facing away from the semiconductor substrate (fig 1);
and the conductive pad (fig 1:100; [para 0027]) has a second surface facing away from the semiconductor substrate (fig 1),
the second surface being recessed (fig 1,2:104; [para 0042]) by a depth with respect to the first surface ([para 0046]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recess before the effective filing date of the claimed invention to recess the surface of the pad in order that the metal pads do not impede bonding of the dielectric surfaces upon contact of the dielectric surfaces with each other (paragraph 4).
Regarding claim 3.
Kuang in view of Shibata in view of Chang in view of Gao teaches the semiconductor die of claim 2 above.
Kuang teaches
that the thickness of the elastic bonding layer is predetermined (fig 5:120; [para 0022]).
Gao teaches:
the depth is proportional to the width of the conductive pad (fig 1:100; [para 0027]) such that the thickness (fig 2:h1; [para 0045]) of the bonding layer (fig 1:108; [para 0041])is predetermined based, at least in part, on the depth ([para 0046]).
Regarding claim 4.
Kuang in view of Shibata in view of Chang in view of Gao teaches the semiconductor die of claim 3 above.
Kuang teaches
that the thickness of the elastic bonding layer (fig 5:120; [para 0022]).
Gao teaches:
the thickness (fig 2:h1,0.8 um; [para 0045]) of the bonding layer (fig 1:108; [para 0041]) is at least ten (10) times the depth (fig 1:6nm; [para 0045]).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuang (US 2015/0108644) in view of Shibata (US 2024/0170447) in view of Chang (US 2022/0139851) as applied to claim 6 and further in view of Suh (US 2021/0125955).
Regarding claim 7.
Kuang in view of Shibata in view of Chang teaches the semiconductor die of claim 6, further:
Kuang in view of Shibata in view of Chang does not teach a particle generating stress
Suh teaches:
the irregularity corresponds to a particle (fig 15:PC; [para 0099]) present at the first side.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a particle be present at the bonding interface because the manufacturing processes have the chance of generating particulate matter that may become entrapped during bonding.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuang (US 2015/0108644) in view of Shibata (US 2024/0170447) in view of Chang (US 2022/0139851) as applied to claim 5 and further in view of Gao (US 2020/0075534).
Regarding claim 9.
Kuang in view of Shibata in view of Cheng teaches a semiconductor die of claim 5.
Kuang in view of Shibata in view of Cheng does not teach the response to receive thermal energy.
Gao teaches:
the irregularity originates from the conductive pad (fig 3:206; [para 0030]), wherein:
the elastic bonding layer has a first surface facing away from the semiconductor substrate (fig 1,3:212; [para 0034]);
the conductive pad (fig 3:206; [para 0030]) has a second surface (fig 3:210; [para 0031]) facing away from the semiconductor substrate (fig 1,3:212; [para 0034]),
the second surface (fig 3:210; [para 0031]) being recessed by a depth with respect to the first surface,
wherein the depth is less than an increase in a thickness of the conductive pad (fig 3:206; [para 0030]) in response to receiving thermal energy,
the thickness being generally perpendicular to the width ([para 0032,0033]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the recess depth to be less than the thermal expansion of the pad so that the surface can bulge out and make contact with the opposing pad thereby enabling bonding.
Claim(s) 13, 14, 15, 16, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuang (US 2015/0108644) in view of Shibata (US 2024/0170447) in view of Chang (US 2022/0139851) in view of Shih (US 2022/0238487).
Regarding claim 13.
Kuang teaches:
A semiconductor die assembly (fig 11:300; [para 0029]), comprising: a substrate die (fig 11:200; [para 0027]);
and a semiconductor die (fig 11:100; [para 0027]) attached to the substrate die (fig 11:200; [para 0027]),
the semiconductor die (fig 11:100; [para 0027]) including:
a semiconductor substrate (fig 5:102; [para 0010]) having integrated circuitry (fig 5:104; [para 0010]);
a dielectric structure (fig 5:116,118; [para 0022]) over the semiconductor substrate (fig 5:102; [para 0010]), the dielectric structure (fig 5:116,118; [para 0022])
including an elastic bonding layer (siloxane) (fig 5:120; [para 0022]) located at a first side of the dielectric structure (fig 5:116,118; [para 0022]) facing away from the semiconductor substrate (fig 5:102; [para 0010]); a copper (fig 5:128; [para 0019]) pad (fig 5:130; [para 0021]) included in the dielectric structure (fig 5:116,118; [para 0022]),
the copper pad (fig 5:130; [para 0021]) having (1) a lateral bottom surface, (2) a top portion located between a top surface of the elastic bonding layer (fig 5:120; [para 0022]) and above the first side of the dielectric structure (fig 5:116,118; [para 0022]),
and (3) opposing planar sidewalls that extend from the top portion to the bottom surface and through the elastic bonding layer (fig 5:120; [para 0022]) and the dielectric structure (fig 5:116,118; [para 0022]), wherein:
the copper pad (fig 5:130; [para 0021]) is operatively coupled to the integrated circuitry (fig 5:104; [para 0010]) and has at least two lateral dimensions,
wherein one of the two lateral dimensions extends between the opposing planar sidewalls (fig 5)
a thickness of the elastic bonding layer (fig 5:120; [para 0022]) is predetermined based, at least in part, on one of the at least two lateral dimensions of the copper pad (fig 5:130; [para 0021]),
the at least two lateral dimensions being generally perpendicular to the thickness (fig 5),
wherein the thickness of the elastic bonding layer (fig 5:120; [para 0022]) is less than the longer one of the at least two lateral dimensions (fig 5),
wherein the elastic bonding layer (fig 5:120; [para 0022]) includes at least one of polysiloxane-based material ([para 0022]) or a sol-gel material;
and a (fig 5:112; [para 0020]) in contact with the lateral bottom surface of the copper pad (fig 5:120; [para 0022]) and operatively coupling the conductive pad (fig 5:130; [para 0021]) to the semiconductor substrate (fig 5:102; [para 0010]).
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Kuang does not teach the elastic modulus of the elastic bonding layer.
Shibata teaches the elastic bonding layer (fig 4:14; [para 0052]) has a modulus of elasticity of 2GPa or less ([para 0052])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a modulus of elasticity of less than 2GPa in order that the layer has the appropriate levels of compliance and resilience to accommodate the bonding process and relieving stressing that can occur at the interface.
Chang teaches:
the copper pad (fig 1:420; [para 0038]) has at least two lateral dimensions (fig 3a:a,b; [para 0036]),
wherein one (fig 3a:b; [para 0036]) of the two lateral dimensions extends between the opposing planar sidewalls and is longer than remaining one (fig 3a:a; [para 0036]) or more lateral dimensions,
and a through-substrate via (TSV) (fig 1:230; [para 0028]) in contact with the lateral bottom surface of the copper pad (fig 1:420; [para 0038]) and operatively coupling the conductive pad (fig 1:420; [para 0032]) to the semiconductor substrate (fig 1:210; [para 0028]).
It would have been obvious to one of ordinary skill in the before the effective filing date of the claimed invention for the bonding pad to comprise a longer dimension in order to accommodate for overlay errors (paragraph 34) and further the inclusion of through silicon vias facilitates the stacking of additional die enabling greater package functionality.
Kuang does not teach a substrate die
Shih teaches:
bonding a semiconductor die (fig 14:200; [para 0100]) to a substrate die (fig 14:100; [para 0100])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach the semiconductor die to a substrate die in order form a stack of die that combines logic and memory functions into a package in order to scale down the size of the semiconductor device (Shih paragraph 2)
Regarding claim 14.
Kuang in view of Shibata in view of Chang in view of Shih teaches the semiconductor die of claim 13, further:
Shibata teaches:
the elastic bonding layer (fig 4,5a:24; [para 0034]) includes a polymer material ([para 0034]) configured to accommodate stress ([para 0008]) generated by an irregularity at the first side (fig 5a:24a; [para 0060]).
Regarding claim 15.
Kuang in view of Shibata in view of Chang in view of Shih teaches the semiconductor die of claim 13, further:
Kuang teaches:
the semiconductor die (fig 11:100; [para 0027]) is a first semiconductor die (fig 11:100; [para 0027])
and the copper pad (fig 11:130; [para 0027]) is a first copper pad (fig 11:130; [para 0027]),
and the semiconductor die assembly (fig 11:300; [para 0029]) further comprises: a second semiconductor die (fig 11:200; [para 0027]) directly bonded to the first semiconductor die (fig 11:100; [para 0029]) at the first side,
wherein the second semiconductor die (fig 11:200; [para 0027]) includes a second copper pad (fig 11:230; [para 0025]) directly bonded to the first copper pad (fig 11:130; [para 0025]).
Regarding claim 16.
Kuang in view of Shibata in view of Chang in view of Shih teaches the semiconductor die of claim 13, further:
Kuang teaches:
the semiconductor die (fig 11:100; [para 0027]) is a first semiconductor die (fig 11:100; [para 0027])
and the elastic bonding layer (fig 11:120; [para 0022]) is a first elastic bonding layer (fig 11:120; [para 0027]),
and the semiconductor die assembly (fig 11:300; [para 0029]) further comprises:
a second semiconductor die (fig 11:200; [para 0027]) directly bonded to the first semiconductor die (fig 11:100; [para 0027]) at the first side, wherein the second semiconductor die (fig 11:200; [para 0027]) includes a second elastic bonding layer (fig 11:220; [para 0027]) directly bonded to the first elastic bonding layer (fig 11:120; [para 0027]).
Regarding claim 17.
Kuang in view of Shibata in view of Chang in view of Shih teaches the semiconductor die of claim 16, further:
Shih teaches:
the substrate die (fig 14:100; [para 0100]) corresponds to an interposer die or a logic die ([para 0100]);
and the first (fig 14:200; [para 0100]) and second (fig 14:300; [para 0100]) semiconductor dies correspond to memory dies.
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference combination as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The applicant argues that the prior art does not show a through silicon via in contact with the conductive pad bottom surface.
However, as demonstrated in the rejection above Chang (US 2022/0139851), used in combination, teaches this limitation
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 31, 2026
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