Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/ Restrictions
Applicant's election of group II: claims 1-20, 21, 23, in the “Response to Election / Restriction Filed - 10/17/2025”, withdrawal of non-elected claim(s) 22 is/are acknowledged. This office action considers claims 1-23, in “Claims - 02/17/2022”, pending for prosecution, of which claim(s) 22 is/are withdrawn.
Priority
Acknowledgment is made of applicant's claim for foreign benefit based on KR10-2021-0023887 filed on 02/23/2021 and KR10-2021-0148400 filed on 11/02/2021.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-3, 6-14, 16-21, 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 20110210385 A1 – hereinafter Lin).
Regarding Claim 1, Lin teaches a neuromorphic synapse device (see the entire document; Fig. 1; specifically, ([0028] - [0034]), and as cited below), comprising:
a channel region (region [hereinafter channel] between S/D 140 and S/D 142 and under gate dielectric 110 as a channel region is understood in the art – Fig. 1 – [0028]) formed on a substrate (150);
a gate insulating film region (110) formed on the channel region (channel);
a floating gate region (120) formed on the gate insulating film region (110);
a charge transfer layer region (132 – [0028]) formed on the floating gate region (120); and
a control gate region (134 – [0028]) formed on the charge transfer layer region (132), wherein the control gate region (134 which is part of 130) is configured to:
generate a potential difference with the floating gate region in response to a fact that a potential that is not less than a reference potential is applied ([0034] teaches “When this control gate, first source/drain 140, the second source/drain 142 and the semiconductor substrate 150 are applied to suitable voltages” – that is, the “suitable” voltage is compared to Vth as it is understood in the art); and
perform a weight update operation by releasing at least one charge stored in the floating gate region or storing the at least one charge into the floating gate region by using the potential difference ([0034] teaches “When this control gate, first source/drain 140, the second source/drain 142 and the semiconductor substrate 150 are applied to suitable voltages respectively for programming or erasing the non-volatile semiconductor device 100, the voltage applied to the coupling gate 130 couples to the floating gate 120, so that electrons can be trapped in the floating gate 120 through a way, such as the channel hot electron injection, or the electrons stored in the floating gate 120 can be pulled out through a way, such as the Fowler-Nordheim tunneling. In this embodiment, the coupling gate 130 is disposed for receiving a voltage and for coupling the voltage to the floating gate 120, so that electric charges of the floating gate 120 are injected or erased through the gate dielectric layer 110”).
Regarding Claim 2, Lin teaches the neuromorphic synapse device of claim 1, wherein the control gate region implements weight depression by releasing the at least one charge stored in the floating gate region and implements weight potentiation by storing the at least one charge into the floating gate region (see operation details in [0034]).
Regarding Claim 3, Lin teaches the neuromorphic synapse device of claim 2, wherein the control gate region implements the weight depression and the weight potentiation in a method in which conductance between a source region and a drain region is changed in response to a fact that the at least one charge passes through an energy barrier by the charge transfer layer region due to the potential difference with the floating gate region ([0034] appears to teach all the claim limitations).
Regarding Claim 6, Lin teaches the neuromorphic synapse device of claim 1, wherein the charge transfer layer region (132) is formed of at least one material of silicon (Si), germanium (Ge), group III-V compound, 2-D material, silicon nitride (Si3N4), nitride, silicon oxynitride (SiON), silicon oxide (SiO2), oxide, aluminum oxide (A1203), IGZO, hafnium oxide (Hf02), a charge transfer material, a semiconductor material, or a solid electrolyte material ([0032] – “The material of the capacitor dielectric layer 132 may be SiOx, SiOxNy, SixNy, other conductive materials, or a combination thereof”).
Regarding Claim 7, Lin teaches the neuromorphic synapse device of claim 1, wherein the floating gate region (120) has one structure among a protruded gate structure including a planar- gate structure, a multiple-gate structure, and a gate-all-around structure or a buried gate structure depending on a structure of the channel region (the floating gate in Fig. 1 appears to be planar gate).
Regarding Claim 8, Lin teaches the neuromorphic synapse device of claim 7, wherein the floating gate region has the protruded gate structure used in one of a finFET, a tri-gate MOSFET, a 1-I-gate MOSFET, a Q-gate MOSFET, a gate-all-around MOSFET, a bulk finFET, or a bulk gate-all-around MOSFET ([0059] teaches that the device is a CMOS which is a MOSFET).
Regarding Claim 9, Lin teaches the neuromorphic synapse device of claim 7, wherein the floating gate region (120) has the buried gate structure used in at least one of a buried gate MOSFET, a recessed gate MOSFET, a sphere-shaped recessed gate MOSFET, a saddle finFET, a groove gate MOSFET, or a V-groove gate MOSFET (floating gate 120 appears to be a buried gate MOSFET – see [0059]).
Regarding Claim 10, Lin teaches the neuromorphic synapse device of claim 1, wherein the floating gate region is formed of at least one material of a metal, a two or three metal alloy, n+ polycrystalline silicon, p+ polycrystalline silicon, or silicide ([0030] – “The floating gate 120 may comprise a conductive material, such as a metal (e.g., tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, or ruthenium), a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, or tantalum silicide), a metal nitride (e.g., titanium nitride or tantalum nitride), doped poly-crystalline silicon, other conductive materials, or a combination thereof”).
Regarding Claim 11, Lin teaches the neuromorphic synapse device of claim 1, wherein the gate insulating film region is formed of at least one of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), hafnium oxide (HfO2), aluminum oxide (A1203), zirconium oxide (ZrO2), hafnium zirconium oxide (HZO), or hafnium oxynitride (HfON) ([0030]).
Regarding Claim 12, Lin teaches the neuromorphic synapse device of claim 1, further comprising: a source region and a drain region formed on left and right sides of the channel region when the neuromorphic synapse device is implemented as a horizontal transistor, and formed at upper and lower ends of the channel region when the neuromorphic synapse device is implemented as a vertical transistor ([0028] and Fig. 1 teach all the limitations of the claim including it being a vertical transistor).
Regarding Claim 13, Lin teaches the neuromorphic synapse device of claim 12, wherein the source region and the drain region are formed of one of n-type silicon, p-type silicon, or metal silicide (n-type and p-type since it is a CMOS device – see [0059]).
Regarding Claim 14, Lin teaches the neuromorphic synapse device of claim 13, wherein, when the source region and the drain region are formed of the n-type silicon or the p-type silicon, the source region and the drain region are formed based on at least one method of diffusion, solid-phase diffusion, epitaxial growth, selective epitaxial growth, ion implantation or subsequent heat treatment ([0037] teaches the invention uses “standard logic processes” which include the claimed limitations).
Regarding Claim 16, Lin teaches the neuromorphic synapse device of claim 12, wherein the channel region, the source region, and the drain region are formed of materials identical to one another (since it is a CMOS device – [0059]).
Regarding Claim 17, Lin teaches the neuromorphic synapse device of claim 16, wherein the channel region, the source region, and the drain region are formed of at least one of silicon, germanium, silicon-germanium, strained silicon, strained germanium, strained silicon-germanium, silicon on insulator (SOI), or group III-V semiconductor materials (see claim 17).
Regarding Claim 18, Lin teaches the neuromorphic synapse device of claim 1, wherein the channel region has either a protruded channel structure or a buried channel structure, which includes a planar structure, a fin structure, a nanosheet structure, or a nanowire structure (Transistor in Fig. 1 appears to be a planar structure).
Regarding Claim 19, Lin teaches the neuromorphic synapse device of claim 18, wherein the channel region has the protruded channel structure used in one of a finFET, a tri-gate MOSFET, a I-gate MOSFET, a Q-gate MOSFET, a gate-all-around MOSFET, a bulk finFET, or a bulk gate-all-around MOSFET ([0059] – it is a CMOS device).
Regarding Claim 20, Lin teaches the neuromorphic synapse device of claim 18, wherein the channel region has the buried channel structure used in at least one of a buried gate MOSFET, a recessed gate MOSFET, a sphere-shaped recessed gate MOSFET, a saddle finFET, a groove gate MOSFET, or a V-groove gate MOSFET (Transistor in Fig. 1 appears to have a buried channel structure in a CMOS device – see [0059]).
Regarding Claim 21, Lin teaches an operating method of a neuromorphic synapse device (see the entire document; Fig. 1; specifically, ([0028] - [0034]), and as cited below), comprising:
a channel region (region [hereinafter channel] between S/D 140 and S/D 142 and under gate dielectric 110 as a channel region is understood in the art – Fig. 1 – [0028]) formed on a substrate (150), a gate insulating film region (110) formed on the channel region (channel), a floating gate region (120) formed on the gate insulating film region (110), a charge transfer layer region (132) formed on the floating gate region (120), and a control gate region (134) formed on the charge transfer layer region (132), the method comprising:
generating a potential difference with the floating gate region in response to a fact that a potential that is not less than a reference potential is applied ([0034] teaches “When this control gate, first source/drain 140, the second source/drain 142 and the semiconductor substrate 150 are applied to suitable voltages” – that is, the “suitable” voltage is compared to Vth as it is understood in the art); and
performing a weight update operation by using the potential difference ([0034]),
wherein the perform of the weight update operation includes one of: implementing weight depression by releasing at least one charge stored in the floating gate region; or implementing weight potentiation by storing the at least one charge into the floating gate region ([0034] teaches “When this control gate, first source/drain 140, the second source/drain 142 and the semiconductor substrate 150 are applied to suitable voltages respectively for programming or erasing the non-volatile semiconductor device 100, the voltage applied to the coupling gate 130 couples to the floating gate 120, so that electrons can be trapped in the floating gate 120 through a way, such as the channel hot electron injection, or the electrons stored in the floating gate 120 can be pulled out through a way, such as the Fowler-Nordheim tunneling. In this embodiment, the coupling gate 130 is disposed for receiving a voltage and for coupling the voltage to the floating gate 120, so that electric charges of the floating gate 120 are injected or erased through the gate dielectric layer 110”).
Regarding Claim 23, Lin teaches a neuromorphic synapse device (see the entire document; Fig. 1; specifically, ([0028] - [0034]), and as cited below), comprising:
a channel region (region [hereinafter channel] between S/D 140 and S/D 142 and under gate dielectric 110 as a channel region is understood in the art – Fig. 1 – [0028]) formed on a substrate (150);
a gate insulating film region (110) formed on the channel region (channel);
a floating gate region (120) formed on the gate insulating film region (110);
a charge transfer layer region (132) formed on the floating gate region (120); and
a control gate region (134) formed on the charge transfer layer region (132),
wherein the control gate region (134) is configured to:
generate a potential difference with the floating gate region in response to a fact that a potential that is not less than a reference potential is applied ([0034] teaches “When this control gate, first source/drain 140, the second source/drain 142 and the semiconductor substrate 150 are applied to suitable voltages” – that is, the “suitable” voltage is compared to Vth as it is understood in the art); and
perform a weight update operation by releasing at least one charge stored in the floating gate region or storing the at least one charge into the floating gate region by using the potential difference ([0034] teaches “When this control gate, first source/drain 140, the second source/drain 142 and the semiconductor substrate 150 are applied to suitable voltages respectively for programming or erasing the non-volatile semiconductor device 100, the voltage applied to the coupling gate 130 couples to the floating gate 120, so that electrons can be trapped in the floating gate 120 through a way, such as the channel hot electron injection, or the electrons stored in the floating gate 120 can be pulled out through a way, such as the Fowler-Nordheim tunneling. In this embodiment, the coupling gate 130 is disposed for receiving a voltage and for coupling the voltage to the floating gate 120, so that electric charges of the floating gate 120 are injected or erased through the gate dielectric layer 110”), and
wherein a charge for the weight update operation is moved between the control gate region and the floating gate region ([0034]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Tarr et al. (US 6172368 B1 - hereinafter Tarr).
Regarding Claim 4, Lin teaches claim 1 from which claim 4 depends. But Lin does not expressly disclose wherein an area of the control gate region or an area of the charge transfer layer region is smaller than an area of the floating gate region.
However, it is well known in the art to fabricate a control gate whose area is smaller than that of floating gate as is also taught by Tarr (Tarr – “making the area of control gate 34 much smaller than that of the floating gate portion 30A” – C7L30).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming wherein an area of the control gate region or an area of the charge transfer layer region is smaller than an area of the floating gate region as taught by Tarr into Lin.
An ordinary artisan would have been motivated to integrate Tarr structure into Lin structure in the manner set forth above for, at least, for the obvious benefit of providing “increased sensitivity” – Tarr – C7L32.
Claims 5, 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Yamashita (US 20180090626 A1 - hereinafter Yamashita).
Regarding claim 5, Lin teaches claim 1 from which claim 5 depends. But Lin does not expressly disclose wherein the control gate region is formed of at least one material of a metal, a two or three metal alloy, n+ polycrystalline silicon, p+ polycrystalline silicon, or silicide.
However, in a related art, Yamashita teaches a control gate if formed of metal films (Yamashita – [0086] - “the control gate electrode CG is formed of the metal films WF and M1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming of a control gate of metal as taught by Yamashita into Lin.
An ordinary artisan would have been motivated to integrate Yamashita structure into Lin structure in the manner set forth above for, at least, for the obvious benefit of providing of superior conductivity of a control gate as is well known.
Regarding claim 15, Lin teaches claim 13 from which claim 55 depends. But Lin does not expressly disclose wherein, when the source region and the drain region are formed of the metal silicide, bonding is improved by using dopant segregation.
However, in a related art, Yamashita teaches the source region and the drain region are formed of metal silicide (Yamashita – [0083] – “the plug PG is electrically coupled to the source region or the drain region via the silicide layer S1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming of the source region and the drain region are formed of metal silicide by Yamashita into Lin.
An ordinary artisan would have been motivated to integrate Yamashita structure into Lin structure in the manner set forth above for, at least, for the obvious benefit of providing of superior conductivity of a control gate and to segregate diffusion dopant as is well known.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898