DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/18/2026 has been entered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a first pillar structure, disposed on the first semiconductor device and laterally in physical contact with the first passivation layer” in claim 10 must be shown or the feature(s) canceled from the claim(s). Currently the Applicant’s figures, specifically the zoom in in Figure 1B seems to show where the passivation is in physical contact with the top rounded portion of Item 14 but does not make physical contact with the pillar structure. Item 105. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 10-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 10, claim 10 recites “a first pillar structure, disposed on the first semiconductor device and laterally in physical contact with the first passivation layer”. However, there is no written support for this limitation nor do the Applicant’s figures clearly show the passivation layer physically contacting the pillar structure. Instead, Applicant’s Fig. 1B seems to show where the passivation layer directly physically contacts the top rounded portion of Item 14. The limitation should be cancelled from the claim or claim cancelled to resolve the new matter issue. Appropriate correction is required.
Claims 11-15 are also rejected under 35 USC 112(a) as they depend from and include all of the limitations of rejected claim 10.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2017/0365581) hereinafter “Yu” in view of Baloglu et al. (US 2017/0352613) hereinafter “Baloglu” and in further view of Chen et al. (US 2020/0135708) hereinafter “Chen”.
Regarding claim 1, Fig. 3 of Yu teaches a package structure (when the page is oriented upside down), comprising: a semiconductor device (Item 104a) comprising a conductive feature (Item 105d); a joint layer (Item 107a), disposed on the conductive feature (Item 105d); a pillar structure (Item 103a), disposed on and coupled to the semiconductor device (Item 104a) through the joint layer (Item 107a), where a bottom surface of the pillar structure (Item 103a) is between the joint layer (Item 107a) and the top surface of the pillar structure; an encapsulant (Item 109), laterally encapsulating the semiconductor device (Item 104a) and the pillar structure (Item 103a); and a redistribution layer structure (Item 102), electrically connected to the semiconductor device (Item 104a).
Yu does not teach a passivation layer laterally covering a sidewall of the conductive feature nor the joint layer being laterally covered by the passivation layer.
Fig. 4D of Baloglu teaches a package structure comprising a semiconductor device (Item 205a), a conductive feature (Item 210) and a pillar structure (Item 220), where a passivation layer (Item 215) is on a surface of the semiconductor device (Item 205a) such that the passivation layer (Item 215) laterally surrounds the conductive feature (Item 210) and laterally surrounds a portion of the pillar structure (Item 220), and where an underfill (Item 225) is on the passivation layer (Item 210) and surrounds the remainder of the pillar structure (Item 220).
It would have been obvious before the effective filing date of the claimed invention to include a passivation layer laterally covering a sidewall of the conductive feature of Yu and having a thickness of the passivation layer extend to a portion of the pillar structure of Yu such that the joint layer is laterally covered by the passivation because the passivation layer is purposely formed such that it protects the semiconductor die during manufacturing and beyond (Baloglu Paragraphs 0026-0027) and further protects the conductive feature from the outside environment (Baloglu Paragraph 0032).
Yu does not teach where the pillar structure has a top surface with rounding corners.
Chen teaches a pillar structure (Item 22) where a top surface of the pillar structure (Item 22) is rounded (Paragraph 0022).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the pillar structure have a top surface with rounding corners because the top surface having rounding corners is a known shape of a pillar structure (Chen Paragraph 0022) and a change in shape is an obvious matter of choice (MPEP 2144.04; See also In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.)
Regarding claim 2, Fig. 3 of Yu further teaches (when the page is oriented upside down) where a top surface of the encapsulant (Item 109) is lower than the top surface of the pillar structure (Item 103a).
Regarding claim 3, Fig. 3 of Yu further teaches where the joint layer (Item 107a) is disposed between the pillar structure (Item 103a) and the conductive feature (Item 105d) of the semiconductor device (Item 104a).
Regarding claim 6, Fig. 3 of Yu further teaches where the RDL structure (Item 102) is disposed on the pillar structure (Item 103a) and electrically connected to the semiconductor device (Item 104a) through the pillar structure (Item 103a).
Regarding claim 9, Fig. 3 of Yu further teaches an additional encapsulant (Item 108), disposed between the semiconductor device (Item 104a) and the encapsulant (Item 109), and between the pillar structure (Item 103a) and the encapsulant (Item 109), wherein the additional encapsulant (Item 108) is encapsulated by the encapsulant (Item 109).
Claims 10-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2017/0365581) hereinafter “Yu” in view of Baloglu et al. (US 2017/0352613) hereinafter “Baloglu” and in further view of Kuechenmeister et al. (US 2010/0164098) hereinafter “Kuechenmeister”.
Regarding claim 10, Fig. 3 of Yu (when the page is oriented upside down) teaches a package structure, comprising: a first semiconductor device (Item 104a) and a second semiconductor device (Item 105a) having different heights; a first pillar structure (Item 103a), disposed on the first semiconductor device (Item 104a); a second pillar structure (Item 103b), disposed on the second semiconductor device (Item 105a), wherein a top surface of the first pillar structure (Item 103a) is level with a top surface of the second pillar structure (Item 103b); a first encapsulant (Item 109), laterally encapsulating the first semiconductor device (Item 104a), the second semiconductor device (Item 105a), the first pillar structure (Item 103a) and the second pillar structure (Item 103b); and a package component (Item 102), electrically connected to the first semiconductor device (Item 104a) and the second semiconductor device (Item 105a).
Yu does not teach where the first semiconductor device includes a first passivation layer and the second semiconductor device includes a second passivation layer nor where the first pillar structure is laterally surrounded by the first passivation layer nor where the second pillar structure is laterally surrounded by the second passivation layer.
Fig. 4D of Baloglu teaches a package structure comprising a semiconductor device (Item 205a), a conductive feature (Item 210) and a pillar structure (Item 220), where a passivation layer (Item 215) is on a surface of the semiconductor device (Item 205a) such that the passivation layer (Item 215) laterally surrounds the conductive feature (Item 210) and laterally surrounds a portion of the pillar structure (Item 220), and where an underfill (Item 225) is on the passivation layer (Item 210) and surrounds the remainder of the pillar structure (Item 220).
It would have been obvious before the effective filing date of the claimed invention to have the first semiconductor device include a first passivation layer and the second semiconductor device include a second passivation layer where the first pillar structure is laterally surrounded by the first passivation layer and where the second pillar structure is laterally surrounded by the second passivation layer because the passivation layer is purposely formed such that it protects the semiconductor die during manufacturing and beyond (Baloglu Paragraphs 0026-0027) and further protects the pillar structure from the outside environment (Baloglu Paragraph 0032).
Yu does not teach where the first pillar structure is laterally in physical contact with the first passivation layer.
Fig. 2a of Kuechenmeister teaches where a passivation layer (Item 212) laterally surrounding and in physical contact with a pillar structure (Item 261).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first pillar structure laterally in physical contact with the first passivation layer because this allows mechanical stress exerted on the pillar structure to be transferred into the passivation layer and thus may be distributed across an increased area (Kuechenmeister Paragraph 0034).
Regarding claim 11, Fig. 3 of Yu further teaches (when the page is oriented upside down) where a top surface of the first semiconductor device (Item 104a) is higher than a top surface of the second semiconductor device (Item 105a), and a height of the first pillar structure (Item 103a) is less than a height of the second pillar structure (Item 103b).
Regarding claim 12, Fig. 3 of Yu further teaches (when the page is oriented upside down) comprising a second encapsulant (Item 108), encapsulating sidewalls and top surfaces of the first semiconductor device (item 104a) and the second semiconductor device (Item 105a) and sidewalls of the first pillar structure (Item 103a) and the second pillar structure (Item 103b), and the second encapsulant (Item 108) is encapsulated by the first encapsulant (Item 109).
Regarding claim 14, Fig. 3 of Yu further teaches (when the page is oriented upside down) an underfill layer (Item 108), disposed to fill a space between the first and second semiconductor devices (Items 104a and 105a, respectively) and the package component (Item 102), and the underfill layer (Item 108) is laterally encapsulated by the first encapsulant (Item 109).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2017/0365581) hereinafter “Yu” in view of Baloglu et al. (US 2017/0352613) hereinafter “Baloglu” and Chen et al. (US 2020/0135708) hereinafter “Chen” and in further view of Kim (US 2021/0013189) hereinafter “Kim”.
Regarding claim 4, the combination of Yu, Baloglu and Chen teaches all of the elements of the claimed invention as stated above except where the joint layer further extends to cover a bottom corner or a portion of a sidewall of the pillar structure.
Fig. 2C of Kim teaches where bottom corners of a pillar structure (Item 540) that contact a joint layer (Item 545) are rounded such that the joint layer (Item 545) covers a bottom corner of the pillar structure (Item 540).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the pillar structure of Yu have rounded corners such that the joint layer of Yu covers a bottom corner of the pillar structure of Yu, as taught by Kim, because this allows the pillar structure to move in a desired direction to help with alignment when the pillar is mated with the redistribution layer (Kim Paragraph 0038).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2017/0365581) hereinafter “Yu” in view of Baloglu et al. (US 2017/0352613) hereinafter “Baloglu” and Kuechenmeister et al. (US 2010/0164098) hereinafter “Kuechenmeister” and in further view of Wu (US 10,170,441) hereinafter “Wu”.
Regarding claim 15, the combination of Yu, Baloglu and Kuechenmeister teaches all of the elements of the claimed invention as stated above except where at least one of the first and second pillar structures comprises a pillar and a coating layer surrounding the pillar, the coating layer is disposed between the pillar and the first encapsulant, and a top surface of the pillar is level with or lower than a top surface of the coating.
Fig. 3A of Wu teaches where a pillar structure (Item 224 in Fig, 3B) comprises a pillar (Item 223) and a coating layer (Item 232) surrounding the pillar (Item 223), where the coating layer (Item 232) is merged (Column 5, Lines 49-53) with a joint layer (Item 224).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have at least one of the first and second pillar structures comprise a pillar and a coating layer surrounding the pillar, the coating layer being disposed between the pillar and the first encapsulant, and a top surface of the pillar is level with or lower than a top surface of the coating because this allows for effective coupling between the semiconductor device and another device (Wu Column 5, Lines 45-47).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2017/0365581) hereinafter “Yu” in view of Baloglu et al. (US 2017/0352613) hereinafter “Baloglu” and Chen et al. (US 2020/0135708) hereinafter “Chen” and in further view of Tsai (US 20190229046) hereinafter “Tsai”.
Regarding claim 7, the combination of Yu, Baloglu and Chen teaches all of the elements of the claimed invention as stated above except where the pillar structure is disposed on a first side of the semiconductor device, and the RDL structure is disposed on a second side of the semiconductor device opposite to the first side.
Tsai teaches a package structure where a first RDl layer (Item 701) is on a first side of a semiconductor device (Item SOC) and a second RDL layer (Item 1103) is on a second side of the semiconductor device (Item SOC), where the first side is opposite the second side.
It would have been obvious to one having ordinary skill in the art before the effective foiling date of the claimed invention to have RDL layers on both sides of the semiconductor device such that the pillar structure is disposed on a first side of the semiconductor device, and the RDL structure is disposed on a second side of the semiconductor device opposite to the first side because the RDL layers on both sides of the semiconductor device allows for devices above or below the semiconductor device to be connected to external connections (Tsai Paragraph 0081).
Regarding claim 8, Fig. 3 of Yu further teaches an underfill layer (Item 108), disposed to fill a space between the semiconductor device (Item 104a) and the RDL structure (Item 102), and the underfill material (Item 108) is laterally encapsulated by the encapsulant (Item 109).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2017/0365581) hereinafter “Yu” in view of Baloglu et al. (US 2017/0352613) hereinafter “Baloglu” and Kuechenmeister et al. (US 2010/0164098) hereinafter “Kuechenmeister” and in further view of Tsai (US 20190229046) hereinafter “Tsai”.
Regarding claim 13, the combination of Yu, Baloglu and Kuechenmeister teaches all of the elements of the claimed invention as stated above.
Yu further teaches wherein the first encapsulant (Item 109) is further disposed to fill a space between the first and second semiconductor devices (Items 104a and 105a) and the package component (Item 102).
Yu teaches all of the elements of the claimed invention as stated above except where the first and second pillar structures are disposed on a first side of the first and second semiconductor devices, and the package component is disposed on a second side of the first and second semiconductor devices opposite to the first side.
Tsai teaches a package structure where a first RDl layer (Item 701) is on a first side of a semiconductor device (Item SOC) and a second RDL layer (Item 1103) is on a second side of the semiconductor device (Item SOC), where the first side is opposite the second side.
It would have been obvious to one having ordinary skill in the art before the effective foiling date of the claimed invention to have RDL layers (package components) on both sides of the semiconductor devices such that the first and second pillar structures are disposed on a first side of the first and second semiconductor devices, and the package component is disposed on a second side of the first and second semiconductor devices opposite to the first side because the RDL layers on both sides of the semiconductor device allows for devices above or below the semiconductor device to be connected to external connections (Tsai Paragraph 0081).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2017/0365581) hereinafter “Yu” in view of Baloglu et al. (US 2017/0352613) hereinafter “Baloglu” and Kuechenmeister et al. (US 2010/0164098) hereinafter “Kuechenmeister” and in further view of Tsai (US 20190229046) hereinafter “Tsai” and Chen et al. (US 2015/0357318) hereinafter “Chen2”.
Regarding claim 21, the combination of Yu, Baloglu, Kuechenmeister and Tsai teaches all of the elements of the claimed invention as stated above except where the semiconductor device is electrically connected in the RDL structure through connectors therebetween.
Fig. 11 of Tsai further teaches where a semiconductor device (Item SOC) is electrically connected to a second RDL (Item 1103) on a second side of the semiconductor device through connectors (Items 1101) therebetween (See Examiner’s Note).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the semiconductor device be electrically connected in the RDL structure through connectors therebetween because the connectors allow various semiconductor devices in the package to work in conjunction or concurrently with each other (Tsai Paragraph 0083).
Yu does not teach where the connectors are located within a span of the semiconductor device.
Fig. 4A of Chen2 teaches where connectors for a semiconductor device are located within a span of a semiconductor device.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the connectors be located within a span of the semiconductor device because this allows the connectors to be directly connected to pads that are on the active surface of the semiconductor device (Chen2 Paragraph 0033).
Response to Arguments
Applicant’s arguments, see Applicant’s REMARKS, filed 03/18/2026, with respect to the rejection(s) of claim(s) 1 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chen.
Applicant’s arguments, see Applicant’s REMARKS, filed 03/18/2026, with respect to the rejection(s) of claim(s) 10 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kuechenmeister.
The Examiner notes that the Applicant argues that there is support for the amended in limitation of claim 10 in Applicant’s Figures. However, Applicant’s figures do not clearly show where the first pillar structure is laterally in physical contact with the first passivation layer. Instead, Fig. 1B of the Applicant’s drawings seem to show where the passivation layer makes lateral physical contact with Item 14. The Examiner also does not see any support in the Applicant’s written description. Appropriate new matter rejection and drawings objection have been made above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891
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