DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see remarks, filed 04/08/2026, with respect to the claim rejections under 35 USC 103 have been fully considered and are persuasive, the amendments made overcome the prior art of record. The 35 USC 103 rejections of the claims have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made incorporating US 20210098306 A1 Smith et al, US 20210313326 A1 Lim et al, and US 20220190161 A1 Miller et al.
Applicant's arguments filed in remarks 04/08/2026 have been fully considered but they are not persuasive.
Applicant argues in part “the Office Action does not provide a rationale for why the plurality of surfaces of the lower source/drain region extending in respective directions, each with a slope with respect to a horizontal and a vertical direction, would lead to crystallographically stable surfaces”. This argument is not persuasive as the prior art explicitly teaches that such a shape having plurality of surfaces of the lower source/drain region extending in respective directions, each with a slope with respect to a horizontal and a vertical direction such as a pentagonal shape would lead and/or be obtained by growing the source/drain along crystallographically stable surfaces in “The second source / drain regions 150B may have a pentagonal shape or the like, as shown, grown along a crystallographically stable surface during the growth process, but is not limited thereto” Cho Page 10 paragraph 3 of attached NPL translation of KR 20190108348 A. This is sufficient rational to modify Sobue in view of Cho to meet the claim limitations. Cho sufficiently in illustrates fig. 2B more than two directions [see annotation below] of a source/drain region and when combining with the lower source/drain Sobue the limitation argued is taught.
The applicant in part also argues that the meaning of “crystallographically stable” and/or “crystallographic stability” is unclear, The examiner respectfully disagrees “crystallographically stable” is a well documented term of the art known to one of ordinary skill in the art before the effective filing date of the claimed invention. As evidence the examiner submits US 20180090495 A1 Lee which agrees with the findings of Cho in paragraph 0069 “The second regions 112 may grow along a crystallographically stable plane in a growth process to have a pentagonal or hexagonal shape”. The examiner notes that “crystallographically stable” may have a broad meaning and/or many meanings under broadest reasonable interpretation but that does not make it unclear and/or indefinite as Breadth is not indefiniteness [See MPEP 2173.04]
The examiner has incorporated Smith to meet the new scope of “a capping layer is bounded by more than two of the plurality of surfaces”.
Applicant argues in part the Sobue in view of Cho does not teach “the capping layer comprises an oxide or a nitride of the first material”. The examiner respectfully disagrees under broadest reasonable interpretation the first material maybe Si wherein the lower source/drain comprises Silicon Germanium [Si in “SiGe” Paragraph 0054 Sobue] and the capping layer comprises a silicon oxide or a silicon nitride [paragraph 0054 Sobue]. The applicant in part argues “a preliminary capping layer may be epitaxially grown from the lower source/drain region, and the preliminary capping layer may be converted to the capping layer by oxidation and/or nitridation of the preliminary capping layer”, this product by process implies an additional atomic structure of the capping layer resulting by the growth and conversion process that is not currently claimed as written [See MPEP 2113 for product by process claims] it is noted that the features upon which applicant relies) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
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Annotated fig. 2B Cho: highlighting the more than 2 directions
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-17, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 20210366902 Sobue et al hereafter “Sobue” and in further view of KR 20190108348 A Cho et al hereafter “Cho” and US 20210098306 A1 Smith et al hereafter “Smith”.
Regarding claim 16 Sobue teaches an integrated circuit device (illustrated in fig. 25) comprising:
an upper transistor (comprising 341n, an upper portion of 358, and 388 see annotation below fig. 25) on a substrate (301 fig. 25), the upper transistor comprising: an upper active region (upper portion of 358 fig. 25); and
an upper source/drain region (comprising 341n and 388 fig. 25) contacting a side surface (left and right sides) of the upper active region;
a lower transistor (331p, a lower portion of 358 and 386, see annotation below fig. 25) between the substrate and the upper transistor, and the lower transistor comprising: a lower active region (a lower portion of 358 fig. 25); and
a lower source/drain region (comprising 331p and 386 fig. 25) contacting a side surface (left and right sides) of the lower active region;
and a capping layer (comprising 332 fig. 25) that is a first insulating layer (Paragraph 0054 “insulating film” meets the limitation),
wherein the lower source/drain region comprises a first material [Si in “SiGe” Paragraph 0054], wherein the capping layer comprises an oxide or a nitride of the first material [Silicon oxide or Silicon nitride].
wherein the lower source/drain region comprises a plurality of surfaces [4 top/bottom surfaces, 4 lateral-side surfaces, illustrated fig. 25].
the capping layer is bounded by the lower source/drain region, and wherein the capping layer has a uniform thickness along at least a portion the source drain region [sufficently illustrate fig. 25].
Sobue does not teach wherein the plurality of surfaces extend in respective directions that differ, wherein the capping layer is bounded by more than two of the plurality of surfaces, and wherein the capping layer has a uniform thickness along more than a portion of each of the more than two of the plurality of surfaces,
Cho teaches a source/drain region (150B fig. 2a) wherein the plurality of surfaces extend in respective directions that differ [sufficiently illustrated fig. 2a].
It would have been obvious to one of ordinary skill in the art to change the shape of a cross section across the lower source/drain and capping layer that Sobue teaches such that “the plurality of surfaces extend in respective directions that differ” as Cho to enable crystallographically stable surfaces during a growth process of the source/drain region [“The second source / drain regions 150B may have a pentagonal shape or the like, as shown, grown along a crystallographically stable surface during the growth process, but is not limited thereto” Cho Page 10 paragraph 3 of attached NPL translation of KR 20190108348 A] and/or it is prima facie type obviousness to substitute equivalents known for the same purpose, this case it is substituting one source/drain region for a known source/drain region with a pentagonal shape [See MPEP 2144.06].
Smith teaches a plurality of surfaces [the surfaces of source/drain comprising 118 and 116 fig. 1B] extend in respective directions that differ [fig. 1B illustrates sufficiently illustrates 5 different surface directions], wherein a capping layer (120 fig. 1B) is bounded by more than two of the plurality of surfaces [fig. 1B sufficiently illustrates 4 bounding surfaces], and wherein the capping layer has a uniform thickness along more than a portion of each of the more than two of the plurality of surfaces [illustrated with sufficient specificity fig. 1B], and a known alternative embodiment wherein a plurality of surfaces [the surfaces of source/drain comprising 118 and 116 fig. 1A] extend in respective directions that differ [fig. 1A illustrates sufficiently illustrates 5 different surface directions], wherein a capping layer (120 fig. 1B) is not bounded by more than two of the plurality of surfaces [fig. 1B sufficiently illustrates only 2 bounding surfaces], and wherein the capping layer has a uniform thickness along more than a portion of each of the more than two of the plurality of surfaces [illustrated with sufficient specificity fig. 1B].
It would have been obvious to one of ordinary skill in the art to change the shape of the capping layer of Sobue in view of Cho and Sith such that “the capping layer is bounded by more than two of the plurality of surfaces, and wherein the capping layer has a uniform thickness along at least a portion of each of the more than two of the plurality of surfaces” as a part of routine optimization of the insulation provide by the capping layer to the lower source/drain region [See MPEP 2144.05 II] and/or to isolate the upper and lower devices [sufficient disclosed paragraph 0065 “the dielectric cap (e.g., second dielectric caps 220) used to isolated the upper and lower devices” wherein in 220 fig. 2 is an embodiment of 120 in a stacked device].
In addition, substituting and/or combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is dielectric caps for the purpose of isolating upper and lower devices.
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Annotation of Fig. 25: highlighting the upper transistor and the lower transistor
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Annotated fig. 2B Cho: highlighting the more than 2 directions
Regarding claim 17 modified Sobue in view of Cho and smith teaches as shown above the integrated circuit device of Claim 16, wherein the capping layer comprises a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a silicon germanium nitride layer or a germanium nitride layer (Paragraph 0054 “a silicon oxide or a silicon nitride”).
Regarding claim 19 modified Sobue in view of Cho and Smith teaches as shown above the integrated circuit device of Claim 16, further comprising:
a second insulating layer (comprising, 321 and 322 fig. 25), wherein the upper source/drain region and the capping layer are in the second insulating layer [illustrated in fig. 25]; and
an etch stop layer (389 fig. 25) extending between the second insulating layer and the upper source/drain region [fig. 25 illustrated as extending (horizontally) between (in a vertical direction) the top of the upper/source drain region and a top region of the capping layer] and the etch stop layer between the insulating layer and the capping layer [illustrated as between the insulating layer and a top region of the capping layer in a direction from bottom to top of fig 25. and/or in a vertical direction relative to the cross section of fig. 25]. Note that the manner in which claim 19 is presently written does not require the etch stop layer to also extend between the insulating layer and the capping layer; furthermore, the extent of the ‘extending between’ with respect to the insulating layer and the upper source/drain region is not specified.
Sobue does not explicitly teach the etch stop layer and the capping layer comprising different materials.
Sobue teaches insulating films comprising of silicon nitride and/or silicon oxide [paragraph 0053].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select the known materials of silicon oxide for the capping layer and silicon nitride for the etch stop layer, such that the etch stop layer and the capping layer comprises different materials, based on the materials suitability for the materials intended use [see MPEP 2144.07] and/or for the known material properties of the materials, such as the known dielectric constants and known etch rates.
Regarding claim 20 Modified Sobue in view of Cho and Smith as shown above teaches the integrated circuit device of Claim 19, wherein the etch stop layer contacts the upper source/drain region and the capping layer [illustrated in fig. 25] and comprises silicon and nitrogen [as modified above in claim 19].
Claim 18 is rejected under 35 USC 103 as obvious over Sobue in view of Cho and Smith as shown above and in further view of US 20210313326 A1 Lim et al hereafter “Lim”.
Regarding claim 18 modified Sobue in view of Cho and Smith teaches as shown above the integrated circuit device of Claim 16, wherein the upper source/drain region contacts the capping layer [illustrated in fig. 25],
Sobue in view of Cho and Smith does not teach wherein a first profile of the upper source/drain region in across-sectional view is different from a second profile of the lower source/drain region in the cross-sectional view
Lim teaches a similar device wherein a first profile [Hexgon shape of 224 fig. 2] of a upper source/drain region (224 fig. 2) in across-sectional [B-B’ fig. 2] view is different from a second profile [rectangular shape of 216 fig. 2] of a lower source/drain region (216 fig. 2) in the cross-sectional view.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sobue in view of Cho and Smith in further view of Lim such that “wherein a first profile of the upper source/drain region in across-sectional view is different from a second profile of the lower source/drain region in the cross-sectional view”.
A person of ordinary skill in the art would have been motivated to make this modification to enable portions of the different source/drain regions to electrically couple to various electrically conductive terminals [disclosed Paragraph 0038 “The extended portion of the source region or drain region may enable the transistor, which is disposed below the other transistor in the layered arrangement, to electrically couple to various electrically conductive terminals 240, 242” Lim]
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is combining stacked/layered transistor devices for the purpose of forming a semiconductor device with desirable electron mobility for the n-type transistor and desirable hole mobility for the p-type transistor [paragraph 0018 Lim].
Claim 21 is rejected under 35 USC 103 as obvious over Sobue in view of Cho and Smith as shown above and in further view of US 20220190161 A1 Miller et al here after “Miller”.
Regarding claim 21 Modified Sobue in view of Cho and Smith teach as shown above the integrated circuit device of Claim 16, further comprising an isolation layer on a lower surface of the lower source/drain region [316 fig. 24], and
Sobue in view of Cho and Smith does not teach the isolation layer is bounded by the capping layer.
Miller teaches a similar device comprising an isolation layer (36 fig. 1A) is bounded by a capping layer (37 fig. 1A, met under broadest reasonable interpretation and/or MPEP 2112.01 layer 37 comprising a silicon nitride and/or oxide in “silicon-carbon-boron-nitrogen (SiCBN), silicon oxycarbide (SiOC) or silicon-carbon-oxynitride (SiCON)” Paragraph 0053) [illustrated fig. 1A left and right sides are bounded.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sobue in view of Cho and Smith in view of Miller such that “the isolation layer is bounded by the capping layer”.
A person of ordinary skill in the art would have been motivated to make this modification to Protect the isolation layer from subsequent etching and/or manufacturing processes.
Combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. Combining capping layers for the same purpose of protecting underlying layers from subsequent etching and/or manufacturing processes.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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