DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see remarks, filed 10/22/2025, with respect to USC 103 Claim rejections have been fully considered and are persuasive. The USC 103 Rejections of the claims has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of KR 20190108348 A Cho et al.
Request for Rejoinder acknowledged however the application is not yet considered to be in an allowable state.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-21 are rejected under 35 U.S.C. 103 as being unpatentable over US 2010366902 Sobue et al hereafter “Sobue” and in further view of KR 20190108348 A Cho et al hereafter “Cho”.
Regarding claim 16 Sobue teaches an integrated circuit device (illustrated in fig. 25) comprising:
an upper transistor (comprising 341n, an upper portion of 358, and 388 see annotation below fig. 25) on a substrate (301 fig. 25), the upper transistor comprising: an upper active region (upper portion of 358 fig. 25); and
an upper source/drain region (comprising 341n and 388 fig. 25) contacting a side surface (left and right sides) of the upper active region;
a lower transistor (331p, a lower portion of 358 and 386, see annotation below fig. 25) between the substrate and the upper transistor, and the lower transistor comprising: a lower active region (a lower portion of 358 fig. 25); and
a lower source/drain region (comprising 331p and 386 fig. 25) contacting a side surface (left and right sides) of the lower active region;
and a capping layer (comprising 332 fig. 25) that is a first insulating layer (Paragraph 0054 “insulating film” meets the limitation),
wherein the lower source/drain region comprises a plurality of surfaces [4 top/bottom surfaces, 4 lateral-side surfaces, illustrated fig. 25].
the capping layer is bounded by the lower source/drain region, and wherein the capping layer has a uniform thickness along at least a portion the source drain region [sufficently illustrate fig. 25].
Sobue does not teach wherein the plurality of surfaces extend in respective directions that differ, wherein the capping layer is bounded by at least two of the plurality of surfaces, and wherein the capping layer has a uniform thickness along at least a portion of each of the at least two of the plurality of surfaces.
Cho teaches a source/drain region (150B fig. 2a) wherein the plurality of surfaces extend in respective directions that differ [sufficiently illustrated fig. 2a].
It would have been obvious to one of ordinary skill in the art to change the shape of a cross section across the lower source/drain and capping layer that Sobue teaches such that “the plurality of surfaces extend in respective directions that differ” as Cho to enable crystallographically stable surfaces during a growth process of the source/drain region [“The second source / drain regions 150B may have a pentagonal shape or the like, as shown, grown along a crystallographically stable surface during the growth process, but is not limited thereto” Cho Page 10 paragraph 3 of attached NPL translation of KR 20190108348 A] and/or it is prima facie type obviousness to substitute equivalents known for the same purpose, this case it is substituting one source/drain region for a known source/drain region with a pentagonal shape [See MPEP 2144.06].
It would have been obvious to one of ordinary skill in the art to change the shape of the capping layer of Sobue in view of Cho such that “the capping layer is bounded by at least two of the plurality of surfaces, and wherein the capping layer has a uniform thickness along at least a portion of each of the at least two of the plurality of surfaces” as a part of routine optimization of the insulation provide by the capping layer to the lower source/drain region [See MPEP 2144.05 II].
PNG
media_image1.png
740
586
media_image1.png
Greyscale
Annotation of Fig. 25: highlighting the upper transistor and the lower transistor
Regarding claim 17 modified Sobue in view of Cho teaches as shown above the integrated circuit device of Claim 16, wherein the capping layer comprises a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a silicon germanium nitride layer or a germanium nitride layer (Paragraph 0054 “a silicon oxide or a silicon nitride”).
Regarding claim 18 modified Sobue in view of Cho teaches as shown above the integrated circuit device of Claim 16, wherein the upper source/drain region contacts the capping layer [illustrated in fig. 25].
Regarding claim 19 modified Sobue in view of Cho teaches as shown above the integrated circuit device of Claim 16, further comprising:
a second insulating layer (comprising, 321 and 322 fig. 25), wherein the upper source/drain region and the capping layer are in the second insulating layer [illustrated in fig. 25]; and
an etch stop layer (389 fig. 25) extending between the second insulating layer and the upper source/drain region [fig. 25 illustrated as extending (horizontally) between (in a vertical direction) the top of the upper/source drain region and a top region of the capping layer] and the etch stop layer between the insulating layer and the capping layer [illustrated as between the insulating layer and a top region of the capping layer in a direction from bottom to top of fig 25. and/or in a vertical direction relative to the cross section of fig. 25]. Note that the manner in which claim 19 is presently written does not require the etch stop layer to also extend between the insulating layer and the capping layer; furthermore, the extent of the ‘extending between’ with respect to the insulating layer and the upper source/drain region is not specified.
Sobue does not explicitly teach the etch stop layer and the capping layer comprising different materials.
Sobue teaches insulating films comprising of silicon nitride and/or silicon oxide [paragraph 0053].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select the known materials of silicon oxide for the capping layer and silicon nitride for the etch stop layer, such that the etch stop layer and the capping layer comprises different materials, based on the materials suitability for the materials intended use [see MPEP 2144.07] and/or for the known material properties of the materials, such as the known dielectric constants and known etch rates.
Regarding claim 20 Modified Sobue in view of Cho as shown above teaches the integrated circuit device of Claim 19, wherein the etch stop layer contacts the upper source/drain region and the capping layer [illustrated in fig. 25] and comprises silicon and nitrogen [as modified above in claim 19].
Regarding claim 21 Modified Sobue in view of Cho teach as shown above the integrated circuit device of Claim 16, wherein the lower source/drain region comprises silicon germanium [at least partially, disclosed paragraph 0054 “The p-type semiconductor layers 331p are p-type SiGe layers”].
Alternatively, if the applicant disagrees it would have been obvious to one of ordinary skill in the art before the effective filing date to select known a material like SiGe as taught by Sobue such that the lower source drain region fully comprises SiGe for the known semiconductive material properties of SiGe [see MPEP 2144.07].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893