DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Applicant’s amendments filed 12/27/2025 have been entered. Claims 5 and 7 are cancelled, Claim 4 remains withdrawn, and Claims 1-4, 6, and 8-22 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8, 10, 19, and 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Or-Bach et al. (US 20110084314 A1) hereinafter “Or-Bach”.
Regarding Claim 1, Figure 48C of Or-Bach teaches: an integrated circuit (IC) device (Paragraph 0003), comprising: a substrate (N Si Substrate); a channel layer (See annotated Figure 48C of Or-Bach below; CL) over the substrate; a first transistor (See annotated Figure 48C of Or-Bach below; T1) and a second transistor (See annotated Figure 48C of Or-Bach below; T2); and a first contact (4812; See annotated Figure 48C of Or-Bach below; C1), a second contact (4806; See annotated Figure 48C of Or-Bach below; C2), and a third contact (4810; See annotated Figure 48C of Or-Bach below; C3), wherein: a channel region (See annotated Figure 48C of Or-Bach below; CR1) of the first transistor includes a first portion of the channel layer, a channel region (See annotated Figure 48C of Or-Bach below; CR2) of the second transistor includes a second portion of the channel layer, the first contact is a first one of a pair of a source contact and a drain contact of the first transistor (Paragraph 0730), the third contact is a first one of a pair of a source contact and a drain contact of the second transistor (Paragraph 0730), the second contact is a second one of the pair of the source contact and the drain contact of the first transistor and a second one of the pair of the source contact and the drain contact of the second transistor (Paragraph 0713; Where contact 4406, comparable to 4806, is a metal contact), the first contact extends into the channel layer (Item 4812 extends into the channel layer; Figure 48C) without extending through an entire thickness of the channel layer (See annotated Figure 48C of Or-Bach; Item marked C1 extends into layer marked CL without extending fully through).
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Annotated Figure 48C of Or-Bach
Regarding Claim 8, Figure 48C of Or-Bach teaches: the channel layer (See annotated Figure 48C of Or-Bach above; CL) has a first face (bottom vertically of CL) and an opposing second face (top vertically of CL), and the first contact (4812; See annotated Figure 48C of Or-Bach above; C1) that extends into the channel layer extends from the second face of the channel layer to the first face of the channel layer (Figure 48C).
Regarding Claim 10, Figure 48C of Or-Bach teaches: the channel layer (See annotated Figure 48C of Or-Bach above; CL) has a first face (bottom vertically of CL) and an opposing second face (top vertically of CL), and the first contact (4812; See annotated Figure 48C of Or-Bach above; C1) extends into the channel layer extends from the second face of the channel layer towards the first face of the channel layer but does not reach the first face of the channel layer (Figure 48C).
Regarding Claim 19, Figure 48C of Or-Bach teaches: A process of making an integrated circuit (IC) device (Paragraph 0003), the process comprising: providing a channel layer (See annotated Figure 48C of Or-Bach above; CL), the channel layer having a first face (See annotated Figure 48C of Or-Bach above; top vertically of item marked CL) and an opposing second face (See annotated Figure 48C of Or-Bach above; bottom vertically of item marked CL); over a substrate (N Si Substrate); providing a first transistor (See annotated Figure 48C of Or-Bach above; T1) and a second transistor (See annotated Figure 48C of Or-Bach above; T2); and providing a first contact (4812; See annotated Figure 48C of Or-Bach above; C1), a second contact (4806; See annotated Figure 48C of Or-Bach above; C2), and a third contact (4810; See annotated Figure 48C of Or-Bach above; C3), wherein: a channel region (See annotated Figure 48C of Or-Bach above; CR1) of the first transistor includes a first portion of the channel layer, a channel region (See annotated Figure 48C of Or-Bach above; CR2) of the second transistor includes a second portion of the channel layer, the first contact is a first one of a pair of a source contact and a drain contact of the first transistor (Paragraph 0730), the third contact a first one of a pair of a source contact and a drain contact of the second transistor (Paragraph 0730), the second contact is a second one of the pair of the source contact and the drain contact of the first transistor and a second one of the pair of the source contact and the drain contact of the second transistor (Paragraph 0713; Where contact 4406, comparable to 4806, is a metal contact), and the first contact extends into the channel layer (Item 4812 extends into the channel layer; Figure 48C) from the first face of the channel layer, and a portion (item N+ below item 4812) of a material (Figures 44A-44E; Where an N+ implant is performed on item 4301) of the channel layer is between the second face of the channel layer and the first contact that extends into the channel layer from the first face of the channel layer.
Regarding Claim 21, Figures 19C-E and Figure 48C of Or-Bach teach: An integrated circuit (IC) package (Figure 19D; Paragraph 0281), comprising: a die (19D14) comprising an IC device (Paragraph 0281); and a further component (19D06; Paragraph 0282) coupled with the die, wherein the die includes: a channel layer (See annotated Figure 48C of Or-Bach above; CL), a first transistor (See annotated Figure 48C of Or-Bach above; T1)and a second transistor(See annotated Figure 48C of Or-Bach above; T2), and a first contact (4812; See annotated Figure 48C of Or-Bach above; C1), a second contact (4806; See annotated Figure 48C of Or-Bach above; C2), and a third contact (4810; See annotated Figure 48C of Or-Bach above; C3) wherein: a channel region (See annotated Figure 48C of Or-Bach above; CR1) of the first transistor includes a first portion of the channel layer, a channel region (See annotated Figure 48C of Or-Bach above; CR2) of the second transistor includes a second portion of the channel layer, the first contact is a first one of a pair of a source contact and a drain contact of the first transistor (Paragraph 0730), the third contact is a first one of a pair of a source contact and a drain contact of the second transistor (Paragraph 0730), the second contact is a second one of the pair of the source contact and the drain contact of the first transistor and a second one of the pair of the source contact and the drain contact of the second transistor (Paragraph 0713; Where contact 4406, comparable to 4806, is a metal contact), the channel layer has a first face (See annotated Figure 48C of Or-Bach above; top vertically of item marked CL) and an opposing second face (See annotated Figure 48C of Or-Bach above; bottom vertically of item marked CL), the first contact extends into the channel layer (Item 4812 extends into the channel layer; Figure 48C) from the first face of the channel layer, and a portion (item N+ below item 4812) of a material (Figures 44A-44E; Where an N+ implant is performed on item 4301) of the channel layer is between the second face of the channel layer and the first contact that extends into the channel layer from the first face of the channel layer.
Regarding Claim 22, Figures 19C-E and Figure 48C of Or-Bach teach: the further component (19D06; Paragraph 0282) is an interposer (Paragraph 0282).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 6, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 20110084314 A1) hereinafter “Or-Bach” in view of Schuele et al. (US 20080057649 A1) hereinafter “Schuele”.
Regarding Claim 2, Figure 48C of Or-Bach teaches: the channel layer (See annotated Figure 48C of Or-Bach above; CL) has a first face (bottom vertically of CL; See annotated Figure 48C of Or-Bach above) and an opposing second face (top vertically of CL; See annotated Figure 48C of Or-Bach above), the second contact (4806; See annotated Figure 48C of Or-Bach above; C2) has a portion at the first face of the channel layer, the first contact (4806; See annotated Figure 48C of Or-Bach above; C1) has a portion at the second face of the channel layer and is the first contact that extends into the channel layer, the first transistor has a gate (4802) having a portion at the second face of the channel layer
Or-Bach does not teach: the gate extending into the channel layer
Figure 5 of Schuele teaches: a thin-film transistor (Paragraph 0031) with a recessed gate (526) formed in an active region (512)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the gate extending into the channel layer because Schuele teaches a gate recessed into an active layer blocks dopants in the channel region (Schuele Paragraph 0038).
The combination of the recessed gate of Schuele and the structure of Or-Bach will yield a structure such that a portion of the channel layer is between a portion of the first contact that extends into the channel layer and a portion of the gate that extends into the channel layer.
Regarding Claim 6, Figure 48C of Or-Bach teaches: the first face (bottom vertically of CL; See annotated Figure 48C of Or-Bach above) of the channel layer (See annotated Figure 48C of Or-Bach above; CL) is closer to substrate (N Si Substrate) the than the second face (top vertically of CL; See annotated Figure 48C of Or-Bach above) of the channel layer.
Regarding Claim 20, Figure 48C of Or-Bach teaches: providing the first transistor (See annotated Figure 48C of Or-Bach above; T1) includes providing a gate stack (4802) of the first transistor
Or-Bach does not teach: the gate stack is at least partially recessed into the channel layer.
Figure 5 of Schuele teaches: a thin-film transistor (Paragraph 0031) with a recessed gate (526) formed in an active region (512)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the gate extending into the channel layer because Schuele teaches a gate recessed into an active layer blocks dopants in the channel region (Schuele Paragraph 0038).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 20110084314 A1) hereinafter “Or-Bach” in view of Isobe et al. (US 20130161621 A1) hereinafter “Isobe”.
Regarding Claim 3, Or-Bach teaches all of the limitations of the claimed invention as stated above.
Or-Bach does not teach: a distance between the portion of the first contact that extends into the channel layer and the portion of the gate that extends into the channel layer is between about 1 and 20 nanometers.
Figure 6A of Isobe teaches: a transistor (162) with a source contact region (combination of 142a and 144) and a gate electrode (148), wherein the distance between the source contact region and the gate electrode is between 1 nm and 30 nm. (Paragraph 0198)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a distance between the portion of the first contact that extends into the channel layer and the portion of the gate that extends into the channel layer is between about 1 and 30 nanometers, as taught by Isobe because Isobe teaches this distance improves the on-state characteristics of the transistor (Isobe Paragraph 0198).
Furthermore, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists, MPEP 2144.05, In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). In the instant case, the claimed range, 1 nm to 20 nm, lies inside the range of Isobe, 1 nm to 30 nm.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 20110084314 A1) hereinafter “Or-Bach” in view of Suzuki et al. (US 20190148558 A1) hereinafter “Suzuki.”
Regarding Claim 9, Or-Bach teaches all of the limitations of the claimed invention as stated above.
Or-Bach does not teach: the first contact that extends into the channel layer from the second face of the channel layer to the first face of the channel layer extends further into an insulating material at the first face of the channel layer.
Figure 4B of Suzuki teaches: an oxide semiconductor TFT (Paragraph 0054) with contacts (114 and 113) that extend through a channel layer (107) from the second face (top vertically of 107) of the channel layer to the first face (bottom vertically of 107) of the channel layer and extends further into an insulating material (105) at the first face of the channel layer
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first contact that extends into the channel layer from the second face of the channel layer to the first face of the channel layer extends further into an insulating material at the first face of the channel layer because Suzuki teaches a larger contact area enables reduction in the contact resistance (Suzuki Paragraph 0052).
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 20110084314 A1) hereinafter “Or-Bach” in view of Then et al. (US 20200219986 A1) hereinafter “Then” and Rios et al. (US 20160181424 A1) hereinafter “Rios”.
Regarding Claim 12, Or-Bach teaches all of the limitations of the claimed invention as stated above.
Or-Bach does not teach: the first contact that extends into the channel layer includes a metal and a semiconductor material in contact with the metal
Figure 1 of Then teaches: a transistor (102) with a contact (combination of 126/118 and 116), wherein the contact includes a metal layer (126/118; Paragraph 0039) with semiconductor material layer (116; Paragraph 0038)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first contact that extends into the channel layer includes a metal and a semiconductor material in contact with the metal because Then teaches the combination of these two layer advantageously form Ohmic contacts (Then Paragraph 0038).
Or-Bach does not teach: the semiconductor material has a bandgap that is smaller than at least one of: a bandgap of a semiconductor material of the channel region of the first transistor, and a bandgap of a semiconductor material of the channel region of the second transistor.
Figure 1a of Rios teaches: a transistor (100) with a contact (combination of 106 and 108) with a metal layer (106) and a semiconductor layer (108) and a channel layer (110) comprising a semiconductor material (Paragraph 11); wherein the semiconductor layer of the contact has a smaller band gap (Paragraph 0017) than the band gap of the semiconductor material of the channel layer (Paragraph 0022)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the semiconductor material has a bandgap that is smaller than at least one of: a bandgap of a semiconductor material of the channel region of the first transistor, and a bandgap of a semiconductor material of the channel region of the second transistor because Rios teaches a smaller band gap at the source/drain contact results in reduced external parasitic resistance of the device (Rios Paragraph 0010).
Regarding Claim 13, the combination of Or-Bach, Then, and Rios teaches all of the limitations of the claimed invention as stated above.
Or-Bach does not teach: at least a portion of the semiconductor material of the first contact that extends into the channel layer is in contact with the channel layer, and no portion of the metal of the first contact that extends into the channel layer is in contact with the channel layer.
However, the combination of the semiconducting material layer of Then, wherein the semiconducting material layer is formed to intersect the metal layer and the channel layer, with the structure of Or-Bach, will yield a structure such that at least a portion of the semiconductor material of the first contact that extends into the channel layer is in contact with the channel layer, and no portion of the metal of the first contact that extends into the channel layer is in contact with the channel layer.
Regarding Claim 14, the combination of Or-Bach, Then, and Rios teaches all of the limitations of the claimed invention as stated above.
Or-Bach does not teach: at least a portion of the semiconductor material of the first contact that extends into the channel layer is in contact with the channel layer, and at least a portion of the metal of the first contact that extends into the channel layer is in contact with the channel layer.
However, the combination of the semiconductor material portion shape of Rios, wherein the semiconductor material portion is formed only under the metal portion, in combination with the structure of Or-Bach will yield a structure such that at least a portion of the semiconductor material of the first contact that extends into the channel layer is in contact with the channel layer, and at least a portion of the metal of the first contact that extends into the channel layer is in contact with the channel layer.
Regarding Claim 15, the combination of Or-Bach, Then, and Rios teaches all of the limitations of the claimed invention as stated above.
Or-Bach does not teach: the semiconductor material of the first contact that extends into the channel layer has dopants at a concentration of at least about 5x1020 dopants per cubic centimeter.
Figure 1 of Then teaches: a transistor (102) with a contact (combination of 126/118 and 116), wherein the contact includes a metal layer (126/118; Paragraph 0039) with semiconductor material layer (116; Paragraph 0038), wherein the semiconductor material has dopants at a concentration of 1x1021 dopants per cubic centimeter (Paragraph 0038).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the semiconductor material of the first contact that extends into the channel layer has dopants at a concentration of at least about 1x1021 dopants per cubic centimeter because Then teaches the semiconductor material layer needs to be highly doped in order to form Ohmic contact with the source/drain electrodes (Then Paragraph 0038).
Furthermore, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists, MPEP 2144.05, In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). In the instant case, the claimed range of, at least about 5x1020 dopants per cubic centimeter overlaps with the range of Then of 1x1021 dopants per cubic centimeter.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 20110084314 A1) hereinafter “Or-Bach” in view of Headrick (US 20080138927 A1) hereinafter “Headrick.”
Regarding Claim 16, Or-Bach teaches all of the limitations of the claimed invention as stated above.
Or-Bach does not teach: at least one of the channel region of the first transistor and the channel region of the second transistor includes a semiconductor material having an average grain size larger than about 1 millimeter.
Figure 11A of Headrick teaches: a thin-film transistor (110) with a source layer (1120), a drain layer (1124), a gate contact layer (1104) and a channel layer (1128) including a semiconductor material (Paragraph 0076; wherein item 1116 is comparable to 1128) and the average grain size is larger than about 1 millimeter (Paragraph 0067).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have at least one of the channel region of the first transistor and the channel region of the second transistor includes a semiconductor material having an average grain size larger than about 1 millimeter because Headrick teaches methods that produce grain sizes larger than about 1 millimeter are 1ow-cost, high throughput methods that produce high-quality structures (Headrick Paragraph 0028).
Regarding Claim 17, Or-Bach teaches all of the limitations of the claimed invention as stated above.
Or-Bach does not teach: at least one of the channel region of the first transistor and the channel region of the second transistor includes a semiconductor material having an average grain size smaller than about 1 millimeter.
Figure 11A of Headrick teaches: a thin-film transistor (110) with a source layer (1120), a drain layer (1124), a gate contact layer (1104) and a channel layer (1128) including a semiconductor material (Paragraph 0076; wherein item 1116 is comparable to 1128) and the average grain size is between 0.1 mm to 1 mm (Paragraph 0069).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have at least one of the channel region of the first transistor and the channel region of the second transistor includes a semiconductor material having an average grain size smaller than about 1 millimeter because Headrick teaches methods that produce grain sizes between 0.1 mm to 1 mm are 1ow-cost, high throughput methods that produce high-quality structures (Headrick Paragraph 0028).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 20110084314 A1) hereinafter “Or-Bach” in view of Sharma et al. (US 20200388685 A1) hereinafter “Sharma”.
Regarding Claim 18, Or-Bach teaches all of the limitations of the claimed invention as stated above.
Or-Bach does not explicitly teach: the channel layer is a fin, a nanoribbon, or a nanowire.
Figures 3-19B of Sharma teach: transistor structures (201) with different shape channels (Paragraph 0048; Wherein the channels can be vertical, lateral, or fins)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the channel layer be a fin because Sharma teaches transistor structures can be planar or non-planar and arrayed over device layers within integrated circuit dies (Sharma Paragraph 0048).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 20110084314 A1) hereinafter “Or-Bach” in view of Schuele et al. (US 20080057649 A1) hereinafter “Schuele” and Le et al. (US 20190355725 A1) hereinafter “Le.”
Regarding Claim 11, Figure 48C of Or-Bach teaches: the channel layer (See annotated Figure 48C of Or-Bach above; CL) has a first face (bottom vertically of CL; See annotated Figure 48C of Or-Bach above) and an opposing second face (top vertically of CL; See annotated Figure 48C of Or-Bach above), the second contact (4806; See annotated Figure 48C of Or-Bach above; C2) has a portion at the first face of the channel layer, the first contact (4806; See annotated Figure 48C of Or-Bach above; C1) has a portion at the second face of the channel layer and is the first contact that extends into the channel layer, the first transistor has a gate (4802) having a portion at the second face of the channel layer
Or-Bach does not teach: the gate extending into the channel layer
Figure 5 of Schuele teaches: a thin-film transistor (Paragraph 0031) with a recessed gate (526) formed in an active region (512)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the gate extending into the channel layer because Schuele teaches a gate recessed into an active layer blocks dopants in the channel region (Schuele Paragraph 0038).
Or-Bach does not teach: a portion of the first contact that extends into the channel layer is in contact with a portion of the gate that extends into the channel layer.
Figures 11A-C of Le teach: a TFT structure (201) with self-aligned source/drain contacts (250) in contact with a gate structure (combination of 273 and 271)
It would be obvious to one of ordinary skill in the art to have a portion of the first contact that extends into the channel layer is in contact with a portion of the gate that extends into the channel layer because Le teaches self-aligned contacts (SAC) formed to contact the gate structure provide good control over the length of the TFT channel (Le Paragraph 0048).
Response to Arguments
Applicant's arguments filed 12/27/2025, regarding the 35 U.S.C. 102 rejections of Claims 1 and 19 have been fully considered but they are not persuasive.
Regarding Claim 1, and similarly Claim 19, the Applicant argues that Or-Bach does not teach “at least one of the first contact, the second contact, and the third contact extends into the channel layer without extending through an entire thickness of the channel layer.” The Examiner respectfully disagrees and asserts that the first contact of Or-Bach extends into the channel layer without extending through an entire thickness of the channel layer. As stated in the 35 U.S.C. 102 rejection of Claim 1 above, item 4812 is a contact that extends into the channel layer, as annotated in Figure 48C of Or-Bach, by the Examiner (See Annotated Figure 48C of Or-Bach above). The channel layer, annotated as item CL, includes the oxide 4402 (Defined in Figures 44A-E), the N+ implanted source/drain region of the channel, and the P- layer (Defined in Figures 44A-E). The first contact 4812, passes through the oxide (item 4402) to contact the N+ implanted region of the channel layer, without extending through the entire thickness of the channel layer. Therefore, the Examiner does not find the Applicant’s arguments to be persuasive and will continue to rely upon Or-Bach to teach the limitations of Claims 1 and 19.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Halee Cramer whose telephone number is (571)270-1641. The examiner can normally be reached Monday - Friday 7:30am - 4:30pm.
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/HALEE CRAMER/Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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