DETAILED ACTION
This Office Action is in response to the Amendment filed 30 July 2025. Claims 1, 3-20 are pending in this application, and Claim 2 is cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1, 3-20 objected to because of the following informalities:
Regarding Claim 1, in lines 10-11 of the claim, applicant claims “wherein the first spacer, the second, the third spacer, the fourth spacer are respectively directly on the dielectric layer”. There should be an and after “the third spacer”.
Suggested fix: “wherein the first spacer, the second, the third spacer, and the fourth spacer are respectively directly on the dielectric layer”
Regarding Claims 3-20, Claims 3-20 depend from Claim 1 and are objected to for the same reasons.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Applicant’s amendment, filed on 30 July 2025, has addressed the previous 112b issues. Therefore, the 112b previous rejection of Claims 1, 3-20 are withdrawn.
Claim 1, 3-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1, in lines 10-11 of the claim, applicant claims “wherein the first spacer, the second, the third spacer, the fourth spacer are respectively directly on the dielectric layer”. It is unclear what “the second” is referring to. For purposes of examination, examiner will treat the claim as reciting “the second spacer”.
Regarding Claims 3-20, Claims 3-20 depend from Claim 1 and are rejected for the same reasons.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1,3-11, 13, 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fan et. al (US 2020/0321215 A1) (newly cited) in view of Roehner et. al (US 2015/0177310 A1) (of record)
Regarding Claim 1, Fan discloses (as shown in Figs. 1-10) A method of manufacturing a semiconductor device ([0075] semiconductor structure 900), ([0082] FIG. 10 illustrates an exemplary method to cut dense line patterns using self-aligned double pattering) comprising:
disposing a dielectric layer ([0049] The first dielectric layer 106) directly ([0049] The first dielectric layer 106 is disposed on top of the insulating layer 104) on a surface of a substrate ([0049] insulating layer 104) in which conductive elements are formed ([0075] In some embodiments, the insulating layer 104 of the semiconductor structure 900/901 can include one or more conductive structures (e.g., a conductive structure 980 shown in FIG. 9B in a cross-sectional view along a line 102), in contact with the objective lines 950/960);
disposing a mandrel layer ([0046] plurality of mandrel lines 101) directly on the dielectric layer (106); ([0046] the plurality of mandrel lines 101 disposed on top of the first dielectric layer 106)
patterning the mandrel layer ([0050] The forming of the mandrel lines 101 includes disposing a sacrificial material on top of the first dielectric layer 106 and patterning the sacrificial material) to form a first mandrel ([0046] plurality of mandrel lines 101) and a second mandrel ([0046] plurality of mandrel lines 101) spaced apart from the first mandrel (101), (See Fig. 1, showing a plurality of mandrel lines 101)
wherein the minimum distance (See Fig. 1, showing the spacing between mandrel lines is B1) between the first mandrel (101) and the second mandrel (101) is equal to or less than 90 nm ([0065] For example… “b1” or “b6” can be designed as 60 nm);
forming a first spacer ([0059] dielectric spacers 422) adjacent to a first side (left) of the first mandrel (101), a second spacer ([0059] dielectric spacers 422) adjacent to a second side (right) of the first mandrel (101), a third spacer ([0059] dielectric spacers 422) adjacent to a first side (left) of the second mandrel (101), and a fourth spacer ([0059] dielectric spacers 422) adjacent to a second side (right) of the second mandrel (101), ([0059] wherein dielectric spacers 422 are formed on the sidewalls of the mandrel lines 101)
wherein the first spacer (422), the second (422), the third spacer (422), the fourth spacer (422) are respectively directly on the dielectric layer (106); (See Fig. 4, showing the dielectric spacers 422 directly on the dielectric layer 106)
etching the dielectric layer (106) by using the first spacer (422), the second spacer (422), the third spacer (422), and the fourth spacer (422) as etching masks to form a first dielectric element (See Ann. Fig. 7; 106-1), a second dielectric element (See Ann. Fig. 7; 106-2), a third dielectric element (See Ann. Fig. 7; 106-3), and a fourth dielectric element (See Ann. Fig. 7; 106-4) directly on the surface of the substrate (104), ([0073] FIG. 7 illustrates a schematic top-down (top) and cross-sectional views (bottom/left) of an exemplary semiconductor structure 700 according to some embodiments. The forming of the semiconductor structure 700 includes forming a plurality of openings 740 extended through the first dielectric layer 106 with a conjunction of spacer masks 522/524/524e and the blocked region 630 formed by the second mask.)
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Ann. Fig. 7
wherein the first dielectric element (106-1), the second dielectric element (106-2), the third dielectric element (106-3), and the fourth dielectric element (106-4) are parts of the dielectric layer (106); (See Amm. Fig. 7, showing the first (106-1), second (106-2), third (106-3), and fourth (106-4) dielectric elements are formed of the remaining portion of the dielectric layer 106)
removing the first spacer (522), the second spacer (522), the third spacer (522), and the fourth spacer (522) from the first dielectric element (106-1), the second dielectric element (106-1), the third dielectric element (106-1), and the fourth dielectric element (106-1), respectively; ([0074] wherein the spacer masks 522/524/524e and the second mask are removed and the top surfaces of the first dielectric layer are exposed.)
forming a first shielding line ([0075] disposing an objective material in the openings 840 (in FIG. 8) and forming objective lines 950; SH-1 in Ann. Fig. 9A) between the second dielectric element (106-2) and the third dielectric element (106-3), (See Ann. Fig. 9A, showing the first shielding line SH-1 between the second dielectric element 106-2 and the third dielectric element 106-3)
wherein the first shielding line (SH-1) is in direct contact with the substrate (104); (See Ann. Fig. 9A)
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Ann. Fig. 9A
and forming a first signal line ([0075] disposing an objective material in the openings 840 (in FIG. 8) and forming objective lines 950; SL-1 in Ann. Fig. 9A) between the first dielectric element (106-1) and the second dielectric element (106-2), (See Ann. Fig. 9A)
and forming a second signal line ([0075] disposing an objective material in the openings 840 (in FIG. 8) and forming objective lines 950; SL-2 in Ann. Fig. 9A) between the third dielectric element (106-3) and the fourth dielectric element (106-4), wherein the first shielding line is deposited between the first signal line and the second signal line,
wherein the first signal line (SL-1) and the second signal line (SL-2) are in direct contact with the substrate (104) and the conductive elements (980); (See Fig. 9B, showing the objective line 950 in direct contact with the conductive structure 980 and the insulating layer 104)
wherein the first shielding line (SH-1), the first signal line (SL-1) and the second signal line (SL-2) include polysilicon, aluminum, magnesium, tungsten, or lanthanum. ([0076] The objective material for objective lines 950/960 can include a semiconductor or a conductor. The conductor can include tungsten, cobalt, copper, or aluminum. The semiconductor can include silicon, silicon germanium, polycrystalline silicon, polycrystalline silicon germanium, amorphous silicon, amorphous silicon germanium, with or without doping.)
However, Fan fails to disclose wherein the first signal line (SL-1) and the second signal line (SL-2) form electrically conductive interconnects to the conductive elements (980), respectively, while the first shielding line (SH-1) forms no electrically conductive interconnect to the conductive elements (980),
Roehner discloses (as shown in Fig. 13C) a substrate ([0083] semiconductor chips 320) in which conductive elements ([0083] contact pads 330) are formed ([0083] a plurality of semiconductor chips 320 having a plurality of contact pads 330)
wherein the first signal line ([0093] first redistribution metal line 410; [0087] The conductive liner 360 may include an adhesion layer, a barrier layer, and/or a seed layer) and the second signal line ([0093] second redistribution metal line 430; [0087] The conductive liner 360 may include an adhesion layer, a barrier layer, and/or a seed layer) form electrically conductive interconnects to the conductive elements (330), respectively, (See Fig. 13C, showing the conductive liner 360 under the first 410 and second 430 redistribution metal lines connected to the contact pads 330)
while the first shielding line ([0093] shield redistribution line 420) forms no electrically conductive interconnect to the conductive elements (330). (See Fig. 13C, showing no connection between the conductive liner 360 under the redistribution shield line 420 and the contact pads 330)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the application to combine the teachings of Fan and Roehner. Fan teaches the substrate (104) containing conductive elements ([0075] In some embodiments, the insulating layer 104 of the semiconductor structure 900/901 can include one or more conductive structures (e.g., a conductive structure 980 shown in FIG. 9B in a cross-sectional view along a line 102), in contact with the objective lines 950/960) but does not describe how the conductive elements (980) are arranged. Roehner teaches a structure with signal lines ([0090] a first redistribution metal line 410, a second redistribution metal line 430) and shield lines ([0090] a shield redistribution line 420). Roehner teaches that the shield lines are test structures to identify defects ([0041] Rather, the shield lines are test structures to identify defects introduced during processing.)
Roehner further teaches that the signal lines (410, 430) are coupled to functional circuitry in the substrate. ([0006] the substrate comprising functional circuitry of a semiconductor device…The first metal line is coupled to the functional circuitry and is configured to be coupled to a high voltage node during operation) It would have been obvious before the effective filing date for the first signal line (410) and the second signal line (430) to form electrically conductive interconnects to the conductive element (330) in order to couple the signal lines (410, 430) to the functional circuitry.
Roehner further teaches that the shield lines may not be coupled to any other circuit of the semiconductor device ([0069] Further, as described in prior embodiments, the shield lines 20 may not be coupled (electrically, inductively, capacitively, and resistively) to any other circuit of the semiconductor device.) so that any current measured in the shield line is leakage current ([0050] Because the shield line 20 is not coupled to any other circuit in the device, the current flowing through the shield line 20 is indicative of leakage current associated with the extrinsic breakdown of the isolation 25 between the first metal line 10 and the shield line 20.) It would have been obvious before the effective filing date to not have conductive element (contact pads 330) connected to the shield lines (420) so that leakage current can be measured by measuring the current of the shield lines (420).
Regarding Claim 3, Fan further discloses (as shown in Fig. 3) before forming the first spacer (422), the second spacer (422), the third spacer (422), and the fourth spacer (422), disposing a conformal spacer layer ([0058] The second dielectric layer 320) to cover the first mandrel (101) and the second mandrel (101). ([0058] The second dielectric layer 320 includes a thickness “d.sub.1” on sidewalls of the mandrel lines 101…in this example, the dielectric spacer is “conformal” to the mandrel lines 101)
Regarding Claim 4, Fan further discloses (as shown in Fig. 4) partially removing the conformal spacer layer (320) to form the first spacer (422), the second spacer (422), the third spacer (422), and the fourth spacer (422). ([0059] The forming of the dielectric spacers 422/424/424e includes an anisotropic etching process, such as RIE)
Regarding Claim 5, Fan further discloses (as shown in Fig. 4) wherein the minimum width of each of the first spacer (422), the second spacer (422), the third spacer (422), and the fourth spacer (422) is between 10 nm and 40 nm. ([0081] Width “d6” of spacer masks can also be chosen as 20 nm…the alignment tolerance at lithography process can be as small as 10 nm.)
Regarding Claim 6, Fan further discloses (as shown in Fig. 5) removing the first mandrel (101) and the second mandrel (101) from the dielectric layer (106) before etching the dielectric layer (106). ([0088] At process step 1050, the mandrel lines and discontinuous mandrel line pairs are removed to form stand-alone dielectric spacers or spacer masks.)
Regarding Claim 7, Fan further discloses (as shown in Fig. 8) wherein the minimum width of each of the first dielectric element (106-1), the second dielectric element (106-2), the third dielectric element (106-3), and the fourth dielectric element (106-4) is between 10 nm and 40 nm. (See Fig. 8, showing the dielectric layer in lines with width d6; [0081] Width “d6” of spacer masks can also be chosen as 20 nm…the alignment tolerance at lithography process can be as small as 10 nm.)
Regarding Claim 8, Fan discloses (as shown in Fig. 9A) wherein forming the first signal line (SL-1) and the second signal line (SL-2) comprises: disposing a conductive layer to cover the first dielectric element (106-1), the second dielectric element (106-2), the third dielectric element (106-3), and the fourth dielectric element (106-4) ([0075] The forming of the semiconductor structures 900 and 901 include disposing an objective material in the openings 840 (in FIG. 8) and forming objective lines 950 and discontinuous line pairs 960 with top surfaces 950s coplanar with the top surface 106s of the first dielectric layer 106, wherein the forming of coplanar surfaces includes a planarization process such as chemical mechanical polishing.)
Regarding Claim 9, Fan discloses (as shown in Ann. Fig. 9A) partially removing the conductive layer (950) to form the first signal line (SL-1) and the second signal line (SL-2). ([0075] The forming of the semiconductor structures 900 and 901 include disposing an objective material in the openings 840 (in FIG. 8) and forming objective lines 950 and discontinuous line pairs 960 with top surfaces 950s coplanar with the top surface 106s of the first dielectric layer 106, wherein the forming of coplanar surfaces includes a planarization process such as chemical mechanical polishing.)
Regarding Claim 10, Fan further discloses (as shown in Fig. 9A) wherein the minimum width of the first shielding line (SH-1) is between 10 nm and 70 nm. ([0078] In some embodiments, the objective lines 950 and discontinuous line pairs 960 include a width “a.sub.6” or “c.sub.6” in a range between about 5 nm to 40 nm, about 10 nm to about 35 nm, about 15 nm to about 30 nm, about 19 nm to about 29 nm, or the like)
Regarding Claim 11, Fan further discloses (as shown in Ann. Fig. 9A) forming a second shielding line (SH-2), wherein the first signal line (SL-1) is disposed between the first shielding line (SH-1) and the second shielding line (SH-2). (See Ann. Fig. 9A, showing the first signal line SL-1 between the first shielding line SH-1 and the second shielding line SH-2)
Regarding Claim 13, Fan further discloses (as shown in Ann. Fig. 9A) forming a third shielding line (SH-3), wherein the second signal line (SL-2) is disposed between the first shielding line (SH-1) and the third shielding line (SH-3). (See Ann. Fig. 9A, showing the second signal line SL-2 between the first shielding line SH-1 and the third shielding line SH-3)
Regarding Claim 15, Fan further discloses (as shown in Fig. 9A) wherein the first shielding line (SH-1), the second shielding line (SH-2), and the third shielding line (SH-3) are parallel. (See Fig. 9A, showing the objective lines 950 are parallel to each other)
Regarding Claim 16, Fan further discloses (as shown in Fig. 9A) forming the first dielectric element (106-1) contacting a first side (left) of the first signal line (SL-1);
and forming the second dielectric element (106-2) contacting a second side (right) of the first signal line (SL-1) opposite to the first side (left). (See Ann. Fig. 9A, showing the first dielectric element 106-1 on the left side of the first signal line SL-1 and the second dielectric element 106-2 on the right side of the first signal line SL-1)
Regarding Claim 17, Fan further discloses (as shown in Fig. 9A) wherein the minimum width of the first dielectric element (106-1) is equal to the minimum width of the second dielectric element (106-2). ([0074] The patterns of the spacer masks 522/524/524e and the blocked regions 630 can be transferred into the first dielectric layer 106) (See Fig. 9A)
Regarding Claim 18, Fan further discloses (as shown in Fig. 9A) wherein the first side (left) and the second side (right) of the first signal line (SL-1) are perpendicular to the surface of the substrate (104). (See Fig. 9A)
Claim(s) 12, 14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fan in view of Roehner as applied to Claim 11 above, and further in view of Li (US 2021/0249416 A1) (of record).
Regarding Claim 12, Fan in view of Roehner discloses all of the limitations of Claim 11 above. However, Fan in view of Roehner fails to disclose wherein the first shielding line (SH-1) is electrically connected with the second shielding line (SH-2).
Li discloses (as shown in Fig. 5) wherein the first shielding line (SH-2) is electrically connected with the second shielding line (SH-1). ([0041] the shield lines (58, 60) are electrically coupled with a first reference voltage. See Fig. 5, showing the shielding lines being electrically connected)
It would have been obvious to one having ordinary skill in the art before the effective filing date to connect the shield lines to the reference potential in order for the current induced in the shielding lines to be dissipated. Therefore, it would have been obvious to connect the shielding lines to the reference potential, making them electrically connected.
Regarding Claim 14, Li further discloses (as shown in Fig. 5) wherein the first shielding line (SH-2) is electrically connected with the third shielding line (SH-3). [0041] the shield lines (58, 60) are electrically coupled with a first reference voltage. See Fig. 5, showing the shielding lines being electrically connected)
Regarding Claim 20, Li further discloses that the second shielding line (SH-1) is a dummy line ([0041] the shield lines (58, 60) are electrically coupled with a first reference voltage. See Fig. 5, showing the shielding lines being electrically connected)
Claim 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fan in view of Roehner as applied to Claim 1 above, and further in view of Li (US 2021/0249416A1) (of record).
Regarding Claim 19, Li further discloses that the first shielding line (SH-2) is a dummy line ([0041] the shield lines (58, 60) are electrically coupled with a first reference voltage. See Fig. 5, showing the shielding lines being electrically connected)
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 on Pages 9-10 of Applicant’s remarks have been considered but are moot because of the new ground of rejection provided above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Huang et. al (US 2020/0075405 A1) (newly cited):
Huang discloses (as shown in Figs. 7-11) A method of manufacturing a semiconductor device consisting of conductive lines ([0043] FIG. 11 also illustrates the formation of conductive vias 64A, 64B, and 64C (collectively referred to as vias 64) in openings in the target layer 28 (of FIG. 10). Conductive lines 66A, 66B, and 66C (collectively referred to as lines 66) are also formed in the trenches of target layer 28) formed on a substrate ([0014] a dielectric layer 22) with conductive elements ([0014] conductive features 24) formed in the substrate (22) ([0014] Metallization structure 21 is formed over substrate 10. Metallization structure 21 includes a dielectric layer 22 with conductive features 24 formed therein.) and the conductive lines (64, 66) are connected to the conductive elements (24). (See Fig. 11 showing conductive lines 64,66 connected to the conductive features 24)
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.J.G./Examiner, Art Unit 2893
/Britt D Hanley/Supervisory Patent Examiner, Art Unit 2893